0001
0002
0003
0004 #include "../wifi.h"
0005 #include "phy_common.h"
0006 #include "../rtl8723ae/reg.h"
0007 #include <linux/module.h>
0008
0009
0010
0011 u32 rtl8723_phy_query_bb_reg(struct ieee80211_hw *hw,
0012 u32 regaddr, u32 bitmask)
0013 {
0014 struct rtl_priv *rtlpriv = rtl_priv(hw);
0015 u32 returnvalue, originalvalue, bitshift;
0016
0017 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0018 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
0019 originalvalue = rtl_read_dword(rtlpriv, regaddr);
0020 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
0021 returnvalue = (originalvalue & bitmask) >> bitshift;
0022
0023 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0024 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask,
0025 regaddr, originalvalue);
0026 return returnvalue;
0027 }
0028 EXPORT_SYMBOL_GPL(rtl8723_phy_query_bb_reg);
0029
0030 void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
0031 u32 bitmask, u32 data)
0032 {
0033 struct rtl_priv *rtlpriv = rtl_priv(hw);
0034 u32 originalvalue, bitshift;
0035
0036 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0037 "regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr, bitmask,
0038 data);
0039
0040 if (bitmask != MASKDWORD) {
0041 originalvalue = rtl_read_dword(rtlpriv, regaddr);
0042 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
0043 data = ((originalvalue & (~bitmask)) | (data << bitshift));
0044 }
0045
0046 rtl_write_dword(rtlpriv, regaddr, data);
0047
0048 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0049 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
0050 regaddr, bitmask, data);
0051 }
0052 EXPORT_SYMBOL_GPL(rtl8723_phy_set_bb_reg);
0053
0054 u32 rtl8723_phy_calculate_bit_shift(u32 bitmask)
0055 {
0056 u32 i = ffs(bitmask);
0057
0058 return i ? i - 1 : 32;
0059 }
0060 EXPORT_SYMBOL_GPL(rtl8723_phy_calculate_bit_shift);
0061
0062 u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw,
0063 enum radio_path rfpath, u32 offset)
0064 {
0065 struct rtl_priv *rtlpriv = rtl_priv(hw);
0066 struct rtl_phy *rtlphy = &(rtlpriv->phy);
0067 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
0068 u32 newoffset;
0069 u32 tmplong, tmplong2;
0070 u8 rfpi_enable = 0;
0071 u32 retvalue;
0072
0073 offset &= 0xff;
0074 newoffset = offset;
0075 if (RT_CANNOT_IO(hw)) {
0076 pr_err("return all one\n");
0077 return 0xFFFFFFFF;
0078 }
0079 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
0080 if (rfpath == RF90_PATH_A)
0081 tmplong2 = tmplong;
0082 else
0083 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
0084 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
0085 (newoffset << 23) | BLSSIREADEDGE;
0086 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
0087 tmplong & (~BLSSIREADEDGE));
0088 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
0089 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
0090 tmplong | BLSSIREADEDGE);
0091 udelay(120);
0092 if (rfpath == RF90_PATH_A)
0093 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
0094 BIT(8));
0095 else if (rfpath == RF90_PATH_B)
0096 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
0097 BIT(8));
0098 if (rfpi_enable)
0099 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
0100 BLSSIREADBACKDATA);
0101 else
0102 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
0103 BLSSIREADBACKDATA);
0104 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0105 "RFR-%d Addr[0x%x]=0x%x\n",
0106 rfpath, pphyreg->rf_rb, retvalue);
0107 return retvalue;
0108 }
0109 EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_read);
0110
0111 void rtl8723_phy_rf_serial_write(struct ieee80211_hw *hw,
0112 enum radio_path rfpath,
0113 u32 offset, u32 data)
0114 {
0115 u32 data_and_addr;
0116 u32 newoffset;
0117 struct rtl_priv *rtlpriv = rtl_priv(hw);
0118 struct rtl_phy *rtlphy = &(rtlpriv->phy);
0119 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
0120
0121 if (RT_CANNOT_IO(hw)) {
0122 pr_err("stop\n");
0123 return;
0124 }
0125 offset &= 0xff;
0126 newoffset = offset;
0127 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
0128 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
0129 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0130 "RFW-%d Addr[0x%x]=0x%x\n",
0131 rfpath, pphyreg->rf3wire_offset,
0132 data_and_addr);
0133 }
0134 EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_write);
0135
0136 long rtl8723_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
0137 enum wireless_mode wirelessmode,
0138 u8 txpwridx)
0139 {
0140 long offset;
0141 long pwrout_dbm;
0142
0143 switch (wirelessmode) {
0144 case WIRELESS_MODE_B:
0145 offset = -7;
0146 break;
0147 case WIRELESS_MODE_G:
0148 case WIRELESS_MODE_N_24G:
0149 offset = -8;
0150 break;
0151 default:
0152 offset = -8;
0153 break;
0154 }
0155 pwrout_dbm = txpwridx / 2 + offset;
0156 return pwrout_dbm;
0157 }
0158 EXPORT_SYMBOL_GPL(rtl8723_phy_txpwr_idx_to_dbm);
0159
0160 void rtl8723_phy_init_bb_rf_reg_def(struct ieee80211_hw *hw)
0161 {
0162 struct rtl_priv *rtlpriv = rtl_priv(hw);
0163 struct rtl_phy *rtlphy = &(rtlpriv->phy);
0164
0165 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
0166 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
0167 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
0168 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
0169
0170 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
0171 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
0172 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
0173 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
0174
0175 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
0176 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
0177
0178 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
0179 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
0180
0181 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
0182 RFPGA0_XA_LSSIPARAMETER;
0183 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
0184 RFPGA0_XB_LSSIPARAMETER;
0185
0186 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
0187 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
0188 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
0189 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
0190
0191 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0192 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0193 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0194 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0195
0196 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
0197 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
0198
0199 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
0200 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
0201
0202 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
0203 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
0204 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
0205 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
0206
0207 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
0208 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
0209 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
0210 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
0211
0212 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
0213 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
0214 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
0215 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
0216
0217 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
0218 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
0219 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
0220 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
0221
0222 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
0223 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
0224 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
0225 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
0226
0227 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
0228 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
0229 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
0230 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
0231
0232 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
0233 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
0234 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
0235 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
0236
0237 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
0238 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
0239 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
0240 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
0241
0242 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
0243 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
0244
0245 }
0246 EXPORT_SYMBOL_GPL(rtl8723_phy_init_bb_rf_reg_def);
0247
0248 bool rtl8723_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
0249 u32 cmdtableidx,
0250 u32 cmdtablesz,
0251 enum swchnlcmd_id cmdid,
0252 u32 para1, u32 para2,
0253 u32 msdelay)
0254 {
0255 struct swchnlcmd *pcmd;
0256
0257 if (cmdtable == NULL) {
0258 WARN_ONCE(true, "rtl8723-common: cmdtable cannot be NULL.\n");
0259 return false;
0260 }
0261
0262 if (cmdtableidx >= cmdtablesz)
0263 return false;
0264
0265 pcmd = cmdtable + cmdtableidx;
0266 pcmd->cmdid = cmdid;
0267 pcmd->para1 = para1;
0268 pcmd->para2 = para2;
0269 pcmd->msdelay = msdelay;
0270 return true;
0271 }
0272 EXPORT_SYMBOL_GPL(rtl8723_phy_set_sw_chnl_cmdarray);
0273
0274 void rtl8723_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
0275 bool iqk_ok,
0276 long result[][8],
0277 u8 final_candidate,
0278 bool btxonly)
0279 {
0280 u32 oldval_0, x, tx0_a, reg;
0281 long y, tx0_c;
0282
0283 if (final_candidate == 0xFF) {
0284 return;
0285 } else if (iqk_ok) {
0286 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
0287 MASKDWORD) >> 22) & 0x3FF;
0288 x = result[final_candidate][0];
0289 if ((x & 0x00000200) != 0)
0290 x = x | 0xFFFFFC00;
0291 tx0_a = (x * oldval_0) >> 8;
0292 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
0293 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
0294 ((x * oldval_0 >> 7) & 0x1));
0295 y = result[final_candidate][1];
0296 if ((y & 0x00000200) != 0)
0297 y = y | 0xFFFFFC00;
0298 tx0_c = (y * oldval_0) >> 8;
0299 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
0300 ((tx0_c & 0x3C0) >> 6));
0301 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
0302 (tx0_c & 0x3F));
0303 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
0304 ((y * oldval_0 >> 7) & 0x1));
0305 if (btxonly)
0306 return;
0307 reg = result[final_candidate][2];
0308 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
0309 reg = result[final_candidate][3] & 0x3F;
0310 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
0311 reg = (result[final_candidate][3] >> 6) & 0xF;
0312 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
0313 }
0314 }
0315 EXPORT_SYMBOL_GPL(rtl8723_phy_path_a_fill_iqk_matrix);
0316
0317 void rtl8723_save_adda_registers(struct ieee80211_hw *hw, u32 *addareg,
0318 u32 *addabackup, u32 registernum)
0319 {
0320 u32 i;
0321
0322 for (i = 0; i < registernum; i++)
0323 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
0324 }
0325 EXPORT_SYMBOL_GPL(rtl8723_save_adda_registers);
0326
0327 void rtl8723_phy_save_mac_registers(struct ieee80211_hw *hw,
0328 u32 *macreg, u32 *macbackup)
0329 {
0330 struct rtl_priv *rtlpriv = rtl_priv(hw);
0331 u32 i;
0332
0333 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
0334 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
0335 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
0336 }
0337 EXPORT_SYMBOL_GPL(rtl8723_phy_save_mac_registers);
0338
0339 void rtl8723_phy_reload_adda_registers(struct ieee80211_hw *hw,
0340 u32 *addareg, u32 *addabackup,
0341 u32 regiesternum)
0342 {
0343 u32 i;
0344
0345 for (i = 0; i < regiesternum; i++)
0346 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
0347 }
0348 EXPORT_SYMBOL_GPL(rtl8723_phy_reload_adda_registers);
0349
0350 void rtl8723_phy_reload_mac_registers(struct ieee80211_hw *hw,
0351 u32 *macreg, u32 *macbackup)
0352 {
0353 struct rtl_priv *rtlpriv = rtl_priv(hw);
0354 u32 i;
0355
0356 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
0357 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
0358 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
0359 }
0360 EXPORT_SYMBOL_GPL(rtl8723_phy_reload_mac_registers);
0361
0362 void rtl8723_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg,
0363 bool is_patha_on, bool is2t)
0364 {
0365 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0366 u32 pathon;
0367 u32 i;
0368
0369 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
0370 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
0371 if (!is2t) {
0372 pathon = 0x0bdb25a0;
0373 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
0374 } else {
0375 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
0376 }
0377 } else {
0378
0379 pathon = 0x01c00014;
0380 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
0381 }
0382
0383 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
0384 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
0385 }
0386 EXPORT_SYMBOL_GPL(rtl8723_phy_path_adda_on);
0387
0388 void rtl8723_phy_mac_setting_calibration(struct ieee80211_hw *hw,
0389 u32 *macreg, u32 *macbackup)
0390 {
0391 struct rtl_priv *rtlpriv = rtl_priv(hw);
0392 u32 i = 0;
0393
0394 rtl_write_byte(rtlpriv, macreg[i], 0x3F);
0395
0396 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
0397 rtl_write_byte(rtlpriv, macreg[i],
0398 (u8) (macbackup[i] & (~BIT(3))));
0399 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
0400 }
0401 EXPORT_SYMBOL_GPL(rtl8723_phy_mac_setting_calibration);
0402
0403 void rtl8723_phy_path_a_standby(struct ieee80211_hw *hw)
0404 {
0405 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
0406 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
0407 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
0408 }
0409 EXPORT_SYMBOL_GPL(rtl8723_phy_path_a_standby);
0410
0411 void rtl8723_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
0412 {
0413 u32 mode;
0414
0415 mode = pi_mode ? 0x01000100 : 0x01000000;
0416 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
0417 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
0418 }
0419 EXPORT_SYMBOL_GPL(rtl8723_phy_pi_mode_switch);
