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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2014  Realtek Corporation.*/
0003 
0004 #ifndef __RTL8723BE_PWRSEQ_H__
0005 #define __RTL8723BE_PWRSEQ_H__
0006 
0007 #include "../pwrseqcmd.h"
0008 /**
0009  *  Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd
0010  *  There are 6 HW Power States:
0011  *  0: POFF--Power Off
0012  *  1: PDN--Power Down
0013  *  2: CARDEMU--Card Emulation
0014  *  3: ACT--Active Mode
0015  *  4: LPS--Low Power State
0016  *  5: SUS--Suspend
0017  *
0018  *  The transision from different states are defined below
0019  *  TRANS_CARDEMU_TO_ACT
0020  *  TRANS_ACT_TO_CARDEMU
0021  *  TRANS_CARDEMU_TO_SUS
0022  *  TRANS_SUS_TO_CARDEMU
0023  *  TRANS_CARDEMU_TO_PDN
0024  *  TRANS_ACT_TO_LPS
0025  *  TRANS_LPS_TO_ACT
0026  *
0027  *  TRANS_END
0028  */
0029 #define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS 23
0030 #define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS 15
0031 #define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS 15
0032 #define RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS 15
0033 #define RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS 15
0034 #define RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS 15
0035 #define RTL8723B_TRANS_ACT_TO_LPS_STEPS     15
0036 #define RTL8723B_TRANS_LPS_TO_ACT_STEPS     15
0037 #define RTL8723B_TRANS_END_STEPS        1
0038 
0039 #define RTL8723B_TRANS_CARDEMU_TO_ACT                   \
0040     /* format */                            \
0041     /* comments here */                     \
0042     /* {offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value}, */\
0043     /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/  \
0044     {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0045      PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,              \
0046      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},      \
0047     /*0x67[0] = 0 to disable BT_GPS_SEL pins*/          \
0048     {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0049      PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,              \
0050      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},           \
0051     /*Delay 1ms*/                           \
0052     {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0053      PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,              \
0054      PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},      \
0055     /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
0056     {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0057      PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,              \
0058      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0},           \
0059     /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/      \
0060     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0061      PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0},   \
0062     /* Disable USB suspend */                   \
0063     {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0064      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)},     \
0065     /* wait till 0x04[17] = 1    power ready*/          \
0066     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0067      PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},        \
0068     /* Enable USB suspend */                    \
0069     {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0070      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0},          \
0071     /* release WLON reset  0x04[16]=1*/             \
0072     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0073      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},      \
0074     /* disable HWPDN 0x04[15]=0*/                   \
0075     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0076      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},           \
0077     /* disable WL suspend*/                     \
0078     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0079      PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},      \
0080     /* polling until return 0*/                 \
0081     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0082      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},      \
0083     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0084      PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},         \
0085     /* Enable WL control XTAL setting*/             \
0086     {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0087      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},      \
0088     /*Enable falling edge triggering interrupt*/            \
0089     {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0090      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},      \
0091     /*Enable GPIO9 interrupt mode*/                 \
0092     {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0093      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},      \
0094     /*Enable GPIO9 input mode*/                 \
0095     {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0096      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},           \
0097     /*Enable HSISR GPIO[C:0] interrupt*/                \
0098     {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0099      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},      \
0100     /*Enable HSISR GPIO9 interrupt*/                \
0101     {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0102      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},      \
0103     /*For GPIO9 internal pull high setting by test chip*/       \
0104     {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0105      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)},      \
0106     /*For GPIO9 internal pull high setting*/            \
0107     {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0108      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},
0109 
0110 #define RTL8723B_TRANS_ACT_TO_CARDEMU                   \
0111     /* format */                            \
0112     /* comments here */                     \
0113     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
0114     /*0x1F[7:0] = 0 turn off RF*/                   \
0115     {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0116      PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},         \
0117     /*0x4C[24] = 0x4F[0] = 0, */                    \
0118     /*switch DPDT_SEL_P output from register 0x65[2] */     \
0119     {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0120      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},           \
0121     /*Enable rising edge triggering interrupt*/         \
0122     {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0123      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},           \
0124      /*0x04[9] = 1 turn off MAC by HW state machine*/       \
0125     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0126      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},      \
0127      /*wait till 0x04[9] = 0 polling until return 0 to disable*/    \
0128     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0129      PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},         \
0130     /* Enable BT control XTAL setting*/             \
0131     {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0132      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0},           \
0133     /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/       \
0134     {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0135      PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,    \
0136      PWR_CMD_WRITE, BIT(5), BIT(5)},                \
0137     /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/           \
0138     {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0139      PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,    \
0140      PWR_CMD_WRITE, BIT(0), 0},
0141 
0142 #define RTL8723B_TRANS_CARDEMU_TO_SUS                   \
0143     /* format */                            \
0144     /* comments here */                     \
0145     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
0146     /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/      \
0147     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0148      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \
0149     /*0x04[12:11] = 2b'01 enable WL suspend*/           \
0150     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0151      PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,    \
0152      PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},           \
0153     /*0x23[4] = 1b'1 12H LDO enter sleep mode*/         \
0154     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0155      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},      \
0156     /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
0157     {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0158      PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20},          \
0159     /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/      \
0160     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0161      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
0162     /*Set SDIO suspend local register*/             \
0163     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0164      PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},     \
0165     /*wait power state to suspend*/                 \
0166     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0167      PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
0168 
0169 #define RTL8723B_TRANS_SUS_TO_CARDEMU                   \
0170     /* format */                            \
0171     /* comments here */                     \
0172     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
0173     /*clear suspend enable and power down enable*/          \
0174     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0175      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0},      \
0176     /*Set SDIO suspend local register*/             \
0177     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0178      PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},          \
0179     /*wait power state to suspend*/                 \
0180     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0181      PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},       \
0182     /*0x23[4] = 1b'0 12H LDO enter normal mode*/            \
0183     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0184      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},           \
0185     /*0x04[12:11] = 2b'00 disable WL suspend*/          \
0186     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0187      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
0188 
0189 #define RTL8723B_TRANS_CARDEMU_TO_CARDDIS               \
0190     /* format */                            \
0191     /* comments here */                     \
0192     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
0193     /*0x07=0x20 , SOP option to disable BG/MB*/         \
0194     {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0195      PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20},          \
0196     /*0x04[12:11] = 2b'01 enable WL suspend*/           \
0197     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0198      PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,              \
0199      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},   \
0200     /*0x04[10] = 1, enable SW LPS*/                 \
0201     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0202      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)},      \
0203     /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/          \
0204     {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
0205      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1},           \
0206     /*0x23[4] = 1b'1 12H LDO enter sleep mode*/         \
0207     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0208      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},      \
0209     /*Set SDIO suspend local register*/             \
0210     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0211      PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},     \
0212     /*wait power state to suspend*/                 \
0213     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0214      PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
0215 
0216 #define RTL8723B_TRANS_CARDDIS_TO_CARDEMU               \
0217     /* format */                            \
0218     /* comments here */                     \
0219     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
0220     /*clear suspend enable and power down enable*/          \
0221     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0222      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0},      \
0223     /*Set SDIO suspend local register*/             \
0224     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0225      PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},          \
0226     /*wait power state to suspend*/                 \
0227     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0228      PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},       \
0229     /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/         \
0230     {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
0231      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},           \
0232     /*0x04[12:11] = 2b'00 disable WL suspend*/          \
0233     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0234      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},        \
0235     /*0x23[4] = 1b'0 12H LDO enter normal mode*/            \
0236     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0237      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},           \
0238     /*PCIe DMA start*/                      \
0239     {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0240      PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
0241 
0242 #define RTL8723B_TRANS_CARDEMU_TO_PDN                   \
0243     /* format */                            \
0244     /* comments here */                     \
0245     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
0246     /*0x23[4] = 1b'1 12H LDO enter sleep mode*/         \
0247     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0248      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},      \
0249     /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/    \
0250     {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0251      PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC,    \
0252      PWR_CMD_WRITE, 0xFF, 0x20},                    \
0253     /* 0x04[16] = 0*/                       \
0254     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0255      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},           \
0256     /* 0x04[15] = 1*/                       \
0257     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0258      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},
0259 
0260 #define RTL8723B_TRANS_PDN_TO_CARDEMU                   \
0261     /* format */                            \
0262     /* comments here */                     \
0263     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
0264     /* 0x04[15] = 0*/                       \
0265     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0266      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},
0267 
0268 #define RTL8723B_TRANS_ACT_TO_LPS                   \
0269     /* format */                            \
0270     /* comments here */                     \
0271     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
0272     /*PCIe DMA stop*/                       \
0273     {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0274      PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},          \
0275     /*Tx Pause*/                            \
0276     {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0277      PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},          \
0278     /*Should be zero if no packet is transmitting*/         \
0279     {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0280      PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},           \
0281     /*Should be zero if no packet is transmitting*/         \
0282     {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0283      PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},           \
0284     /*Should be zero if no packet is transmitting*/         \
0285     {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0286      PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},           \
0287     /*Should be zero if no packet is transmitting*/         \
0288     {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0289      PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},           \
0290     /*CCK and OFDM are disabled,and clock are gated*/       \
0291     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0292      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},           \
0293     /*Delay 1us*/                           \
0294     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0295      PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},      \
0296     /*Whole BB is reset*/                       \
0297     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0298      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},           \
0299     /*Reset MAC TRX*/                       \
0300     {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0301      PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},          \
0302     /*check if removed later*/                  \
0303     {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0304      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},           \
0305     /*When driver enter Sus/ Disable, enable LOP for BT*/       \
0306     {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0307      PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},          \
0308     /*Respond TxOK to scheduler*/                   \
0309     {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0310      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},
0311 
0312 #define RTL8723B_TRANS_LPS_TO_ACT                   \
0313     /* format */                            \
0314     /* comments here */                     \
0315     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
0316     /*SDIO RPWM*/                           \
0317     {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0318      PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84},         \
0319     /*USB RPWM*/                            \
0320     {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
0321      PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84},          \
0322     /*PCIe RPWM*/                           \
0323     {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0324      PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84},          \
0325     /*Delay*/                           \
0326     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0327      PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS},      \
0328     /*. 0x08[4] = 0      switch TSF to 40M*/        \
0329     {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0330      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},           \
0331     /*Polling 0x109[7]=0  TSF in 40M*/              \
0332     {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0333      PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0},         \
0334     /*. 0x29[7:6] = 2b'00    enable BB clock*/      \
0335     {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0336      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0},        \
0337     /*. 0x101[1] = 1*/                      \
0338     {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0339      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},      \
0340     /*. 0x100[7:0] = 0xFF    enable WMAC TRX*/      \
0341     {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0342      PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},          \
0343     /*. 0x02[1:0] = 2b'11    enable BB macro*/      \
0344     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0345      PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
0346     /*. 0x522 = 0*/                     \
0347     {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0348      PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
0349 
0350 #define RTL8723B_TRANS_END                      \
0351     /* format */                            \
0352     /* comments here */                     \
0353     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
0354     {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, \
0355      PWR_CMD_END, 0, 0},
0356 
0357 extern struct wlan_pwr_cfg rtl8723B_power_on_flow
0358                 [RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS +
0359                  RTL8723B_TRANS_END_STEPS];
0360 extern struct wlan_pwr_cfg rtl8723B_radio_off_flow
0361                 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
0362                  RTL8723B_TRANS_END_STEPS];
0363 extern struct wlan_pwr_cfg rtl8723B_card_disable_flow
0364                 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
0365                  RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
0366                  RTL8723B_TRANS_END_STEPS];
0367 extern struct wlan_pwr_cfg rtl8723B_card_enable_flow
0368                 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
0369                  RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
0370                  RTL8723B_TRANS_END_STEPS];
0371 extern struct wlan_pwr_cfg rtl8723B_suspend_flow
0372                 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
0373                  RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS +
0374                  RTL8723B_TRANS_END_STEPS];
0375 extern struct wlan_pwr_cfg rtl8723B_resume_flow
0376                 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
0377                  RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS +
0378                  RTL8723B_TRANS_END_STEPS];
0379 extern struct wlan_pwr_cfg rtl8723B_hwpdn_flow
0380                 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
0381                  RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
0382                  RTL8723B_TRANS_END_STEPS];
0383 extern struct wlan_pwr_cfg rtl8723B_enter_lps_flow
0384                 [RTL8723B_TRANS_ACT_TO_LPS_STEPS +
0385                  RTL8723B_TRANS_END_STEPS];
0386 extern struct wlan_pwr_cfg rtl8723B_leave_lps_flow
0387                 [RTL8723B_TRANS_LPS_TO_ACT_STEPS +
0388                  RTL8723B_TRANS_END_STEPS];
0389 
0390 /* RTL8723 Power Configuration CMDs for PCIe interface */
0391 #define RTL8723_NIC_PWR_ON_FLOW     rtl8723B_power_on_flow
0392 #define RTL8723_NIC_RF_OFF_FLOW     rtl8723B_radio_off_flow
0393 #define RTL8723_NIC_DISABLE_FLOW    rtl8723B_card_disable_flow
0394 #define RTL8723_NIC_ENABLE_FLOW     rtl8723B_card_enable_flow
0395 #define RTL8723_NIC_SUSPEND_FLOW    rtl8723B_suspend_flow
0396 #define RTL8723_NIC_RESUME_FLOW     rtl8723B_resume_flow
0397 #define RTL8723_NIC_PDN_FLOW        rtl8723B_hwpdn_flow
0398 #define RTL8723_NIC_LPS_ENTER_FLOW  rtl8723B_enter_lps_flow
0399 #define RTL8723_NIC_LPS_LEAVE_FLOW  rtl8723B_leave_lps_flow
0400 
0401 #endif
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