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0002
0003
0004 #ifndef __RTL8723BE_PHY_H__
0005 #define __RTL8723BE_PHY_H__
0006
0007
0008
0009
0010 #define MAX_TX_COUNT 4
0011 #define TX_1S 0
0012 #define TX_2S 1
0013 #define TX_3S 2
0014 #define TX_4S 3
0015
0016 #define MAX_POWER_INDEX 0x3F
0017
0018 #define MAX_PRECMD_CNT 16
0019 #define MAX_RFDEPENDCMD_CNT 16
0020 #define MAX_POSTCMD_CNT 16
0021
0022 #define MAX_DOZE_WAITING_TIMES_9x 64
0023
0024 #define RT_CANNOT_IO(hw) false
0025 #define HIGHPOWER_RADIOA_ARRAYLEN 22
0026
0027 #define TARGET_CHNL_NUM_2G_5G 59
0028
0029 #define IQK_ADDA_REG_NUM 16
0030 #define IQK_BB_REG_NUM 9
0031 #define MAX_TOLERANCE 5
0032 #define IQK_DELAY_TIME 10
0033 #define index_mapping_NUM 15
0034
0035 #define APK_BB_REG_NUM 5
0036 #define APK_AFE_REG_NUM 16
0037 #define APK_CURVE_REG_NUM 4
0038 #define PATH_NUM 1
0039
0040 #define LOOP_LIMIT 5
0041 #define MAX_STALL_TIME 50
0042 #define ANTENNADIVERSITYVALUE 0x80
0043 #define MAX_TXPWR_IDX_NMODE_92S 63
0044 #define RESET_CNT_LIMIT 3
0045
0046 #define IQK_ADDA_REG_NUM 16
0047 #define IQK_MAC_REG_NUM 4
0048
0049 #define RF6052_MAX_PATH 2
0050
0051 #define CT_OFFSET_MAC_ADDR 0X16
0052
0053 #define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
0054 #define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
0055 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
0056 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
0057 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
0058
0059 #define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
0060 #define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
0061
0062 #define CT_OFFSET_CHANNEL_PLAH 0x75
0063 #define CT_OFFSET_THERMAL_METER 0x78
0064 #define CT_OFFSET_RF_OPTION 0x79
0065 #define CT_OFFSET_VERSION 0x7E
0066 #define CT_OFFSET_CUSTOMER_ID 0x7F
0067
0068 #define RTL92C_MAX_PATH_NUM 2
0069
0070 enum baseband_config_type {
0071 BASEBAND_CONFIG_PHY_REG = 0,
0072 BASEBAND_CONFIG_AGC_TAB = 1,
0073 };
0074
0075 enum ant_div_type {
0076 NO_ANTDIV = 0xFF,
0077 CG_TRX_HW_ANTDIV = 0x01,
0078 CGCS_RX_HW_ANTDIV = 0x02,
0079 FIXED_HW_ANTDIV = 0x03,
0080 CG_TRX_SMART_ANTDIV = 0x04,
0081 CGCS_RX_SW_ANTDIV = 0x05,
0082
0083 };
0084
0085 u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw,
0086 enum radio_path rfpath,
0087 u32 regaddr, u32 bitmask);
0088 void rtl8723be_phy_set_rf_reg(struct ieee80211_hw *hw,
0089 enum radio_path rfpath,
0090 u32 regaddr, u32 bitmask, u32 data);
0091 bool rtl8723be_phy_mac_config(struct ieee80211_hw *hw);
0092 bool rtl8723be_phy_bb_config(struct ieee80211_hw *hw);
0093 bool rtl8723be_phy_rf_config(struct ieee80211_hw *hw);
0094 void rtl8723be_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
0095 void rtl8723be_phy_set_txpower_level(struct ieee80211_hw *hw,
0096 u8 channel);
0097 void rtl8723be_phy_scan_operation_backup(struct ieee80211_hw *hw,
0098 u8 operation);
0099 void rtl8723be_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
0100 void rtl8723be_phy_set_bw_mode(struct ieee80211_hw *hw,
0101 enum nl80211_channel_type ch_type);
0102 void rtl8723be_phy_sw_chnl_callback(struct ieee80211_hw *hw);
0103 u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw);
0104 void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw,
0105 bool b_recovery);
0106 void rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw);
0107 void rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
0108 bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
0109 enum radio_path rfpath);
0110 bool rtl8723be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
0111 bool rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw,
0112 enum rf_pwrstate rfpwr_state);
0113 #endif