0001
0002
0003
0004 #ifndef __RTL8723BE_DEF_H__
0005 #define __RTL8723BE_DEF_H__
0006
0007 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
0008 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
0009 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
0010
0011
0012 #define RX_MPDU_QUEUE 0
0013 #define CHIP_8723B (BIT(1) | BIT(2))
0014 #define NORMAL_CHIP BIT(3)
0015 #define CHIP_VENDOR_SMIC BIT(8)
0016
0017 #define EXT_VENDOR_ID (BIT(18) | BIT(19))
0018
0019 enum rtl_desc_qsel {
0020 QSLT_BK = 0x2,
0021 QSLT_BE = 0x0,
0022 QSLT_VI = 0x5,
0023 QSLT_VO = 0x7,
0024 QSLT_BEACON = 0x10,
0025 QSLT_HIGH = 0x11,
0026 QSLT_MGNT = 0x12,
0027 QSLT_CMD = 0x13,
0028 };
0029
0030 enum rtl_desc8723e_rate {
0031 DESC92C_RATE1M = 0x00,
0032 DESC92C_RATE2M = 0x01,
0033 DESC92C_RATE5_5M = 0x02,
0034 DESC92C_RATE11M = 0x03,
0035
0036 DESC92C_RATE6M = 0x04,
0037 DESC92C_RATE9M = 0x05,
0038 DESC92C_RATE12M = 0x06,
0039 DESC92C_RATE18M = 0x07,
0040 DESC92C_RATE24M = 0x08,
0041 DESC92C_RATE36M = 0x09,
0042 DESC92C_RATE48M = 0x0a,
0043 DESC92C_RATE54M = 0x0b,
0044
0045 DESC92C_RATEMCS0 = 0x0c,
0046 DESC92C_RATEMCS1 = 0x0d,
0047 DESC92C_RATEMCS2 = 0x0e,
0048 DESC92C_RATEMCS3 = 0x0f,
0049 DESC92C_RATEMCS4 = 0x10,
0050 DESC92C_RATEMCS5 = 0x11,
0051 DESC92C_RATEMCS6 = 0x12,
0052 DESC92C_RATEMCS7 = 0x13,
0053 DESC92C_RATEMCS8 = 0x14,
0054 DESC92C_RATEMCS9 = 0x15,
0055 DESC92C_RATEMCS10 = 0x16,
0056 DESC92C_RATEMCS11 = 0x17,
0057 DESC92C_RATEMCS12 = 0x18,
0058 DESC92C_RATEMCS13 = 0x19,
0059 DESC92C_RATEMCS14 = 0x1a,
0060 DESC92C_RATEMCS15 = 0x1b,
0061 };
0062 #endif