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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003 
0004 #ifndef __RTL8723E_PWRSEQ_H__
0005 #define __RTL8723E_PWRSEQ_H__
0006 
0007 #include "../pwrseqcmd.h"
0008 /*
0009  *  Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
0010  *  There are 6 HW Power States:
0011  *  0: POFF--Power Off
0012  *  1: PDN--Power Down
0013  *  2: CARDEMU--Card Emulation
0014  *  3: ACT--Active Mode
0015  *  4: LPS--Low Power State
0016  *  5: SUS--Suspend
0017  *
0018  *  The transision from different states are defined below
0019  *  TRANS_CARDEMU_TO_ACT
0020  *  TRANS_ACT_TO_CARDEMU
0021  *  TRANS_CARDEMU_TO_SUS
0022  *  TRANS_SUS_TO_CARDEMU
0023  *  TRANS_CARDEMU_TO_PDN
0024  *  TRANS_ACT_TO_LPS
0025  *  TRANS_LPS_TO_ACT
0026  *
0027  *  TRANS_END
0028  */
0029 
0030 #define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 10
0031 #define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 10
0032 #define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 10
0033 #define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 10
0034 #define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 10
0035 #define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 10
0036 #define RTL8723A_TRANS_ACT_TO_LPS_STEPS     15
0037 #define RTL8723A_TRANS_LPS_TO_ACT_STEPS     15
0038 #define RTL8723A_TRANS_END_STEPS        1
0039 
0040 /* format */
0041 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }*/
0042 
0043 #define RTL8723A_TRANS_CARDEMU_TO_ACT   \
0044     /* disable SW LPS 0x04[10]=0*/  \
0045     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0046         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
0047     /* wait till 0x04[17] = 1    power ready*/  \
0048     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0049         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\
0050     /* release WLON reset  0x04[16]=1*/ \
0051     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0052         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
0053     /* disable HWPDN 0x04[15]=0*/ \
0054     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0055         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
0056     /* disable WL suspend*/ \
0057     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0058         PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
0059     /* polling until return 0*/ \
0060     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0061         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
0062     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0063         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},
0064 
0065 /* format */
0066 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
0067 
0068 #define RTL8723A_TRANS_ACT_TO_CARDEMU   \
0069     /*0x1F[7:0] = 0 turn off RF*/ \
0070     {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0071         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},  \
0072     {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0073         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
0074     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0075         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
0076     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0077         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},
0078 
0079 /* format */
0080 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/
0081 #define RTL8723A_TRANS_CARDEMU_TO_SUS           \
0082         /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/  \
0083     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0084         PWR_BASEADDR_MAC, PWR_CMD_WRITE, \
0085         BIT(4)|BIT(3), (BIT(4)|BIT(3))},\
0086 /*0x04[12:11] = 2b'01 enable WL suspend*/   \
0087     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK| \
0088         PWR_INTF_SDIO_MSK,\
0089         PWR_BASEADDR_MAC, \
0090         PWR_CMD_WRITE, \
0091         BIT(3)|BIT(4), BIT(3)}, \
0092 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
0093     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0094         PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, \
0095         PWR_CMD_WRITE, BIT(3)|BIT(4), \
0096         BIT(3)|BIT(4)}, \
0097 /*Set SDIO suspend local register*/ \
0098     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0099         PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
0100         PWR_CMD_WRITE, BIT(0), BIT(0)}, \
0101 /*wait power state to suspend*/ \
0102     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0103         PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
0104         PWR_CMD_POLLING, BIT(1), 0},
0105 
0106 /* format */
0107 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
0108 
0109 #define RTL8723A_TRANS_SUS_TO_CARDEMU   \
0110  /*Set SDIO suspend local register*/    \
0111     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0112         PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\
0113  /*wait power state to suspend*/ \
0114     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0115         PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\
0116  /*0x04[12:11] = 2b'00 disable WL suspend*/ \
0117     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0118         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
0119 
0120 /* format */
0121 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
0122 
0123 #define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
0124  /*0x04[12:11] = 2b'01 enable WL suspend*/   \
0125     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0126         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
0127         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
0128 /*0x04[10] = 1, enable SW LPS*/ \
0129     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0130         PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
0131         PWR_CMD_WRITE, BIT(2), BIT(2)}, \
0132 /*Set SDIO suspend local register*/ \
0133     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0134         PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
0135         PWR_CMD_WRITE, BIT(0), BIT(0)}, \
0136  /*wait power state to suspend*/ \
0137     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0138         PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
0139         PWR_CMD_POLLING, BIT(1), 0},
0140 
0141 /* format */
0142 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
0143 
0144 #define RTL8723A_TRANS_CARDDIS_TO_CARDEMU\
0145 /*Set SDIO suspend local register*/ \
0146     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0147         PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
0148         PWR_CMD_WRITE, BIT(0), 0}, \
0149  /*wait power state to suspend*/ \
0150     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0151         PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
0152         PWR_CMD_POLLING, BIT(1), BIT(1)},\
0153  /*0x04[12:11] = 2b'00 disable WL suspend*/ \
0154     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0155         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0156         PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\
0157 /*PCIe DMA start*/ \
0158     {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0159         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0160         PWR_CMD_WRITE, 0xFF, 0},
0161 
0162 /* format */
0163 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
0164 #define RTL8723A_TRANS_CARDEMU_TO_PDN   \
0165     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0166         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0167         PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
0168     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0169         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0170         PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
0171 
0172 /* format */
0173 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
0174 #define RTL8723A_TRANS_PDN_TO_CARDEMU   \
0175     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0176         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0177         PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
0178 
0179 /* format */
0180 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
0181 
0182 #define RTL8723A_TRANS_ACT_TO_LPS   \
0183     {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0184         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0185         PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/    \
0186     {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0187         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0188         PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
0189     /*Should be zero if no packet is transmitting*/ \
0190     {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0191         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0192         PWR_CMD_POLLING, 0xFF, 0},\
0193     /*Should be zero if no packet is transmitting*/ \
0194     {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0195         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0196         PWR_CMD_POLLING, 0xFF, 0},\
0197     /*Should be zero if no packet is transmitting*/ \
0198     {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0199         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0200         PWR_CMD_POLLING, 0xFF, 0},\
0201     /*Should be zero if no packet is transmitting*/ \
0202     {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0203         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0204         PWR_CMD_POLLING, 0xFF, 0},\
0205     /*CCK and OFDM are disabled,and clock are gated*/ \
0206     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0207         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0208         PWR_CMD_WRITE, BIT(0), 0},\
0209     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0210         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0211         PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\
0212     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0213         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0214         PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \
0215     {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0216         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0217         PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/    \
0218     {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0219         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0220         PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/    \
0221     /*Respond TxOK to scheduler*/   \
0222     {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0223         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0224         PWR_CMD_WRITE, BIT(5), BIT(5)},\
0225 
0226 #define RTL8723A_TRANS_LPS_TO_ACT\
0227 /* format */    \
0228 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ \
0229     {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0230         PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
0231         PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
0232     {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0233         PWR_INTF_USB_MSK, PWR_BASEADDR_MAC,\
0234         PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
0235     {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0236         PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
0237         PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
0238     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0239         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0240         PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
0241     /*. 0x08[4] = 0      switch TSF to 40M*/\
0242     {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0243         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0244         PWR_CMD_WRITE, BIT(4), 0},  \
0245     /*Polling 0x109[7]=0  TSF in 40M*/\
0246     {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0247         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0248         PWR_CMD_POLLING, BIT(7), 0}, \
0249     /*. 0x29[7:6] = 2b'00    enable BB clock*/\
0250     {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0251         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0252         PWR_CMD_WRITE, BIT(6)|BIT(7), 0},\
0253      /*.    0x101[1] = 1*/\
0254     {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0255         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0256         PWR_CMD_WRITE, BIT(1), BIT(1)},\
0257      /*.    0x100[7:0] = 0xFF    enable WMAC TRX*/\
0258     {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0259         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0260         PWR_CMD_WRITE, 0xFF, 0xFF},\
0261      /*.    0x02[1:0] = 2b'11    enable BB macro*/\
0262     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0263         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0264         PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)},\
0265     {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
0266         PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
0267         PWR_CMD_WRITE, 0xFF, 0}, /*.    0x522 = 0*/
0268 
0269 /* format */
0270 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
0271 
0272 #define RTL8723A_TRANS_END \
0273     {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0274     0, PWR_CMD_END, 0, 0}
0275 
0276 extern struct wlan_pwr_cfg rtl8723A_power_on_flow
0277         [RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS +
0278          RTL8723A_TRANS_END_STEPS];
0279 extern struct wlan_pwr_cfg rtl8723A_radio_off_flow
0280         [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
0281          RTL8723A_TRANS_END_STEPS];
0282 extern struct wlan_pwr_cfg rtl8723A_card_disable_flow
0283         [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
0284          RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
0285          RTL8723A_TRANS_END_STEPS];
0286 extern struct wlan_pwr_cfg rtl8723A_card_enable_flow
0287         [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
0288          RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
0289          RTL8723A_TRANS_END_STEPS];
0290 extern struct wlan_pwr_cfg rtl8723A_suspend_flow
0291         [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
0292          RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
0293          RTL8723A_TRANS_END_STEPS];
0294 extern struct wlan_pwr_cfg rtl8723A_resume_flow
0295         [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
0296          RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
0297          RTL8723A_TRANS_END_STEPS];
0298 extern struct wlan_pwr_cfg rtl8723A_hwpdn_flow
0299         [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
0300          RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
0301          RTL8723A_TRANS_END_STEPS];
0302 extern struct wlan_pwr_cfg rtl8723A_enter_lps_flow
0303         [RTL8723A_TRANS_ACT_TO_LPS_STEPS + RTL8723A_TRANS_END_STEPS];
0304 extern struct wlan_pwr_cfg rtl8723A_leave_lps_flow
0305         [RTL8723A_TRANS_LPS_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
0306 
0307 /* RTL8723 Power Configuration CMDs for PCIe interface */
0308 #define RTL8723_NIC_PWR_ON_FLOW     rtl8723A_power_on_flow
0309 #define RTL8723_NIC_RF_OFF_FLOW     rtl8723A_radio_off_flow
0310 #define RTL8723_NIC_DISABLE_FLOW    rtl8723A_card_disable_flow
0311 #define RTL8723_NIC_ENABLE_FLOW     rtl8723A_card_enable_flow
0312 #define RTL8723_NIC_SUSPEND_FLOW    rtl8723A_suspend_flow
0313 #define RTL8723_NIC_RESUME_FLOW     rtl8723A_resume_flow
0314 #define RTL8723_NIC_PDN_FLOW        rtl8723A_hwpdn_flow
0315 #define RTL8723_NIC_LPS_ENTER_FLOW  rtl8723A_enter_lps_flow
0316 #define RTL8723_NIC_LPS_LEAVE_FLOW  rtl8723A_leave_lps_flow
0317 
0318 #endif
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