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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003 
0004 #include "../wifi.h"
0005 #include "../pci.h"
0006 #include "../ps.h"
0007 #include "reg.h"
0008 #include "def.h"
0009 #include "phy.h"
0010 #include "rf.h"
0011 #include "dm.h"
0012 #include "table.h"
0013 #include "../rtl8723com/phy_common.h"
0014 
0015 static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
0016                          enum radio_path rfpath, u32 offset,
0017                          u32 data);
0018 static bool _rtl8723e_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
0019 static bool _rtl8723e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
0020 static bool _rtl8723e_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
0021                             u8 configtype);
0022 static bool _rtl8723e_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
0023                               u8 configtype);
0024 static bool _rtl8723e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
0025                            u8 channel, u8 *stage, u8 *step,
0026                            u32 *delay);
0027 static u8 _rtl8723e_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
0028                      enum wireless_mode wirelessmode,
0029                      long power_indbm);
0030 static void rtl8723e_phy_set_rf_on(struct ieee80211_hw *hw);
0031 static void rtl8723e_phy_set_io(struct ieee80211_hw *hw);
0032 
0033 u32 rtl8723e_phy_query_rf_reg(struct ieee80211_hw *hw,
0034                   enum radio_path rfpath,
0035                   u32 regaddr, u32 bitmask)
0036 {
0037     struct rtl_priv *rtlpriv = rtl_priv(hw);
0038     u32 original_value = 0, readback_value, bitshift;
0039     struct rtl_phy *rtlphy = &rtlpriv->phy;
0040 
0041     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0042         "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
0043         regaddr, rfpath, bitmask);
0044 
0045     spin_lock(&rtlpriv->locks.rf_lock);
0046 
0047     if (rtlphy->rf_mode != RF_OP_BY_FW) {
0048         original_value = rtl8723_phy_rf_serial_read(hw,
0049                                 rfpath, regaddr);
0050     }
0051 
0052     bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
0053     readback_value = (original_value & bitmask) >> bitshift;
0054 
0055     spin_unlock(&rtlpriv->locks.rf_lock);
0056 
0057     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0058         "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
0059         regaddr, rfpath, bitmask, original_value);
0060 
0061     return readback_value;
0062 }
0063 
0064 void rtl8723e_phy_set_rf_reg(struct ieee80211_hw *hw,
0065                  enum radio_path rfpath,
0066                u32 regaddr, u32 bitmask, u32 data)
0067 {
0068     struct rtl_priv *rtlpriv = rtl_priv(hw);
0069     struct rtl_phy *rtlphy = &rtlpriv->phy;
0070     u32 original_value = 0, bitshift;
0071 
0072     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0073         "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
0074         regaddr, bitmask, data, rfpath);
0075 
0076     spin_lock(&rtlpriv->locks.rf_lock);
0077 
0078     if (rtlphy->rf_mode != RF_OP_BY_FW) {
0079         if (bitmask != RFREG_OFFSET_MASK) {
0080             original_value = rtl8723_phy_rf_serial_read(hw,
0081                                     rfpath,
0082                                     regaddr);
0083             bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
0084             data =
0085                 ((original_value & (~bitmask)) |
0086                  (data << bitshift));
0087         }
0088 
0089         rtl8723_phy_rf_serial_write(hw, rfpath, regaddr, data);
0090     } else {
0091         if (bitmask != RFREG_OFFSET_MASK) {
0092             bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
0093             data =
0094                 ((original_value & (~bitmask)) |
0095                  (data << bitshift));
0096         }
0097         _rtl8723e_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
0098     }
0099 
0100     spin_unlock(&rtlpriv->locks.rf_lock);
0101 
0102     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0103         "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
0104         regaddr, bitmask, data, rfpath);
0105 
0106 }
0107 
0108 static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
0109                          enum radio_path rfpath, u32 offset,
0110                          u32 data)
0111 {
0112     WARN_ONCE(true, "rtl8723ae: _rtl8723e_phy_fw_rf_serial_write deprecated!\n");
0113 }
0114 
0115 static void _rtl8723e_phy_bb_config_1t(struct ieee80211_hw *hw)
0116 {
0117     rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
0118     rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
0119     rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
0120     rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
0121     rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
0122     rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
0123     rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
0124     rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
0125     rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
0126     rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
0127 }
0128 
0129 bool rtl8723e_phy_mac_config(struct ieee80211_hw *hw)
0130 {
0131     struct rtl_priv *rtlpriv = rtl_priv(hw);
0132     bool rtstatus = _rtl8723e_phy_config_mac_with_headerfile(hw);
0133     rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
0134     return rtstatus;
0135 }
0136 
0137 bool rtl8723e_phy_bb_config(struct ieee80211_hw *hw)
0138 {
0139     bool rtstatus = true;
0140     struct rtl_priv *rtlpriv = rtl_priv(hw);
0141     u8 tmpu1b;
0142     u8 b_reg_hwparafile = 1;
0143 
0144     rtl8723_phy_init_bb_rf_reg_def(hw);
0145 
0146     /* 1. 0x28[1] = 1 */
0147     tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_PLL_CTRL);
0148     udelay(2);
0149     rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, (tmpu1b|BIT(1)));
0150     udelay(2);
0151     /* 2. 0x29[7:0] = 0xFF */
0152     rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL+1, 0xff);
0153     udelay(2);
0154 
0155     /* 3. 0x02[1:0] = 2b'11 */
0156     tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
0157     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
0158                (tmpu1b | FEN_BB_GLB_RSTN | FEN_BBRSTB));
0159 
0160     /* 4. 0x25[6] = 0 */
0161     tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+1);
0162     rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+1, (tmpu1b & (~BIT(6))));
0163 
0164     /* 5. 0x24[20] = 0  //Advised by SD3 Alex Wang. 2011.02.09. */
0165     tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2);
0166     rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, (tmpu1b & (~BIT(4))));
0167 
0168     /* 6. 0x1f[7:0] = 0x07 */
0169     rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x07);
0170 
0171     if (b_reg_hwparafile == 1)
0172         rtstatus = _rtl8723e_phy_bb8192c_config_parafile(hw);
0173     return rtstatus;
0174 }
0175 
0176 bool rtl8723e_phy_rf_config(struct ieee80211_hw *hw)
0177 {
0178     return rtl8723e_phy_rf6052_config(hw);
0179 }
0180 
0181 static bool _rtl8723e_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
0182 {
0183     struct rtl_priv *rtlpriv = rtl_priv(hw);
0184     struct rtl_phy *rtlphy = &rtlpriv->phy;
0185     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0186     bool rtstatus;
0187 
0188     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
0189     rtstatus = _rtl8723e_phy_config_bb_with_headerfile(hw,
0190                         BASEBAND_CONFIG_PHY_REG);
0191     if (!rtstatus) {
0192         pr_err("Write BB Reg Fail!!\n");
0193         return false;
0194     }
0195 
0196     if (rtlphy->rf_type == RF_1T2R) {
0197         _rtl8723e_phy_bb_config_1t(hw);
0198         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
0199     }
0200     if (rtlefuse->autoload_failflag == false) {
0201         rtlphy->pwrgroup_cnt = 0;
0202         rtstatus = _rtl8723e_phy_config_bb_with_pgheaderfile(hw,
0203                     BASEBAND_CONFIG_PHY_REG);
0204     }
0205     if (!rtstatus) {
0206         pr_err("BB_PG Reg Fail!!\n");
0207         return false;
0208     }
0209     rtstatus =
0210       _rtl8723e_phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_AGC_TAB);
0211     if (!rtstatus) {
0212         pr_err("AGC Table Fail\n");
0213         return false;
0214     }
0215     rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
0216                     RFPGA0_XA_HSSIPARAMETER2,
0217                     0x200));
0218 
0219     return true;
0220 }
0221 
0222 static bool _rtl8723e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
0223 {
0224     struct rtl_priv *rtlpriv = rtl_priv(hw);
0225     u32 i;
0226     u32 arraylength;
0227     u32 *ptrarray;
0228 
0229     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl723MACPHY_Array\n");
0230     arraylength = RTL8723E_MACARRAYLENGTH;
0231     ptrarray = RTL8723EMAC_ARRAY;
0232 
0233     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0234         "Img:RTL8192CEMAC_2T_ARRAY\n");
0235     for (i = 0; i < arraylength; i = i + 2)
0236         rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
0237     return true;
0238 }
0239 
0240 static bool _rtl8723e_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
0241                             u8 configtype)
0242 {
0243     int i;
0244     u32 *phy_regarray_table;
0245     u32 *agctab_array_table;
0246     u16 phy_reg_arraylen, agctab_arraylen;
0247     struct rtl_priv *rtlpriv = rtl_priv(hw);
0248 
0249     agctab_arraylen = RTL8723E_AGCTAB_1TARRAYLENGTH;
0250     agctab_array_table = RTL8723EAGCTAB_1TARRAY;
0251     phy_reg_arraylen = RTL8723E_PHY_REG_1TARRAY_LENGTH;
0252     phy_regarray_table = RTL8723EPHY_REG_1TARRAY;
0253     if (configtype == BASEBAND_CONFIG_PHY_REG) {
0254         for (i = 0; i < phy_reg_arraylen; i = i + 2) {
0255             if (phy_regarray_table[i] == 0xfe)
0256                 mdelay(50);
0257             else if (phy_regarray_table[i] == 0xfd)
0258                 mdelay(5);
0259             else if (phy_regarray_table[i] == 0xfc)
0260                 mdelay(1);
0261             else if (phy_regarray_table[i] == 0xfb)
0262                 udelay(50);
0263             else if (phy_regarray_table[i] == 0xfa)
0264                 udelay(5);
0265             else if (phy_regarray_table[i] == 0xf9)
0266                 udelay(1);
0267             rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
0268                       phy_regarray_table[i + 1]);
0269             udelay(1);
0270             rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0271                 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
0272                 phy_regarray_table[i],
0273                 phy_regarray_table[i + 1]);
0274         }
0275     } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
0276         for (i = 0; i < agctab_arraylen; i = i + 2) {
0277             rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
0278                       agctab_array_table[i + 1]);
0279             udelay(1);
0280             rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0281                 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
0282                 agctab_array_table[i],
0283                 agctab_array_table[i + 1]);
0284         }
0285     }
0286     return true;
0287 }
0288 
0289 static void store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
0290                        u32 regaddr, u32 bitmask,
0291                        u32 data)
0292 {
0293     struct rtl_priv *rtlpriv = rtl_priv(hw);
0294     struct rtl_phy *rtlphy = &rtlpriv->phy;
0295 
0296     if (regaddr == RTXAGC_A_RATE18_06) {
0297         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
0298             data;
0299         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0300             "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
0301             rtlphy->pwrgroup_cnt,
0302             rtlphy->mcs_txpwrlevel_origoffset
0303             [rtlphy->pwrgroup_cnt][0]);
0304     }
0305     if (regaddr == RTXAGC_A_RATE54_24) {
0306         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
0307             data;
0308         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0309             "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
0310             rtlphy->pwrgroup_cnt,
0311             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0312                                 pwrgroup_cnt][1]);
0313     }
0314     if (regaddr == RTXAGC_A_CCK1_MCS32) {
0315         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
0316             data;
0317         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0318             "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
0319             rtlphy->pwrgroup_cnt,
0320             rtlphy->mcs_txpwrlevel_origoffset
0321             [rtlphy->pwrgroup_cnt][6]);
0322     }
0323     if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
0324         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
0325             data;
0326         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0327             "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
0328             rtlphy->pwrgroup_cnt,
0329             rtlphy->mcs_txpwrlevel_origoffset
0330             [rtlphy->pwrgroup_cnt][7]);
0331     }
0332     if (regaddr == RTXAGC_A_MCS03_MCS00) {
0333         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
0334             data;
0335         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0336             "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
0337             rtlphy->pwrgroup_cnt,
0338             rtlphy->mcs_txpwrlevel_origoffset
0339             [rtlphy->pwrgroup_cnt][2]);
0340     }
0341     if (regaddr == RTXAGC_A_MCS07_MCS04) {
0342         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
0343             data;
0344         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0345             "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
0346             rtlphy->pwrgroup_cnt,
0347             rtlphy->mcs_txpwrlevel_origoffset
0348             [rtlphy->pwrgroup_cnt][3]);
0349     }
0350     if (regaddr == RTXAGC_A_MCS11_MCS08) {
0351         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
0352             data;
0353         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0354             "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
0355             rtlphy->pwrgroup_cnt,
0356             rtlphy->mcs_txpwrlevel_origoffset
0357             [rtlphy->pwrgroup_cnt][4]);
0358     }
0359     if (regaddr == RTXAGC_A_MCS15_MCS12) {
0360         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
0361             data;
0362         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0363             "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
0364             rtlphy->pwrgroup_cnt,
0365             rtlphy->mcs_txpwrlevel_origoffset
0366             [rtlphy->pwrgroup_cnt][5]);
0367     }
0368     if (regaddr == RTXAGC_B_RATE18_06) {
0369         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
0370             data;
0371         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0372             "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
0373             rtlphy->pwrgroup_cnt,
0374             rtlphy->mcs_txpwrlevel_origoffset
0375             [rtlphy->pwrgroup_cnt][8]);
0376     }
0377     if (regaddr == RTXAGC_B_RATE54_24) {
0378         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
0379             data;
0380         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0381             "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
0382             rtlphy->pwrgroup_cnt,
0383             rtlphy->mcs_txpwrlevel_origoffset
0384             [rtlphy->pwrgroup_cnt][9]);
0385     }
0386     if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
0387         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
0388             data;
0389         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0390             "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
0391             rtlphy->pwrgroup_cnt,
0392             rtlphy->mcs_txpwrlevel_origoffset
0393             [rtlphy->pwrgroup_cnt][14]);
0394     }
0395     if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
0396         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
0397             data;
0398         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0399             "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
0400             rtlphy->pwrgroup_cnt,
0401             rtlphy->mcs_txpwrlevel_origoffset
0402             [rtlphy->pwrgroup_cnt][15]);
0403     }
0404     if (regaddr == RTXAGC_B_MCS03_MCS00) {
0405         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
0406             data;
0407         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0408             "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
0409             rtlphy->pwrgroup_cnt,
0410             rtlphy->mcs_txpwrlevel_origoffset
0411             [rtlphy->pwrgroup_cnt][10]);
0412     }
0413     if (regaddr == RTXAGC_B_MCS07_MCS04) {
0414         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
0415             data;
0416         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0417             "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
0418             rtlphy->pwrgroup_cnt,
0419             rtlphy->mcs_txpwrlevel_origoffset
0420             [rtlphy->pwrgroup_cnt][11]);
0421     }
0422     if (regaddr == RTXAGC_B_MCS11_MCS08) {
0423         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
0424             data;
0425         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0426             "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
0427             rtlphy->pwrgroup_cnt,
0428             rtlphy->mcs_txpwrlevel_origoffset
0429             [rtlphy->pwrgroup_cnt][12]);
0430     }
0431     if (regaddr == RTXAGC_B_MCS15_MCS12) {
0432         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
0433             data;
0434         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0435             "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
0436             rtlphy->pwrgroup_cnt,
0437             rtlphy->mcs_txpwrlevel_origoffset
0438             [rtlphy->pwrgroup_cnt][13]);
0439 
0440         rtlphy->pwrgroup_cnt++;
0441     }
0442 }
0443 
0444 static bool _rtl8723e_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
0445                               u8 configtype)
0446 {
0447     struct rtl_priv *rtlpriv = rtl_priv(hw);
0448     int i;
0449     u32 *phy_regarray_table_pg;
0450     u16 phy_regarray_pg_len;
0451 
0452     phy_regarray_pg_len = RTL8723E_PHY_REG_ARRAY_PGLENGTH;
0453     phy_regarray_table_pg = RTL8723EPHY_REG_ARRAY_PG;
0454 
0455     if (configtype == BASEBAND_CONFIG_PHY_REG) {
0456         for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
0457             if (phy_regarray_table_pg[i] == 0xfe)
0458                 mdelay(50);
0459             else if (phy_regarray_table_pg[i] == 0xfd)
0460                 mdelay(5);
0461             else if (phy_regarray_table_pg[i] == 0xfc)
0462                 mdelay(1);
0463             else if (phy_regarray_table_pg[i] == 0xfb)
0464                 udelay(50);
0465             else if (phy_regarray_table_pg[i] == 0xfa)
0466                 udelay(5);
0467             else if (phy_regarray_table_pg[i] == 0xf9)
0468                 udelay(1);
0469 
0470             store_pwrindex_diffrate_offset(hw,
0471                         phy_regarray_table_pg[i],
0472                         phy_regarray_table_pg[i + 1],
0473                         phy_regarray_table_pg[i + 2]);
0474         }
0475     } else {
0476         rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,
0477             "configtype != BaseBand_Config_PHY_REG\n");
0478     }
0479     return true;
0480 }
0481 
0482 bool rtl8723e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
0483                         enum radio_path rfpath)
0484 {
0485     int i;
0486     u32 *radioa_array_table;
0487     u16 radioa_arraylen;
0488 
0489     radioa_arraylen = RTL8723ERADIOA_1TARRAYLENGTH;
0490     radioa_array_table = RTL8723E_RADIOA_1TARRAY;
0491 
0492     switch (rfpath) {
0493     case RF90_PATH_A:
0494         for (i = 0; i < radioa_arraylen; i = i + 2) {
0495             if (radioa_array_table[i] == 0xfe) {
0496                 mdelay(50);
0497             } else if (radioa_array_table[i] == 0xfd) {
0498                 mdelay(5);
0499             } else if (radioa_array_table[i] == 0xfc) {
0500                 mdelay(1);
0501             } else if (radioa_array_table[i] == 0xfb) {
0502                 udelay(50);
0503             } else if (radioa_array_table[i] == 0xfa) {
0504                 udelay(5);
0505             } else if (radioa_array_table[i] == 0xf9) {
0506                 udelay(1);
0507             } else {
0508                 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
0509                           RFREG_OFFSET_MASK,
0510                           radioa_array_table[i + 1]);
0511                 udelay(1);
0512             }
0513         }
0514         break;
0515     case RF90_PATH_B:
0516     case RF90_PATH_C:
0517     case RF90_PATH_D:
0518         break;
0519     }
0520     return true;
0521 }
0522 
0523 void rtl8723e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
0524 {
0525     struct rtl_priv *rtlpriv = rtl_priv(hw);
0526     struct rtl_phy *rtlphy = &rtlpriv->phy;
0527 
0528     rtlphy->default_initialgain[0] =
0529         (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
0530     rtlphy->default_initialgain[1] =
0531         (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
0532     rtlphy->default_initialgain[2] =
0533         (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
0534     rtlphy->default_initialgain[3] =
0535         (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
0536 
0537     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0538         "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
0539         rtlphy->default_initialgain[0],
0540         rtlphy->default_initialgain[1],
0541         rtlphy->default_initialgain[2],
0542         rtlphy->default_initialgain[3]);
0543 
0544     rtlphy->framesync = (u8) rtl_get_bbreg(hw,
0545                            ROFDM0_RXDETECTOR3, MASKBYTE0);
0546     rtlphy->framesync_c34 = rtl_get_bbreg(hw,
0547                           ROFDM0_RXDETECTOR2, MASKDWORD);
0548 
0549     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0550         "Default framesync (0x%x) = 0x%x\n",
0551         ROFDM0_RXDETECTOR3, rtlphy->framesync);
0552 }
0553 
0554 void rtl8723e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
0555 {
0556     struct rtl_priv *rtlpriv = rtl_priv(hw);
0557     struct rtl_phy *rtlphy = &rtlpriv->phy;
0558     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0559     u8 txpwr_level;
0560     long txpwr_dbm;
0561 
0562     txpwr_level = rtlphy->cur_cck_txpwridx;
0563     txpwr_dbm = rtl8723_phy_txpwr_idx_to_dbm(hw,
0564                          WIRELESS_MODE_B, txpwr_level);
0565     txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
0566         rtlefuse->legacy_ht_txpowerdiff;
0567     if (rtl8723_phy_txpwr_idx_to_dbm(hw,
0568                      WIRELESS_MODE_G,
0569                      txpwr_level) > txpwr_dbm)
0570         txpwr_dbm =
0571             rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
0572                          txpwr_level);
0573     txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
0574     if (rtl8723_phy_txpwr_idx_to_dbm(hw,
0575                      WIRELESS_MODE_N_24G,
0576                      txpwr_level) > txpwr_dbm)
0577         txpwr_dbm =
0578             rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
0579                          txpwr_level);
0580     *powerlevel = txpwr_dbm;
0581 }
0582 
0583 static void _rtl8723e_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
0584                     u8 *cckpowerlevel, u8 *ofdmpowerlevel)
0585 {
0586     struct rtl_priv *rtlpriv = rtl_priv(hw);
0587     struct rtl_phy *rtlphy = &rtlpriv->phy;
0588     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0589     u8 index = (channel - 1);
0590 
0591     cckpowerlevel[RF90_PATH_A] =
0592         rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
0593     cckpowerlevel[RF90_PATH_B] =
0594         rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
0595     if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
0596         ofdmpowerlevel[RF90_PATH_A] =
0597             rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
0598         ofdmpowerlevel[RF90_PATH_B] =
0599             rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
0600     } else if (get_rf_type(rtlphy) == RF_2T2R) {
0601         ofdmpowerlevel[RF90_PATH_A] =
0602             rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
0603         ofdmpowerlevel[RF90_PATH_B] =
0604             rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
0605     }
0606 }
0607 
0608 static void _rtl8723e_ccxpower_index_check(struct ieee80211_hw *hw,
0609                        u8 channel, u8 *cckpowerlevel,
0610                        u8 *ofdmpowerlevel)
0611 {
0612     struct rtl_priv *rtlpriv = rtl_priv(hw);
0613     struct rtl_phy *rtlphy = &rtlpriv->phy;
0614 
0615     rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
0616     rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
0617 
0618 }
0619 
0620 void rtl8723e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
0621 {
0622     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0623     u8 cckpowerlevel[2], ofdmpowerlevel[2];
0624 
0625     if (!rtlefuse->txpwr_fromeprom)
0626         return;
0627     _rtl8723e_get_txpower_index(hw, channel,
0628                     &cckpowerlevel[0], &ofdmpowerlevel[0]);
0629     _rtl8723e_ccxpower_index_check(hw,
0630                        channel, &cckpowerlevel[0],
0631                        &ofdmpowerlevel[0]);
0632     rtl8723e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
0633     rtl8723e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
0634 }
0635 
0636 bool rtl8723e_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
0637 {
0638     struct rtl_priv *rtlpriv = rtl_priv(hw);
0639     struct rtl_phy *rtlphy = &rtlpriv->phy;
0640     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0641     u8 idx;
0642     u8 rf_path;
0643     u8 ccktxpwridx = _rtl8723e_phy_dbm_to_txpwr_idx(hw,
0644                               WIRELESS_MODE_B,
0645                               power_indbm);
0646     u8 ofdmtxpwridx = _rtl8723e_phy_dbm_to_txpwr_idx(hw,
0647                                WIRELESS_MODE_N_24G,
0648                                power_indbm);
0649     if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
0650         ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
0651     else
0652         ofdmtxpwridx = 0;
0653     rtl_dbg(rtlpriv, COMP_TXAGC, DBG_TRACE,
0654         "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
0655         power_indbm, ccktxpwridx, ofdmtxpwridx);
0656     for (idx = 0; idx < 14; idx++) {
0657         for (rf_path = 0; rf_path < 2; rf_path++) {
0658             rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
0659             rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
0660                 ofdmtxpwridx;
0661             rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
0662                 ofdmtxpwridx;
0663         }
0664     }
0665     rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel);
0666     return true;
0667 }
0668 
0669 static u8 _rtl8723e_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
0670                      enum wireless_mode wirelessmode,
0671                      long power_indbm)
0672 {
0673     u8 txpwridx;
0674     long offset;
0675 
0676     switch (wirelessmode) {
0677     case WIRELESS_MODE_B:
0678         offset = -7;
0679         break;
0680     case WIRELESS_MODE_G:
0681     case WIRELESS_MODE_N_24G:
0682         offset = -8;
0683         break;
0684     default:
0685         offset = -8;
0686         break;
0687     }
0688 
0689     if ((power_indbm - offset) > 0)
0690         txpwridx = (u8)((power_indbm - offset) * 2);
0691     else
0692         txpwridx = 0;
0693 
0694     if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
0695         txpwridx = MAX_TXPWR_IDX_NMODE_92S;
0696 
0697     return txpwridx;
0698 }
0699 
0700 void rtl8723e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
0701 {
0702     struct rtl_priv *rtlpriv = rtl_priv(hw);
0703     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0704     enum io_type iotype;
0705 
0706     if (!is_hal_stop(rtlhal)) {
0707         switch (operation) {
0708         case SCAN_OPT_BACKUP_BAND0:
0709             iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
0710             rtlpriv->cfg->ops->set_hw_reg(hw,
0711                               HW_VAR_IO_CMD,
0712                               (u8 *)&iotype);
0713 
0714             break;
0715         case SCAN_OPT_RESTORE:
0716             iotype = IO_CMD_RESUME_DM_BY_SCAN;
0717             rtlpriv->cfg->ops->set_hw_reg(hw,
0718                               HW_VAR_IO_CMD,
0719                               (u8 *)&iotype);
0720             break;
0721         default:
0722             pr_err("Unknown Scan Backup operation.\n");
0723             break;
0724         }
0725     }
0726 }
0727 
0728 void rtl8723e_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
0729 {
0730     struct rtl_priv *rtlpriv = rtl_priv(hw);
0731     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0732     struct rtl_phy *rtlphy = &rtlpriv->phy;
0733     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
0734     u8 reg_bw_opmode;
0735     u8 reg_prsr_rsc;
0736 
0737     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
0738         "Switch to %s bandwidth\n",
0739         rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
0740         "20MHz" : "40MHz");
0741 
0742     if (is_hal_stop(rtlhal)) {
0743         rtlphy->set_bwmode_inprogress = false;
0744         return;
0745     }
0746 
0747     reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
0748     reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
0749 
0750     switch (rtlphy->current_chan_bw) {
0751     case HT_CHANNEL_WIDTH_20:
0752         reg_bw_opmode |= BW_OPMODE_20MHZ;
0753         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
0754         break;
0755     case HT_CHANNEL_WIDTH_20_40:
0756         reg_bw_opmode &= ~BW_OPMODE_20MHZ;
0757         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
0758         reg_prsr_rsc =
0759             (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
0760         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
0761         break;
0762     default:
0763         pr_err("unknown bandwidth: %#X\n",
0764                rtlphy->current_chan_bw);
0765         break;
0766     }
0767 
0768     switch (rtlphy->current_chan_bw) {
0769     case HT_CHANNEL_WIDTH_20:
0770         rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
0771         rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
0772         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
0773         break;
0774     case HT_CHANNEL_WIDTH_20_40:
0775         rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
0776         rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
0777 
0778         rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
0779                   (mac->cur_40_prime_sc >> 1));
0780         rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
0781         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
0782 
0783         rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
0784                   (mac->cur_40_prime_sc ==
0785                    HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
0786         break;
0787     default:
0788         pr_err("unknown bandwidth: %#X\n",
0789                rtlphy->current_chan_bw);
0790         break;
0791     }
0792     rtl8723e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
0793     rtlphy->set_bwmode_inprogress = false;
0794     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
0795 }
0796 
0797 void rtl8723e_phy_set_bw_mode(struct ieee80211_hw *hw,
0798                   enum nl80211_channel_type ch_type)
0799 {
0800     struct rtl_priv *rtlpriv = rtl_priv(hw);
0801     struct rtl_phy *rtlphy = &rtlpriv->phy;
0802     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0803     u8 tmp_bw = rtlphy->current_chan_bw;
0804 
0805     if (rtlphy->set_bwmode_inprogress)
0806         return;
0807     rtlphy->set_bwmode_inprogress = true;
0808     if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
0809         rtl8723e_phy_set_bw_mode_callback(hw);
0810     } else {
0811         rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
0812             "false driver sleep or unload\n");
0813         rtlphy->set_bwmode_inprogress = false;
0814         rtlphy->current_chan_bw = tmp_bw;
0815     }
0816 }
0817 
0818 void rtl8723e_phy_sw_chnl_callback(struct ieee80211_hw *hw)
0819 {
0820     struct rtl_priv *rtlpriv = rtl_priv(hw);
0821     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0822     struct rtl_phy *rtlphy = &rtlpriv->phy;
0823     u32 delay;
0824 
0825     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
0826         "switch to channel%d\n", rtlphy->current_channel);
0827     if (is_hal_stop(rtlhal))
0828         return;
0829     do {
0830         if (!rtlphy->sw_chnl_inprogress)
0831             break;
0832         if (!_rtl8723e_phy_sw_chnl_step_by_step
0833             (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
0834              &rtlphy->sw_chnl_step, &delay)) {
0835             if (delay > 0)
0836                 mdelay(delay);
0837             else
0838                 continue;
0839         } else {
0840             rtlphy->sw_chnl_inprogress = false;
0841         }
0842         break;
0843     } while (true);
0844     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
0845 }
0846 
0847 u8 rtl8723e_phy_sw_chnl(struct ieee80211_hw *hw)
0848 {
0849     struct rtl_priv *rtlpriv = rtl_priv(hw);
0850     struct rtl_phy *rtlphy = &rtlpriv->phy;
0851     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0852 
0853     if (rtlphy->sw_chnl_inprogress)
0854         return 0;
0855     if (rtlphy->set_bwmode_inprogress)
0856         return 0;
0857     WARN_ONCE((rtlphy->current_channel > 14),
0858           "rtl8723ae: WIRELESS_MODE_G but channel>14");
0859     rtlphy->sw_chnl_inprogress = true;
0860     rtlphy->sw_chnl_stage = 0;
0861     rtlphy->sw_chnl_step = 0;
0862     if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
0863         rtl8723e_phy_sw_chnl_callback(hw);
0864         rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
0865             "sw_chnl_inprogress false schedule workitem\n");
0866         rtlphy->sw_chnl_inprogress = false;
0867     } else {
0868         rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
0869             "sw_chnl_inprogress false driver sleep or unload\n");
0870         rtlphy->sw_chnl_inprogress = false;
0871     }
0872     return 1;
0873 }
0874 
0875 static void _rtl8723e_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel)
0876 {
0877     struct rtl_priv *rtlpriv = rtl_priv(hw);
0878     struct rtl_phy *rtlphy = &rtlpriv->phy;
0879     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0880 
0881     if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
0882         if (channel == 6 && rtlphy->current_chan_bw ==
0883                 HT_CHANNEL_WIDTH_20)
0884             rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
0885                       MASKDWORD, 0x00255);
0886         else{
0887             u32 backuprf0x1a = (u32)rtl_get_rfreg(hw,
0888                     RF90_PATH_A, RF_RX_G1,
0889                     RFREG_OFFSET_MASK);
0890             rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
0891                       MASKDWORD, backuprf0x1a);
0892         }
0893     }
0894 }
0895 
0896 static bool _rtl8723e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
0897                            u8 channel, u8 *stage, u8 *step,
0898                            u32 *delay)
0899 {
0900     struct rtl_priv *rtlpriv = rtl_priv(hw);
0901     struct rtl_phy *rtlphy = &rtlpriv->phy;
0902     struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
0903     u32 precommoncmdcnt;
0904     struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
0905     u32 postcommoncmdcnt;
0906     struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
0907     u32 rfdependcmdcnt;
0908     struct swchnlcmd *currentcmd = NULL;
0909     u8 rfpath;
0910     u8 num_total_rfpath = rtlphy->num_total_rfpath;
0911 
0912     precommoncmdcnt = 0;
0913     rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
0914                      MAX_PRECMD_CNT,
0915                      CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
0916     rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
0917                      MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
0918 
0919     postcommoncmdcnt = 0;
0920 
0921     rtl8723_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
0922                      MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
0923 
0924     rfdependcmdcnt = 0;
0925 
0926     WARN_ONCE((channel < 1 || channel > 14),
0927           "rtl8723ae: illegal channel for Zebra: %d\n", channel);
0928 
0929     rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
0930                      MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
0931                      RF_CHNLBW, channel, 10);
0932 
0933     rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
0934                      MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
0935                      0);
0936 
0937     do {
0938         switch (*stage) {
0939         case 0:
0940             currentcmd = &precommoncmd[*step];
0941             break;
0942         case 1:
0943             currentcmd = &rfdependcmd[*step];
0944             break;
0945         case 2:
0946             currentcmd = &postcommoncmd[*step];
0947             break;
0948         default:
0949             pr_err("Invalid 'stage' = %d, Check it!\n",
0950                    *stage);
0951             return true;
0952         }
0953 
0954         if (currentcmd->cmdid == CMDID_END) {
0955             if ((*stage) == 2) {
0956                 return true;
0957             } else {
0958                 (*stage)++;
0959                 (*step) = 0;
0960                 continue;
0961             }
0962         }
0963 
0964         switch (currentcmd->cmdid) {
0965         case CMDID_SET_TXPOWEROWER_LEVEL:
0966             rtl8723e_phy_set_txpower_level(hw, channel);
0967             break;
0968         case CMDID_WRITEPORT_ULONG:
0969             rtl_write_dword(rtlpriv, currentcmd->para1,
0970                     currentcmd->para2);
0971             break;
0972         case CMDID_WRITEPORT_USHORT:
0973             rtl_write_word(rtlpriv, currentcmd->para1,
0974                        (u16) currentcmd->para2);
0975             break;
0976         case CMDID_WRITEPORT_UCHAR:
0977             rtl_write_byte(rtlpriv, currentcmd->para1,
0978                        (u8) currentcmd->para2);
0979             break;
0980         case CMDID_RF_WRITEREG:
0981             for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
0982                 rtlphy->rfreg_chnlval[rfpath] =
0983                     ((rtlphy->rfreg_chnlval[rfpath] &
0984                       0xfffffc00) | currentcmd->para2);
0985 
0986                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
0987                           currentcmd->para1,
0988                           RFREG_OFFSET_MASK,
0989                           rtlphy->rfreg_chnlval[rfpath]);
0990             }
0991             _rtl8723e_phy_sw_rf_seting(hw, channel);
0992             break;
0993         default:
0994             rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
0995                 "switch case %#x not processed\n",
0996                 currentcmd->cmdid);
0997             break;
0998         }
0999 
1000         break;
1001     } while (true);
1002 
1003     (*delay) = currentcmd->msdelay;
1004     (*step)++;
1005     return false;
1006 }
1007 
1008 static u8 _rtl8723e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1009 {
1010     u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
1011     u8 result = 0x00;
1012 
1013     rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1014     rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1015     rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1016     rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
1017               config_pathb ? 0x28160202 : 0x28160502);
1018 
1019     if (config_pathb) {
1020         rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1021         rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1022         rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1023         rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
1024     }
1025 
1026     rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
1027     rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1028     rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1029 
1030     mdelay(IQK_DELAY_TIME);
1031 
1032     reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1033     reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1034     reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1035     reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1036 
1037     if (!(reg_eac & BIT(28)) &&
1038         (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1039         (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1040         result |= 0x01;
1041     else
1042         return result;
1043 
1044     if (!(reg_eac & BIT(27)) &&
1045         (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1046         (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1047         result |= 0x02;
1048     return result;
1049 }
1050 
1051 static u8 _rtl8723e_phy_path_b_iqk(struct ieee80211_hw *hw)
1052 {
1053     u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1054     u8 result = 0x00;
1055 
1056     rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1057     rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1058     mdelay(IQK_DELAY_TIME);
1059     reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1060     reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1061     reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1062     reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1063     reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1064 
1065     if (!(reg_eac & BIT(31)) &&
1066         (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1067         (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1068         result |= 0x01;
1069     else
1070         return result;
1071     if (!(reg_eac & BIT(30)) &&
1072         (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1073         (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1074         result |= 0x02;
1075     return result;
1076 }
1077 
1078 static bool _rtl8723e_phy_simularity_compare(struct ieee80211_hw *hw,
1079                          long result[][8], u8 c1, u8 c2)
1080 {
1081     u32 i, j, diff, simularity_bitmap, bound;
1082 
1083     u8 final_candidate[2] = { 0xFF, 0xFF };
1084     bool bresult = true;
1085 
1086     bound = 4;
1087 
1088     simularity_bitmap = 0;
1089 
1090     for (i = 0; i < bound; i++) {
1091         diff = (result[c1][i] > result[c2][i]) ?
1092             (result[c1][i] - result[c2][i]) :
1093             (result[c2][i] - result[c1][i]);
1094 
1095         if (diff > MAX_TOLERANCE) {
1096             if ((i == 2 || i == 6) && !simularity_bitmap) {
1097                 if (result[c1][i] + result[c1][i + 1] == 0)
1098                     final_candidate[(i / 4)] = c2;
1099                 else if (result[c2][i] + result[c2][i + 1] == 0)
1100                     final_candidate[(i / 4)] = c1;
1101                 else
1102                     simularity_bitmap = simularity_bitmap |
1103                         (1 << i);
1104             } else
1105                 simularity_bitmap =
1106                     simularity_bitmap | (1 << i);
1107         }
1108     }
1109 
1110     if (simularity_bitmap == 0) {
1111         for (i = 0; i < (bound / 4); i++) {
1112             if (final_candidate[i] != 0xFF) {
1113                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1114                     result[3][j] =
1115                         result[final_candidate[i]][j];
1116                 bresult = false;
1117             }
1118         }
1119         return bresult;
1120     } else if (!(simularity_bitmap & 0x0F)) {
1121         for (i = 0; i < 4; i++)
1122             result[3][i] = result[c1][i];
1123         return false;
1124     } else {
1125         return false;
1126     }
1127 
1128 }
1129 
1130 static void _rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw,
1131                        long result[][8], u8 t, bool is2t)
1132 {
1133     struct rtl_priv *rtlpriv = rtl_priv(hw);
1134     struct rtl_phy *rtlphy = &rtlpriv->phy;
1135     u32 i;
1136     u8 patha_ok, pathb_ok;
1137     u32 adda_reg[IQK_ADDA_REG_NUM] = {
1138         0x85c, 0xe6c, 0xe70, 0xe74,
1139         0xe78, 0xe7c, 0xe80, 0xe84,
1140         0xe88, 0xe8c, 0xed0, 0xed4,
1141         0xed8, 0xedc, 0xee0, 0xeec
1142     };
1143 
1144     u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1145         0x522, 0x550, 0x551, 0x040
1146     };
1147 
1148     const u32 retrycount = 2;
1149 
1150     if (t == 0) {
1151         rtl_get_bbreg(hw, 0x800, MASKDWORD);
1152 
1153         rtl8723_save_adda_registers(hw, adda_reg,
1154                         rtlphy->adda_backup, 16);
1155         rtl8723_phy_save_mac_registers(hw, iqk_mac_reg,
1156                            rtlphy->iqk_mac_backup);
1157     }
1158     rtl8723_phy_path_adda_on(hw, adda_reg, true, is2t);
1159     if (t == 0) {
1160         rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1161                     RFPGA0_XA_HSSIPARAMETER1,
1162                     BIT(8));
1163     }
1164 
1165     if (!rtlphy->rfpi_enable)
1166         rtl8723_phy_pi_mode_switch(hw, true);
1167     if (t == 0) {
1168         rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1169         rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1170         rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1171     }
1172     rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1173     rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1174     rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1175     if (is2t) {
1176         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1177         rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1178     }
1179     rtl8723_phy_mac_setting_calibration(hw, iqk_mac_reg,
1180                         rtlphy->iqk_mac_backup);
1181     rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1182     if (is2t)
1183         rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1184     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1185     rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1186     rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1187     for (i = 0; i < retrycount; i++) {
1188         patha_ok = _rtl8723e_phy_path_a_iqk(hw, is2t);
1189         if (patha_ok == 0x03) {
1190             result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1191                     0x3FF0000) >> 16;
1192             result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1193                     0x3FF0000) >> 16;
1194             result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1195                     0x3FF0000) >> 16;
1196             result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1197                     0x3FF0000) >> 16;
1198             break;
1199         } else if (i == (retrycount - 1) && patha_ok == 0x01)
1200 
1201             result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1202                               MASKDWORD) & 0x3FF0000) >>
1203                 16;
1204         result[t][1] =
1205             (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1206 
1207     }
1208 
1209     if (is2t) {
1210         rtl8723_phy_path_a_standby(hw);
1211         rtl8723_phy_path_adda_on(hw, adda_reg, false, is2t);
1212         for (i = 0; i < retrycount; i++) {
1213             pathb_ok = _rtl8723e_phy_path_b_iqk(hw);
1214             if (pathb_ok == 0x03) {
1215                 result[t][4] = (rtl_get_bbreg(hw,
1216                                   0xeb4,
1217                                   MASKDWORD) &
1218                         0x3FF0000) >> 16;
1219                 result[t][5] =
1220                     (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1221                      0x3FF0000) >> 16;
1222                 result[t][6] =
1223                     (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1224                      0x3FF0000) >> 16;
1225                 result[t][7] =
1226                     (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1227                      0x3FF0000) >> 16;
1228                 break;
1229             } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1230                 result[t][4] = (rtl_get_bbreg(hw,
1231                                   0xeb4,
1232                                   MASKDWORD) &
1233                         0x3FF0000) >> 16;
1234             }
1235             result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1236                     0x3FF0000) >> 16;
1237         }
1238     }
1239     rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1240     rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1241     rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1242     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1243     rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1244     if (is2t)
1245         rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1246     if (t != 0) {
1247         if (!rtlphy->rfpi_enable)
1248             rtl8723_phy_pi_mode_switch(hw, false);
1249         rtl8723_phy_reload_adda_registers(hw, adda_reg,
1250                           rtlphy->adda_backup, 16);
1251         rtl8723_phy_reload_mac_registers(hw, iqk_mac_reg,
1252                          rtlphy->iqk_mac_backup);
1253     }
1254 }
1255 
1256 static void _rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1257 {
1258     u8 tmpreg;
1259     u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1260     struct rtl_priv *rtlpriv = rtl_priv(hw);
1261 
1262     tmpreg = rtl_read_byte(rtlpriv, 0xd03);
1263 
1264     if ((tmpreg & 0x70) != 0)
1265         rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
1266     else
1267         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1268 
1269     if ((tmpreg & 0x70) != 0) {
1270         rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
1271 
1272         if (is2t)
1273             rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
1274                           MASK12BITS);
1275 
1276         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
1277                   (rf_a_mode & 0x8FFFF) | 0x10000);
1278 
1279         if (is2t)
1280             rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1281                       (rf_b_mode & 0x8FFFF) | 0x10000);
1282     }
1283     lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
1284 
1285     rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
1286 
1287     mdelay(100);
1288 
1289     if ((tmpreg & 0x70) != 0) {
1290         rtl_write_byte(rtlpriv, 0xd03, tmpreg);
1291         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
1292 
1293         if (is2t)
1294             rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1295                       rf_b_mode);
1296     } else {
1297         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1298     }
1299 }
1300 
1301 static void _rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1302                         bool bmain, bool is2t)
1303 {
1304     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1305 
1306     if (is_hal_stop(rtlhal)) {
1307         rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1308         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1309     }
1310     if (is2t) {
1311         if (bmain)
1312             rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1313                       BIT(5) | BIT(6), 0x1);
1314         else
1315             rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1316                       BIT(5) | BIT(6), 0x2);
1317     } else {
1318         if (bmain)
1319             rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1320         else
1321             rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1322 
1323     }
1324 
1325 }
1326 
1327 #undef IQK_ADDA_REG_NUM
1328 #undef IQK_DELAY_TIME
1329 
1330 void rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1331 {
1332     struct rtl_priv *rtlpriv = rtl_priv(hw);
1333     struct rtl_phy *rtlphy = &rtlpriv->phy;
1334 
1335     long result[4][8];
1336     u8 i, final_candidate;
1337     bool b_patha_ok;
1338     long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc,
1339        reg_tmp = 0;
1340     bool is12simular, is13simular, is23simular;
1341     u32 iqk_bb_reg[10] = {
1342         ROFDM0_XARXIQIMBALANCE,
1343         ROFDM0_XBRXIQIMBALANCE,
1344         ROFDM0_ECCATHRESHOLD,
1345         ROFDM0_AGCRSSITABLE,
1346         ROFDM0_XATXIQIMBALANCE,
1347         ROFDM0_XBTXIQIMBALANCE,
1348         ROFDM0_XCTXIQIMBALANCE,
1349         ROFDM0_XCTXAFE,
1350         ROFDM0_XDTXAFE,
1351         ROFDM0_RXIQEXTANTA
1352     };
1353 
1354     if (b_recovery) {
1355         rtl8723_phy_reload_adda_registers(hw,
1356                           iqk_bb_reg,
1357                           rtlphy->iqk_bb_backup, 10);
1358         return;
1359     }
1360     for (i = 0; i < 8; i++) {
1361         result[0][i] = 0;
1362         result[1][i] = 0;
1363         result[2][i] = 0;
1364         result[3][i] = 0;
1365     }
1366     final_candidate = 0xff;
1367     b_patha_ok = false;
1368     is12simular = false;
1369     is23simular = false;
1370     is13simular = false;
1371     for (i = 0; i < 3; i++) {
1372         _rtl8723e_phy_iq_calibrate(hw, result, i, false);
1373         if (i == 1) {
1374             is12simular =
1375               _rtl8723e_phy_simularity_compare(hw, result, 0, 1);
1376             if (is12simular) {
1377                 final_candidate = 0;
1378                 break;
1379             }
1380         }
1381         if (i == 2) {
1382             is13simular =
1383               _rtl8723e_phy_simularity_compare(hw, result, 0, 2);
1384             if (is13simular) {
1385                 final_candidate = 0;
1386                 break;
1387             }
1388             is23simular =
1389               _rtl8723e_phy_simularity_compare(hw, result, 1, 2);
1390             if (is23simular)
1391                 final_candidate = 1;
1392             else {
1393                 for (i = 0; i < 8; i++)
1394                     reg_tmp += result[3][i];
1395 
1396                 if (reg_tmp != 0)
1397                     final_candidate = 3;
1398                 else
1399                     final_candidate = 0xFF;
1400             }
1401         }
1402     }
1403     for (i = 0; i < 4; i++) {
1404         reg_e94 = result[i][0];
1405         reg_e9c = result[i][1];
1406         reg_ea4 = result[i][2];
1407         reg_eb4 = result[i][4];
1408         reg_ebc = result[i][5];
1409     }
1410     if (final_candidate != 0xff) {
1411         rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1412         rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1413         reg_ea4 = result[final_candidate][2];
1414         rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1415         rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1416         b_patha_ok = true;
1417     } else {
1418         rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1419         rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1420     }
1421     if (reg_e94 != 0)
1422         rtl8723_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
1423                            final_candidate,
1424                            (reg_ea4 == 0));
1425     rtl8723_save_adda_registers(hw, iqk_bb_reg,
1426                     rtlphy->iqk_bb_backup, 10);
1427 }
1428 
1429 void rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw)
1430 {
1431     _rtl8723e_phy_lc_calibrate(hw, false);
1432 }
1433 
1434 void rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1435 {
1436     _rtl8723e_phy_set_rfpath_switch(hw, bmain, false);
1437 }
1438 
1439 bool rtl8723e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1440 {
1441     struct rtl_priv *rtlpriv = rtl_priv(hw);
1442     struct rtl_phy *rtlphy = &rtlpriv->phy;
1443     bool postprocessing = false;
1444 
1445     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1446         "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1447         iotype, rtlphy->set_io_inprogress);
1448     do {
1449         switch (iotype) {
1450         case IO_CMD_RESUME_DM_BY_SCAN:
1451             rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1452                 "[IO CMD] Resume DM after scan.\n");
1453             postprocessing = true;
1454             break;
1455         case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1456             rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1457                 "[IO CMD] Pause DM before scan.\n");
1458             postprocessing = true;
1459             break;
1460         default:
1461             rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1462                 "switch case %#x not processed\n", iotype);
1463             break;
1464         }
1465     } while (false);
1466     if (postprocessing && !rtlphy->set_io_inprogress) {
1467         rtlphy->set_io_inprogress = true;
1468         rtlphy->current_io_type = iotype;
1469     } else {
1470         return false;
1471     }
1472     rtl8723e_phy_set_io(hw);
1473     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
1474     return true;
1475 }
1476 
1477 static void rtl8723e_phy_set_io(struct ieee80211_hw *hw)
1478 {
1479     struct rtl_priv *rtlpriv = rtl_priv(hw);
1480     struct rtl_phy *rtlphy = &rtlpriv->phy;
1481     struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
1482 
1483     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1484         "--->Cmd(%#x), set_io_inprogress(%d)\n",
1485         rtlphy->current_io_type, rtlphy->set_io_inprogress);
1486     switch (rtlphy->current_io_type) {
1487     case IO_CMD_RESUME_DM_BY_SCAN:
1488         dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1489         rtl8723e_dm_write_dig(hw);
1490         rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel);
1491         break;
1492     case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1493         rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
1494         dm_digtable->cur_igvalue = 0x17;
1495         rtl8723e_dm_write_dig(hw);
1496         break;
1497     default:
1498         rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1499             "switch case %#x not processed\n",
1500             rtlphy->current_io_type);
1501         break;
1502     }
1503     rtlphy->set_io_inprogress = false;
1504     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1505         "(%#x)\n", rtlphy->current_io_type);
1506 }
1507 
1508 static void rtl8723e_phy_set_rf_on(struct ieee80211_hw *hw)
1509 {
1510     struct rtl_priv *rtlpriv = rtl_priv(hw);
1511 
1512     rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
1513     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1514     rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1515     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1516     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1517     rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1518 }
1519 
1520 static void _rtl8723e_phy_set_rf_sleep(struct ieee80211_hw *hw)
1521 {
1522     u32 u4b_tmp;
1523     u8 delay = 5;
1524     struct rtl_priv *rtlpriv = rtl_priv(hw);
1525 
1526     rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1527     rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1528     rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1529     u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1530     while (u4b_tmp != 0 && delay > 0) {
1531         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
1532         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1533         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1534         u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1535         delay--;
1536     }
1537     if (delay == 0) {
1538         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1539         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1540         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1541         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1542         rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
1543             "Switch RF timeout !!!.\n");
1544         return;
1545     }
1546     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1547     rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
1548 }
1549 
1550 static bool _rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw,
1551                          enum rf_pwrstate rfpwr_state)
1552 {
1553     struct rtl_priv *rtlpriv = rtl_priv(hw);
1554     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1555     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1556     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1557     bool bresult = true;
1558     u8 i, queue_id;
1559     struct rtl8192_tx_ring *ring = NULL;
1560 
1561     switch (rfpwr_state) {
1562     case ERFON:
1563         if ((ppsc->rfpwr_state == ERFOFF) &&
1564             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
1565             bool rtstatus;
1566             u32 initializecount = 0;
1567 
1568             do {
1569                 initializecount++;
1570                 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
1571                     "IPS Set eRf nic enable\n");
1572                 rtstatus = rtl_ps_enable_nic(hw);
1573             } while (!rtstatus && (initializecount < 10));
1574             RT_CLEAR_PS_LEVEL(ppsc,
1575                       RT_RF_OFF_LEVL_HALT_NIC);
1576         } else {
1577             rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
1578                 "Set ERFON slept:%d ms\n",
1579                 jiffies_to_msecs(jiffies -
1580                        ppsc->last_sleep_jiffies));
1581             ppsc->last_awake_jiffies = jiffies;
1582             rtl8723e_phy_set_rf_on(hw);
1583         }
1584         if (mac->link_state == MAC80211_LINKED) {
1585             rtlpriv->cfg->ops->led_control(hw,
1586                                LED_CTL_LINK);
1587         } else {
1588             rtlpriv->cfg->ops->led_control(hw,
1589                                LED_CTL_NO_LINK);
1590         }
1591         break;
1592     case ERFOFF:
1593         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
1594             rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
1595                 "IPS Set eRf nic disable\n");
1596             rtl_ps_disable_nic(hw);
1597             RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1598         } else {
1599             if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
1600                 rtlpriv->cfg->ops->led_control(hw,
1601                         LED_CTL_NO_LINK);
1602             } else {
1603                 rtlpriv->cfg->ops->led_control(hw,
1604                         LED_CTL_POWER_OFF);
1605             }
1606         }
1607         break;
1608     case ERFSLEEP:
1609         if (ppsc->rfpwr_state == ERFOFF)
1610             break;
1611         for (queue_id = 0, i = 0;
1612              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
1613             ring = &pcipriv->dev.tx_ring[queue_id];
1614             if (queue_id == BEACON_QUEUE ||
1615                 skb_queue_len(&ring->queue) == 0) {
1616                 queue_id++;
1617                 continue;
1618             } else {
1619                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1620                     "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
1621                     (i + 1), queue_id,
1622                     skb_queue_len(&ring->queue));
1623 
1624                 udelay(10);
1625                 i++;
1626             }
1627             if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1628                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1629                     "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
1630                     MAX_DOZE_WAITING_TIMES_9x,
1631                     queue_id,
1632                     skb_queue_len(&ring->queue));
1633                 break;
1634             }
1635         }
1636         rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
1637             "Set ERFSLEEP awaked:%d ms\n",
1638             jiffies_to_msecs(jiffies -
1639                ppsc->last_awake_jiffies));
1640         ppsc->last_sleep_jiffies = jiffies;
1641         _rtl8723e_phy_set_rf_sleep(hw);
1642         break;
1643     default:
1644         rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1645             "switch case %#x not processed\n", rfpwr_state);
1646         bresult = false;
1647         break;
1648     }
1649     if (bresult)
1650         ppsc->rfpwr_state = rfpwr_state;
1651     return bresult;
1652 }
1653 
1654 bool rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw,
1655                      enum rf_pwrstate rfpwr_state)
1656 {
1657     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1658 
1659     bool bresult = false;
1660 
1661     if (rfpwr_state == ppsc->rfpwr_state)
1662         return bresult;
1663     bresult = _rtl8723e_phy_set_rf_power_state(hw, rfpwr_state);
1664     return bresult;
1665 }
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