rtlwifi/rtl8723ae/dm.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003
0004 #ifndef __RTL8723E_DM_H__
0005 #define __RTL8723E_DM_H__
0006
0007 #define HAL_DM_DIG_DISABLE          BIT(0)
0008 #define HAL_DM_HIPWR_DISABLE            BIT(1)
0009
0010 #define OFDM_TABLE_LENGTH           37
0011 #define CCK_TABLE_LENGTH            33
0012
0013 #define OFDM_TABLE_SIZE             37
0014 #define CCK_TABLE_SIZE              33
0015
0016 #define BW_AUTO_SWITCH_HIGH_LOW         25
0017 #define BW_AUTO_SWITCH_LOW_HIGH         30
0018
0019 #define DM_DIG_FA_UPPER             0x32
0020 #define DM_DIG_FA_LOWER             0x20
0021 #define DM_DIG_FA_TH0               0x20
0022 #define DM_DIG_FA_TH1               0x100
0023 #define DM_DIG_FA_TH2               0x200
0024
0025 #define RXPATHSELECTION_SS_TH_LOW       30
0026 #define RXPATHSELECTION_DIFF_TH         18
0027
0028 #define DM_RATR_STA_INIT            0
0029 #define DM_RATR_STA_HIGH            1
0030 #define DM_RATR_STA_MIDDLE          2
0031 #define DM_RATR_STA_LOW             3
0032
0033 #define CTS2SELF_THVAL              30
0034 #define REGC38_TH               20
0035
0036 #define WAIOTTHVAL              25
0037
0038 #define TXHIGHPWRLEVEL_NORMAL           0
0039 #define TXHIGHPWRLEVEL_LEVEL1           1
0040 #define TXHIGHPWRLEVEL_LEVEL2           2
0041 #define TXHIGHPWRLEVEL_BT1          3
0042 #define TXHIGHPWRLEVEL_BT2          4
0043
0044 #define DM_TYPE_BYFW                0
0045 #define DM_TYPE_BYDRIVER            1
0046
0047 #define TX_POWER_NEAR_FIELD_THRESH_LVL2     74
0048 #define TX_POWER_NEAR_FIELD_THRESH_LVL1     67
0049
0050 struct swat_t {
0051     u8 failure_cnt;
0052     u8 try_flag;
0053     u8 stop_trying;
0054     long pre_rssi;
0055     long trying_threshold;
0056     u8 cur_antenna;
0057     u8 pre_antenna;
0058
0059 };
0060
0061 enum tag_dynamic_init_gain_operation_type_definition {
0062     DIG_TYPE_THRESH_HIGH = 0,
0063     DIG_TYPE_THRESH_LOW = 1,
0064     DIG_TYPE_BACKOFF = 2,
0065     DIG_TYPE_RX_GAIN_MIN = 3,
0066     DIG_TYPE_RX_GAIN_MAX = 4,
0067     DIG_TYPE_ENABLE = 5,
0068     DIG_TYPE_DISABLE = 6,
0069     DIG_OP_TYPE_MAX
0070 };
0071
0072 enum dm_1r_cca_e {
0073     CCA_1R = 0,
0074     CCA_2R = 1,
0075     CCA_MAX = 2,
0076 };
0077
0078 enum dm_rf_e {
0079     RF_SAVE = 0,
0080     RF_NORMAL = 1,
0081     RF_MAX = 2,
0082 };
0083
0084 enum dm_sw_ant_switch_e {
0085     ANS_ANTENNA_B = 1,
0086     ANS_ANTENNA_A = 2,
0087     ANS_ANTENNA_MAX = 3,
0088 };
0089
0090 #define BT_RSSI_STATE_NORMAL_POWER      BIT_OFFSET_LEN_MASK_32(0, 1)
0091 #define BT_RSSI_STATE_AMDPU_OFF         BIT_OFFSET_LEN_MASK_32(1, 1)
0092 #define BT_RSSI_STATE_SPECIAL_LOW       BIT_OFFSET_LEN_MASK_32(2, 1)
0093 #define BT_RSSI_STATE_BG_EDCA_LOW       BIT_OFFSET_LEN_MASK_32(3, 1)
0094 #define BT_RSSI_STATE_TXPOWER_LOW       BIT_OFFSET_LEN_MASK_32(4, 1)
0095 #define GET_UNDECORATED_AVERAGE_RSSI(_priv)     \
0096     ( \
0097     (((struct rtl_priv *)(_priv))->mac80211.opmode ==       \
0098                  NL80211_IFTYPE_ADHOC) ?            \
0099     (((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) :    \
0100     (((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb)        \
0101     )
0102
0103 void rtl8723e_dm_init(struct ieee80211_hw *hw);
0104 void rtl8723e_dm_watchdog(struct ieee80211_hw *hw);
0105 void rtl8723e_dm_write_dig(struct ieee80211_hw *hw);
0106 void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw);
0107 void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
0108 void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal);
0109 void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw);
0110 #endif