rtlwifi/rtl8723ae/def.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003
0004 #ifndef __RTL8723E_DEF_H__
0005 #define __RTL8723E_DEF_H__
0006
0007 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE     0
0008 #define HAL_PRIME_CHNL_OFFSET_LOWER         1
0009 #define HAL_PRIME_CHNL_OFFSET_UPPER         2
0010
0011 #define RX_MPDU_QUEUE                       0
0012 #define RX_CMD_QUEUE                        1
0013
0014 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
0015 #define CHIP_BONDING_92C_1T2R       0x1
0016
0017 #define CHIP_8723       BIT(0)
0018 #define NORMAL_CHIP     BIT(3)
0019 #define RF_TYPE_1T1R        (~(BIT(4)|BIT(5)|BIT(6)))
0020 #define RF_TYPE_1T2R        BIT(4)
0021 #define RF_TYPE_2T2R        BIT(5)
0022 #define CHIP_VENDOR_UMC     BIT(7)
0023 #define B_CUT_VERSION       BIT(12)
0024 #define C_CUT_VERSION       BIT(13)
0025 #define D_CUT_VERSION       ((BIT(12)|BIT(13)))
0026 #define E_CUT_VERSION       BIT(14)
0027 #define RF_RL_ID        (BIT(31)|BIT(30)|BIT(29)|BIT(28))
0028
0029 /* MASK */
0030 #define IC_TYPE_MASK        (BIT(0)|BIT(1)|BIT(2))
0031 #define CHIP_TYPE_MASK      BIT(3)
0032 #define RF_TYPE_MASK        (BIT(4)|BIT(5)|BIT(6))
0033 #define MANUFACTUER_MASK    BIT(7)
0034 #define ROM_VERSION_MASK    (BIT(11)|BIT(10)|BIT(9)|BIT(8))
0035 #define CUT_VERSION_MASK    (BIT(15)|BIT(14)|BIT(13)|BIT(12))
0036
0037 /* Get element */
0038 #define GET_CVID_IC_TYPE(version)   ((version) & IC_TYPE_MASK)
0039 #define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
0040 #define GET_CVID_RF_TYPE(version)   ((version) & RF_TYPE_MASK)
0041 #define GET_CVID_MANUFACTUER(version)   ((version) & MANUFACTUER_MASK)
0042 #define GET_CVID_ROM_VERSION(version)   ((version) & ROM_VERSION_MASK)
0043 #define GET_CVID_CUT_VERSION(version)   ((version) & CUT_VERSION_MASK)
0044
0045 #define IS_81XXC(version)   ((GET_CVID_IC_TYPE(version) == 0) ?\
0046                         true : false)
0047 #define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723) ? \
0048                         true : false)
0049 #define IS_1T1R(version)    ((GET_CVID_RF_TYPE(version)) ? false : true)
0050 #define IS_1T2R(version)    ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
0051                         ? true : false)
0052 #define IS_2T2R(version)    ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
0053                         ? true : false)
0054 #define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version)) ? \
0055                         true : false)
0056
0057 #define IS_VENDOR_UMC_A_CUT(version)    ((IS_CHIP_VENDOR_UMC(version))\
0058                     ? ((GET_CVID_CUT_VERSION(version)) ? \
0059                     false : true) : false)
0060 #define IS_VENDOR_8723_A_CUT(version)   ((IS_8723_SERIES(version))\
0061                     ? ((GET_CVID_CUT_VERSION(version)) ? \
0062                     false : true) : false)
0063 #define IS_VENDOR_8723A_B_CUT(version)  ((IS_8723_SERIES(version))\
0064         ? ((GET_CVID_CUT_VERSION(version) == \
0065         B_CUT_VERSION) ? true : false) : false)
0066 #define IS_81XXC_VENDOR_UMC_B_CUT(version)  ((IS_CHIP_VENDOR_UMC(version))\
0067         ? ((GET_CVID_CUT_VERSION(version) == \
0068         B_CUT_VERSION) ? true : false) : false)
0069
0070 enum rf_optype {
0071     RF_OP_BY_SW_3WIRE = 0,
0072     RF_OP_BY_FW,
0073     RF_OP_MAX
0074 };
0075
0076 enum rf_power_state {
0077     RF_ON,
0078     RF_OFF,
0079     RF_SLEEP,
0080     RF_SHUT_DOWN,
0081 };
0082
0083 enum power_save_mode {
0084     POWER_SAVE_MODE_ACTIVE,
0085     POWER_SAVE_MODE_SAVE,
0086 };
0087
0088 enum power_policy_config {
0089     POWERCFG_MAX_POWER_SAVINGS,
0090     POWERCFG_GLOBAL_POWER_SAVINGS,
0091     POWERCFG_LOCAL_POWER_SAVINGS,
0092     POWERCFG_LENOVO,
0093 };
0094
0095 enum interface_select_pci {
0096     INTF_SEL1_MINICARD = 0,
0097     INTF_SEL0_PCIE = 1,
0098     INTF_SEL2_RSV = 2,
0099     INTF_SEL3_RSV = 3,
0100 };
0101
0102 enum rtl_desc_qsel {
0103     QSLT_BK = 0x2,
0104     QSLT_BE = 0x0,
0105     QSLT_VI = 0x5,
0106     QSLT_VO = 0x7,
0107     QSLT_BEACON = 0x10,
0108     QSLT_HIGH = 0x11,
0109     QSLT_MGNT = 0x12,
0110     QSLT_CMD = 0x13,
0111 };
0112
0113 enum rtl_desc8723e_rate {
0114     DESC92C_RATE1M = 0x00,
0115     DESC92C_RATE2M = 0x01,
0116     DESC92C_RATE5_5M = 0x02,
0117     DESC92C_RATE11M = 0x03,
0118
0119     DESC92C_RATE6M = 0x04,
0120     DESC92C_RATE9M = 0x05,
0121     DESC92C_RATE12M = 0x06,
0122     DESC92C_RATE18M = 0x07,
0123     DESC92C_RATE24M = 0x08,
0124     DESC92C_RATE36M = 0x09,
0125     DESC92C_RATE48M = 0x0a,
0126     DESC92C_RATE54M = 0x0b,
0127
0128     DESC92C_RATEMCS0 = 0x0c,
0129     DESC92C_RATEMCS1 = 0x0d,
0130     DESC92C_RATEMCS2 = 0x0e,
0131     DESC92C_RATEMCS3 = 0x0f,
0132     DESC92C_RATEMCS4 = 0x10,
0133     DESC92C_RATEMCS5 = 0x11,
0134     DESC92C_RATEMCS6 = 0x12,
0135     DESC92C_RATEMCS7 = 0x13,
0136     DESC92C_RATEMCS8 = 0x14,
0137     DESC92C_RATEMCS9 = 0x15,
0138     DESC92C_RATEMCS10 = 0x16,
0139     DESC92C_RATEMCS11 = 0x17,
0140     DESC92C_RATEMCS12 = 0x18,
0141     DESC92C_RATEMCS13 = 0x19,
0142     DESC92C_RATEMCS14 = 0x1a,
0143     DESC92C_RATEMCS15 = 0x1b,
0144     DESC92C_RATEMCS15_SG = 0x1c,
0145     DESC92C_RATEMCS32 = 0x20,
0146 };
0147
0148 struct phy_sts_cck_8723e_t {
0149     u8 adc_pwdb_X[4];
0150     u8 sq_rpt;
0151     u8 cck_agc_rpt;
0152 };
0153
0154 struct h2c_cmd_8723e {
0155     u8 element_id;
0156     u32 cmd_len;
0157     u8 *p_cmdbuffer;
0158 };
0159
0160 #endif