rtlwifi/rtl8192se/sw.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003
0004 #include "../wifi.h"
0005 #include "../core.h"
0006 #include "../base.h"
0007 #include "../pci.h"
0008 #include "reg.h"
0009 #include "def.h"
0010 #include "phy.h"
0011 #include "dm.h"
0012 #include "fw.h"
0013 #include "hw.h"
0014 #include "trx.h"
0015 #include "led.h"
0016
0017 #include <linux/module.h>
0018
0019 static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
0020 {
0021     struct rtl_priv *rtlpriv = rtl_priv(hw);
0022     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0023
0024     /*close ASPM for AMD defaultly */
0025     rtlpci->const_amdpci_aspm = 0;
0026
0027     /* ASPM PS mode.
0028      * 0 - Disable ASPM,
0029      * 1 - Enable ASPM without Clock Req,
0030      * 2 - Enable ASPM with Clock Req,
0031      * 3 - Alwyas Enable ASPM with Clock Req,
0032      * 4 - Always Enable ASPM without Clock Req.
0033      * set defult to RTL8192CE:3 RTL8192E:2
0034      * */
0035     rtlpci->const_pci_aspm = 2;
0036
0037     /*Setting for PCI-E device */
0038     rtlpci->const_devicepci_aspm_setting = 0x03;
0039
0040     /*Setting for PCI-E bridge */
0041     rtlpci->const_hostpci_aspm_setting = 0x02;
0042
0043     /* In Hw/Sw Radio Off situation.
0044      * 0 - Default,
0045      * 1 - From ASPM setting without low Mac Pwr,
0046      * 2 - From ASPM setting with low Mac Pwr,
0047      * 3 - Bus D3
0048      * set default to RTL8192CE:0 RTL8192SE:2
0049      */
0050     rtlpci->const_hwsw_rfoff_d3 = 2;
0051
0052     /* This setting works for those device with
0053      * backdoor ASPM setting such as EPHY setting.
0054      * 0 - Not support ASPM,
0055      * 1 - Support ASPM,
0056      * 2 - According to chipset.
0057      */
0058     rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
0059 }
0060
0061 static void rtl92se_fw_cb(const struct firmware *firmware, void *context)
0062 {
0063     struct ieee80211_hw *hw = context;
0064     struct rtl_priv *rtlpriv = rtl_priv(hw);
0065     struct rt_firmware *pfirmware = NULL;
0066     char *fw_name = "rtlwifi/rtl8192sefw.bin";
0067
0068     rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
0069         "Firmware callback routine entered!\n");
0070     complete(&rtlpriv->firmware_loading_complete);
0071     if (!firmware) {
0072         pr_err("Firmware %s not available\n", fw_name);
0073         rtlpriv->max_fw_size = 0;
0074         return;
0075     }
0076     if (firmware->size > rtlpriv->max_fw_size) {
0077         pr_err("Firmware is too big!\n");
0078         rtlpriv->max_fw_size = 0;
0079         release_firmware(firmware);
0080         return;
0081     }
0082     pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
0083     memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
0084     pfirmware->sz_fw_tmpbufferlen = firmware->size;
0085     release_firmware(firmware);
0086 }
0087
0088 static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
0089 {
0090     struct rtl_priv *rtlpriv = rtl_priv(hw);
0091     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0092     int err = 0;
0093     u16 earlyrxthreshold = 7;
0094     char *fw_name = "rtlwifi/rtl8192sefw.bin";
0095
0096     rtlpriv->dm.dm_initialgain_enable = true;
0097     rtlpriv->dm.dm_flag = 0;
0098     rtlpriv->dm.disable_framebursting = false;
0099     rtlpriv->dm.thermalvalue = 0;
0100     rtlpriv->dm.useramask = true;
0101
0102     /* compatible 5G band 91se just 2.4G band & smsp */
0103     rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
0104     rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
0105     rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
0106
0107     rtlpci->transmit_config = 0;
0108
0109     rtlpci->receive_config =
0110             RCR_APPFCS |
0111             RCR_APWRMGT |
0112             /*RCR_ADD3 |*/
0113             RCR_AMF |
0114             RCR_ADF |
0115             RCR_APP_MIC |
0116             RCR_APP_ICV |
0117             RCR_AICV |
0118             /* Accept ICV error, CRC32 Error */
0119             RCR_ACRC32 |
0120             RCR_AB |
0121             /* Accept Broadcast, Multicast */
0122             RCR_AM  |
0123             /* Accept Physical match */
0124             RCR_APM |
0125             /* Accept Destination Address packets */
0126             /*RCR_AAP |*/
0127             RCR_APP_PHYST_STAFF |
0128             /* Accept PHY status */
0129             RCR_APP_PHYST_RXFF |
0130             (earlyrxthreshold << RCR_FIFO_OFFSET);
0131
0132     rtlpci->irq_mask[0] = (u32)
0133             (IMR_ROK |
0134             IMR_VODOK |
0135             IMR_VIDOK |
0136             IMR_BEDOK |
0137             IMR_BKDOK |
0138             IMR_HCCADOK |
0139             IMR_MGNTDOK |
0140             IMR_COMDOK |
0141             IMR_HIGHDOK |
0142             IMR_BDOK |
0143             IMR_RXCMDOK |
0144             /*IMR_TIMEOUT0 |*/
0145             IMR_RDU |
0146             IMR_RXFOVW  |
0147             IMR_BCNINT
0148             /*| IMR_TXFOVW*/
0149             /*| IMR_TBDOK |
0150             IMR_TBDER*/);
0151
0152     rtlpci->irq_mask[1] = (u32) 0;
0153
0154     rtlpci->shortretry_limit = 0x30;
0155     rtlpci->longretry_limit = 0x30;
0156
0157     rtlpci->first_init = true;
0158
0159     /* for LPS & IPS */
0160     rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
0161     rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
0162     rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
0163     if (!rtlpriv->psc.inactiveps)
0164         pr_info("Power Save off (module option)\n");
0165     if (!rtlpriv->psc.fwctrl_lps)
0166         pr_info("FW Power Save off (module option)\n");
0167     rtlpriv->psc.reg_fwctrl_lps = 3;
0168     rtlpriv->psc.reg_max_lps_awakeintvl = 5;
0169     /* for ASPM, you can close aspm through
0170      * set const_support_pciaspm = 0 */
0171     rtl92s_init_aspm_vars(hw);
0172
0173     if (rtlpriv->psc.reg_fwctrl_lps == 1)
0174         rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
0175     else if (rtlpriv->psc.reg_fwctrl_lps == 2)
0176         rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
0177     else if (rtlpriv->psc.reg_fwctrl_lps == 3)
0178         rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
0179
0180     /* for firmware buf */
0181     rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));
0182     if (!rtlpriv->rtlhal.pfirmware)
0183         return 1;
0184
0185     rtlpriv->max_fw_size = RTL8190_MAX_FIRMWARE_CODE_SIZE*2 +
0186                    sizeof(struct fw_hdr);
0187     pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
0188         "Loading firmware %s\n", fw_name);
0189     /* request fw */
0190     err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
0191                       rtlpriv->io.dev, GFP_KERNEL, hw,
0192                       rtl92se_fw_cb);
0193     if (err) {
0194         pr_err("Failed to request firmware!\n");
0195         vfree(rtlpriv->rtlhal.pfirmware);
0196         rtlpriv->rtlhal.pfirmware = NULL;
0197         return 1;
0198     }
0199
0200     return err;
0201 }
0202
0203 static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)
0204 {
0205     struct rtl_priv *rtlpriv = rtl_priv(hw);
0206
0207     if (rtlpriv->rtlhal.pfirmware) {
0208         vfree(rtlpriv->rtlhal.pfirmware);
0209         rtlpriv->rtlhal.pfirmware = NULL;
0210     }
0211 }
0212
0213 static bool rtl92se_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue,
0214                       u16 index)
0215 {
0216     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0217     struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
0218     u8 *entry = (u8 *)(&ring->desc[ring->idx]);
0219     u8 own = (u8)rtl92se_get_desc(hw, entry, true, HW_DESC_OWN);
0220
0221     if (own)
0222         return false;
0223     return true;
0224 }
0225
0226 static struct rtl_hal_ops rtl8192se_hal_ops = {
0227     .init_sw_vars = rtl92s_init_sw_vars,
0228     .deinit_sw_vars = rtl92s_deinit_sw_vars,
0229     .read_eeprom_info = rtl92se_read_eeprom_info,
0230     .interrupt_recognized = rtl92se_interrupt_recognized,
0231     .hw_init = rtl92se_hw_init,
0232     .hw_disable = rtl92se_card_disable,
0233     .hw_suspend = rtl92se_suspend,
0234     .hw_resume = rtl92se_resume,
0235     .enable_interrupt = rtl92se_enable_interrupt,
0236     .disable_interrupt = rtl92se_disable_interrupt,
0237     .set_network_type = rtl92se_set_network_type,
0238     .set_chk_bssid = rtl92se_set_check_bssid,
0239     .set_qos = rtl92se_set_qos,
0240     .set_bcn_reg = rtl92se_set_beacon_related_registers,
0241     .set_bcn_intv = rtl92se_set_beacon_interval,
0242     .update_interrupt_mask = rtl92se_update_interrupt_mask,
0243     .get_hw_reg = rtl92se_get_hw_reg,
0244     .set_hw_reg = rtl92se_set_hw_reg,
0245     .update_rate_tbl = rtl92se_update_hal_rate_tbl,
0246     .fill_tx_desc = rtl92se_tx_fill_desc,
0247     .fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,
0248     .query_rx_desc = rtl92se_rx_query_desc,
0249     .set_channel_access = rtl92se_update_channel_access_setting,
0250     .radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,
0251     .set_bw_mode = rtl92s_phy_set_bw_mode,
0252     .switch_channel = rtl92s_phy_sw_chnl,
0253     .dm_watchdog = rtl92s_dm_watchdog,
0254     .scan_operation_backup = rtl92s_phy_scan_operation_backup,
0255     .set_rf_power_state = rtl92s_phy_set_rf_power_state,
0256     .led_control = rtl92se_led_control,
0257     .set_desc = rtl92se_set_desc,
0258     .get_desc = rtl92se_get_desc,
0259     .is_tx_desc_closed = rtl92se_is_tx_desc_closed,
0260     .tx_polling = rtl92se_tx_polling,
0261     .enable_hw_sec = rtl92se_enable_hw_security_config,
0262     .set_key = rtl92se_set_key,
0263     .init_sw_leds = rtl92se_init_sw_leds,
0264     .get_bbreg = rtl92s_phy_query_bb_reg,
0265     .set_bbreg = rtl92s_phy_set_bb_reg,
0266     .get_rfreg = rtl92s_phy_query_rf_reg,
0267     .set_rfreg = rtl92s_phy_set_rf_reg,
0268     .get_btc_status = rtl_btc_status_false,
0269 };
0270
0271 static struct rtl_mod_params rtl92se_mod_params = {
0272     .sw_crypto = false,
0273     .inactiveps = true,
0274     .swctrl_lps = true,
0275     .fwctrl_lps = false,
0276     .aspm_support = 2,
0277     .debug_level = 0,
0278     .debug_mask = 0,
0279 };
0280
0281 /* Because memory R/W bursting will cause system hang/crash
0282  * for 92se, so we don't read back after every write action */
0283 static const struct rtl_hal_cfg rtl92se_hal_cfg = {
0284     .bar_id = 1,
0285     .write_readback = false,
0286     .name = "rtl92s_pci",
0287     .ops = &rtl8192se_hal_ops,
0288     .mod_params = &rtl92se_mod_params,
0289
0290     .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
0291     .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
0292     .maps[SYS_CLK] = SYS_CLKR,
0293     .maps[MAC_RCR_AM] = RCR_AM,
0294     .maps[MAC_RCR_AB] = RCR_AB,
0295     .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
0296     .maps[MAC_RCR_ACF] = RCR_ACF,
0297     .maps[MAC_RCR_AAP] = RCR_AAP,
0298     .maps[MAC_HIMR] = INTA_MASK,
0299     .maps[MAC_HIMRE] = INTA_MASK + 4,
0300
0301     .maps[EFUSE_TEST] = REG_EFUSE_TEST,
0302     .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
0303     .maps[EFUSE_CLK] = REG_EFUSE_CLK,
0304     .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
0305     .maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */
0306     .maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */
0307     .maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */
0308     .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
0309     .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,
0310     .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
0311     .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
0312     .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
0313
0314     .maps[RWCAM] = REG_RWCAM,
0315     .maps[WCAMI] = REG_WCAMI,
0316     .maps[RCAMO] = REG_RCAMO,
0317     .maps[CAMDBG] = REG_CAMDBG,
0318     .maps[SECR] = REG_SECR,
0319     .maps[SEC_CAM_NONE] = CAM_NONE,
0320     .maps[SEC_CAM_WEP40] = CAM_WEP40,
0321     .maps[SEC_CAM_TKIP] = CAM_TKIP,
0322     .maps[SEC_CAM_AES] = CAM_AES,
0323     .maps[SEC_CAM_WEP104] = CAM_WEP104,
0324
0325     .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
0326     .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
0327     .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
0328     .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
0329     .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
0330     .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
0331     .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
0332     .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
0333     .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
0334     .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
0335     .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
0336     .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
0337     .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
0338     .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
0339     .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
0340     .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
0341
0342     .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
0343     .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
0344     .maps[RTL_IMR_BCNINT] = IMR_BCNINT,
0345     .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
0346     .maps[RTL_IMR_RDU] = IMR_RDU,
0347     .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
0348     .maps[RTL_IMR_BDOK] = IMR_BDOK,
0349     .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
0350     .maps[RTL_IMR_TBDER] = IMR_TBDER,
0351     .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
0352     .maps[RTL_IMR_COMDOK] = IMR_COMDOK,
0353     .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
0354     .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
0355     .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
0356     .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
0357     .maps[RTL_IMR_VODOK] = IMR_VODOK,
0358     .maps[RTL_IMR_ROK] = IMR_ROK,
0359     .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
0360
0361     .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
0362     .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
0363     .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
0364     .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
0365     .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
0366     .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
0367     .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
0368     .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
0369     .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
0370     .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
0371     .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
0372     .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
0373
0374     .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
0375     .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
0376 };
0377
0378 static const struct pci_device_id rtl92se_pci_ids[] = {
0379     {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},
0380     {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},
0381     {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},
0382     {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},
0383     {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},
0384     {},
0385 };
0386
0387 MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);
0388
0389 MODULE_AUTHOR("lizhaoming   <chaoming_li@realsil.com.cn>");
0390 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
0391 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
0392 MODULE_LICENSE("GPL");
0393 MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
0394 MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");
0395
0396 module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);
0397 module_param_named(debug_level, rtl92se_mod_params.debug_level, int, 0644);
0398 module_param_named(debug_mask, rtl92se_mod_params.debug_mask, ullong, 0644);
0399 module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);
0400 module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);
0401 module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);
0402 module_param_named(aspm, rtl92se_mod_params.aspm_support, int, 0444);
0403 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
0404 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
0405 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
0406 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");
0407 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
0408 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
0409 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
0410
0411 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
0412
0413 static struct pci_driver rtl92se_driver = {
0414     .name = KBUILD_MODNAME,
0415     .id_table = rtl92se_pci_ids,
0416     .probe = rtl_pci_probe,
0417     .remove = rtl_pci_disconnect,
0418     .driver.pm = &rtlwifi_pm_ops,
0419 };
0420
0421 module_pci_driver(rtl92se_driver);