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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003 
0004 #include "../wifi.h"
0005 #include "../pci.h"
0006 #include "../ps.h"
0007 #include "../core.h"
0008 #include "reg.h"
0009 #include "def.h"
0010 #include "phy.h"
0011 #include "rf.h"
0012 #include "dm.h"
0013 #include "fw.h"
0014 #include "hw.h"
0015 #include "table.h"
0016 
0017 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask)
0018 {
0019     u32 i = ffs(bitmask);
0020 
0021     return i ? i - 1 : 32;
0022 }
0023 
0024 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
0025 {
0026     struct rtl_priv *rtlpriv = rtl_priv(hw);
0027     u32 returnvalue = 0, originalvalue, bitshift;
0028 
0029     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
0030         regaddr, bitmask);
0031 
0032     originalvalue = rtl_read_dword(rtlpriv, regaddr);
0033     bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
0034     returnvalue = (originalvalue & bitmask) >> bitshift;
0035 
0036     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
0037         bitmask, regaddr, originalvalue);
0038 
0039     return returnvalue;
0040 
0041 }
0042 
0043 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
0044                u32 data)
0045 {
0046     struct rtl_priv *rtlpriv = rtl_priv(hw);
0047     u32 originalvalue, bitshift;
0048 
0049     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0050         "regaddr(%#x), bitmask(%#x), data(%#x)\n",
0051         regaddr, bitmask, data);
0052 
0053     if (bitmask != MASKDWORD) {
0054         originalvalue = rtl_read_dword(rtlpriv, regaddr);
0055         bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
0056         data = ((originalvalue & (~bitmask)) | (data << bitshift));
0057     }
0058 
0059     rtl_write_dword(rtlpriv, regaddr, data);
0060 
0061     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0062         "regaddr(%#x), bitmask(%#x), data(%#x)\n",
0063         regaddr, bitmask, data);
0064 
0065 }
0066 
0067 static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw,
0068                       enum radio_path rfpath, u32 offset)
0069 {
0070 
0071     struct rtl_priv *rtlpriv = rtl_priv(hw);
0072     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0073     struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
0074     u32 newoffset;
0075     u32 tmplong, tmplong2;
0076     u8 rfpi_enable = 0;
0077     u32 retvalue = 0;
0078 
0079     offset &= 0x3f;
0080     newoffset = offset;
0081 
0082     tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
0083 
0084     if (rfpath == RF90_PATH_A)
0085         tmplong2 = tmplong;
0086     else
0087         tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
0088 
0089     tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) |
0090             BLSSI_READEDGE;
0091 
0092     rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
0093               tmplong & (~BLSSI_READEDGE));
0094 
0095     mdelay(1);
0096 
0097     rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
0098     mdelay(1);
0099 
0100     rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |
0101               BLSSI_READEDGE);
0102     mdelay(1);
0103 
0104     if (rfpath == RF90_PATH_A)
0105         rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
0106                         BIT(8));
0107     else if (rfpath == RF90_PATH_B)
0108         rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
0109                         BIT(8));
0110 
0111     if (rfpi_enable)
0112         retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
0113                      BLSSI_READBACK_DATA);
0114     else
0115         retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
0116                      BLSSI_READBACK_DATA);
0117 
0118     retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
0119                  BLSSI_READBACK_DATA);
0120 
0121     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
0122         rfpath, pphyreg->rf_rb, retvalue);
0123 
0124     return retvalue;
0125 
0126 }
0127 
0128 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw,
0129                     enum radio_path rfpath, u32 offset,
0130                     u32 data)
0131 {
0132     struct rtl_priv *rtlpriv = rtl_priv(hw);
0133     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0134     struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
0135     u32 data_and_addr = 0;
0136     u32 newoffset;
0137 
0138     offset &= 0x3f;
0139     newoffset = offset;
0140 
0141     data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
0142     rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
0143 
0144     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
0145         rfpath, pphyreg->rf3wire_offset, data_and_addr);
0146 }
0147 
0148 
0149 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
0150                 u32 regaddr, u32 bitmask)
0151 {
0152     struct rtl_priv *rtlpriv = rtl_priv(hw);
0153     u32 original_value, readback_value, bitshift;
0154 
0155     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0156         "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
0157          regaddr, rfpath, bitmask);
0158 
0159     spin_lock(&rtlpriv->locks.rf_lock);
0160 
0161     original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr);
0162 
0163     bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
0164     readback_value = (original_value & bitmask) >> bitshift;
0165 
0166     spin_unlock(&rtlpriv->locks.rf_lock);
0167 
0168     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0169         "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
0170         regaddr, rfpath, bitmask, original_value);
0171 
0172     return readback_value;
0173 }
0174 
0175 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
0176                u32 regaddr, u32 bitmask, u32 data)
0177 {
0178     struct rtl_priv *rtlpriv = rtl_priv(hw);
0179     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0180     u32 original_value, bitshift;
0181 
0182     if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
0183         return;
0184 
0185     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0186         "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
0187         regaddr, bitmask, data, rfpath);
0188 
0189     spin_lock(&rtlpriv->locks.rf_lock);
0190 
0191     if (bitmask != RFREG_OFFSET_MASK) {
0192         original_value = _rtl92s_phy_rf_serial_read(hw, rfpath,
0193                                 regaddr);
0194         bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
0195         data = ((original_value & (~bitmask)) | (data << bitshift));
0196     }
0197 
0198     _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data);
0199 
0200     spin_unlock(&rtlpriv->locks.rf_lock);
0201 
0202     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0203         "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
0204         regaddr, bitmask, data, rfpath);
0205 
0206 }
0207 
0208 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw,
0209                       u8 operation)
0210 {
0211     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0212 
0213     if (!is_hal_stop(rtlhal)) {
0214         switch (operation) {
0215         case SCAN_OPT_BACKUP:
0216             rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN);
0217             break;
0218         case SCAN_OPT_RESTORE:
0219             rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN);
0220             break;
0221         default:
0222             pr_err("Unknown operation\n");
0223             break;
0224         }
0225     }
0226 }
0227 
0228 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
0229                 enum nl80211_channel_type ch_type)
0230 {
0231     struct rtl_priv *rtlpriv = rtl_priv(hw);
0232     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0233     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0234     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
0235     u8 reg_bw_opmode;
0236 
0237     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
0238         rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
0239         "20MHz" : "40MHz");
0240 
0241     if (rtlphy->set_bwmode_inprogress)
0242         return;
0243     if (is_hal_stop(rtlhal))
0244         return;
0245 
0246     rtlphy->set_bwmode_inprogress = true;
0247 
0248     reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE);
0249     /* dummy read */
0250     rtl_read_byte(rtlpriv, RRSR + 2);
0251 
0252     switch (rtlphy->current_chan_bw) {
0253     case HT_CHANNEL_WIDTH_20:
0254         reg_bw_opmode |= BW_OPMODE_20MHZ;
0255         rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
0256         break;
0257     case HT_CHANNEL_WIDTH_20_40:
0258         reg_bw_opmode &= ~BW_OPMODE_20MHZ;
0259         rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
0260         break;
0261     default:
0262         pr_err("unknown bandwidth: %#X\n",
0263                rtlphy->current_chan_bw);
0264         break;
0265     }
0266 
0267     switch (rtlphy->current_chan_bw) {
0268     case HT_CHANNEL_WIDTH_20:
0269         rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
0270         rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
0271 
0272         if (rtlhal->version >= VERSION_8192S_BCUT)
0273             rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58);
0274         break;
0275     case HT_CHANNEL_WIDTH_20_40:
0276         rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
0277         rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
0278 
0279         rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
0280                 (mac->cur_40_prime_sc >> 1));
0281         rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
0282 
0283         if (rtlhal->version >= VERSION_8192S_BCUT)
0284             rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18);
0285         break;
0286     default:
0287         pr_err("unknown bandwidth: %#X\n",
0288                rtlphy->current_chan_bw);
0289         break;
0290     }
0291 
0292     rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
0293     rtlphy->set_bwmode_inprogress = false;
0294     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
0295 }
0296 
0297 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
0298         u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
0299         u32 para1, u32 para2, u32 msdelay)
0300 {
0301     struct swchnlcmd *pcmd;
0302 
0303     if (cmdtable == NULL) {
0304         WARN_ONCE(true, "rtl8192se: cmdtable cannot be NULL\n");
0305         return false;
0306     }
0307 
0308     if (cmdtableidx >= cmdtablesz)
0309         return false;
0310 
0311     pcmd = cmdtable + cmdtableidx;
0312     pcmd->cmdid = cmdid;
0313     pcmd->para1 = para1;
0314     pcmd->para2 = para2;
0315     pcmd->msdelay = msdelay;
0316 
0317     return true;
0318 }
0319 
0320 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
0321          u8 channel, u8 *stage, u8 *step, u32 *delay)
0322 {
0323     struct rtl_priv *rtlpriv = rtl_priv(hw);
0324     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0325     struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
0326     u32 precommoncmdcnt;
0327     struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
0328     u32 postcommoncmdcnt;
0329     struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
0330     u32 rfdependcmdcnt;
0331     struct swchnlcmd *currentcmd = NULL;
0332     u8 rfpath;
0333     u8 num_total_rfpath = rtlphy->num_total_rfpath;
0334 
0335     precommoncmdcnt = 0;
0336     _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
0337             MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
0338     _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
0339             MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
0340 
0341     postcommoncmdcnt = 0;
0342 
0343     _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
0344             MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
0345 
0346     rfdependcmdcnt = 0;
0347 
0348     WARN_ONCE((channel < 1 || channel > 14),
0349           "rtl8192se: invalid channel for Zebra: %d\n", channel);
0350 
0351     _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
0352                      MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
0353                      RF_CHNLBW, channel, 10);
0354 
0355     _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
0356             MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
0357 
0358     do {
0359         switch (*stage) {
0360         case 0:
0361             currentcmd = &precommoncmd[*step];
0362             break;
0363         case 1:
0364             currentcmd = &rfdependcmd[*step];
0365             break;
0366         case 2:
0367             currentcmd = &postcommoncmd[*step];
0368             break;
0369         default:
0370             return true;
0371         }
0372 
0373         if (currentcmd->cmdid == CMDID_END) {
0374             if ((*stage) == 2) {
0375                 return true;
0376             } else {
0377                 (*stage)++;
0378                 (*step) = 0;
0379                 continue;
0380             }
0381         }
0382 
0383         switch (currentcmd->cmdid) {
0384         case CMDID_SET_TXPOWEROWER_LEVEL:
0385             rtl92s_phy_set_txpower(hw, channel);
0386             break;
0387         case CMDID_WRITEPORT_ULONG:
0388             rtl_write_dword(rtlpriv, currentcmd->para1,
0389                     currentcmd->para2);
0390             break;
0391         case CMDID_WRITEPORT_USHORT:
0392             rtl_write_word(rtlpriv, currentcmd->para1,
0393                        (u16)currentcmd->para2);
0394             break;
0395         case CMDID_WRITEPORT_UCHAR:
0396             rtl_write_byte(rtlpriv, currentcmd->para1,
0397                        (u8)currentcmd->para2);
0398             break;
0399         case CMDID_RF_WRITEREG:
0400             for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
0401                 rtlphy->rfreg_chnlval[rfpath] =
0402                      ((rtlphy->rfreg_chnlval[rfpath] &
0403                      0xfffffc00) | currentcmd->para2);
0404                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
0405                           currentcmd->para1,
0406                           RFREG_OFFSET_MASK,
0407                           rtlphy->rfreg_chnlval[rfpath]);
0408             }
0409             break;
0410         default:
0411             pr_err("switch case %#x not processed\n",
0412                    currentcmd->cmdid);
0413             break;
0414         }
0415 
0416         break;
0417     } while (true);
0418 
0419     (*delay) = currentcmd->msdelay;
0420     (*step)++;
0421     return false;
0422 }
0423 
0424 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw)
0425 {
0426     struct rtl_priv *rtlpriv = rtl_priv(hw);
0427     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0428     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0429     u32 delay;
0430     bool ret;
0431 
0432     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
0433         rtlphy->current_channel);
0434 
0435     if (rtlphy->sw_chnl_inprogress)
0436         return 0;
0437 
0438     if (rtlphy->set_bwmode_inprogress)
0439         return 0;
0440 
0441     if (is_hal_stop(rtlhal))
0442         return 0;
0443 
0444     rtlphy->sw_chnl_inprogress = true;
0445     rtlphy->sw_chnl_stage = 0;
0446     rtlphy->sw_chnl_step = 0;
0447 
0448     do {
0449         if (!rtlphy->sw_chnl_inprogress)
0450             break;
0451 
0452         ret = _rtl92s_phy_sw_chnl_step_by_step(hw,
0453                  rtlphy->current_channel,
0454                  &rtlphy->sw_chnl_stage,
0455                  &rtlphy->sw_chnl_step, &delay);
0456         if (!ret) {
0457             if (delay > 0)
0458                 mdelay(delay);
0459             else
0460                 continue;
0461         } else {
0462             rtlphy->sw_chnl_inprogress = false;
0463         }
0464         break;
0465     } while (true);
0466 
0467     rtlphy->sw_chnl_inprogress = false;
0468 
0469     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
0470 
0471     return 1;
0472 }
0473 
0474 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw)
0475 {
0476     struct rtl_priv *rtlpriv = rtl_priv(hw);
0477     u8 u1btmp;
0478 
0479     u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
0480     u1btmp |= BIT(0);
0481 
0482     rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
0483     rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
0484     rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
0485     rtl_write_word(rtlpriv, CMDR, 0x57FC);
0486     udelay(100);
0487 
0488     rtl_write_word(rtlpriv, CMDR, 0x77FC);
0489     rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
0490     udelay(10);
0491 
0492     rtl_write_word(rtlpriv, CMDR, 0x37FC);
0493     udelay(10);
0494 
0495     rtl_write_word(rtlpriv, CMDR, 0x77FC);
0496     udelay(10);
0497 
0498     rtl_write_word(rtlpriv, CMDR, 0x57FC);
0499 
0500     /* we should chnge GPIO to input mode
0501      * this will drop away current about 25mA*/
0502     rtl8192se_gpiobit3_cfg_inputmode(hw);
0503 }
0504 
0505 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
0506                    enum rf_pwrstate rfpwr_state)
0507 {
0508     struct rtl_priv *rtlpriv = rtl_priv(hw);
0509     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
0510     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
0511     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
0512     bool bresult = true;
0513     u8 i, queue_id;
0514     struct rtl8192_tx_ring *ring = NULL;
0515 
0516     if (rfpwr_state == ppsc->rfpwr_state)
0517         return false;
0518 
0519     switch (rfpwr_state) {
0520     case ERFON:{
0521             if ((ppsc->rfpwr_state == ERFOFF) &&
0522                 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
0523 
0524                 bool rtstatus;
0525                 u32 initializecount = 0;
0526                 do {
0527                     initializecount++;
0528                     rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
0529                         "IPS Set eRf nic enable\n");
0530                     rtstatus = rtl_ps_enable_nic(hw);
0531                 } while (!rtstatus && (initializecount < 10));
0532 
0533                 RT_CLEAR_PS_LEVEL(ppsc,
0534                           RT_RF_OFF_LEVL_HALT_NIC);
0535             } else {
0536                 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
0537                     "awake, slept:%d ms state_inap:%x\n",
0538                     jiffies_to_msecs(jiffies -
0539                     ppsc->last_sleep_jiffies),
0540                     rtlpriv->psc.state_inap);
0541                 ppsc->last_awake_jiffies = jiffies;
0542                 rtl_write_word(rtlpriv, CMDR, 0x37FC);
0543                 rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
0544                 rtl_write_byte(rtlpriv, PHY_CCA, 0x3);
0545             }
0546 
0547             if (mac->link_state == MAC80211_LINKED)
0548                 rtlpriv->cfg->ops->led_control(hw,
0549                              LED_CTL_LINK);
0550             else
0551                 rtlpriv->cfg->ops->led_control(hw,
0552                              LED_CTL_NO_LINK);
0553             break;
0554         }
0555     case ERFOFF:{
0556             if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
0557                 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
0558                     "IPS Set eRf nic disable\n");
0559                 rtl_ps_disable_nic(hw);
0560                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
0561             } else {
0562                 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
0563                     rtlpriv->cfg->ops->led_control(hw,
0564                              LED_CTL_NO_LINK);
0565                 else
0566                     rtlpriv->cfg->ops->led_control(hw,
0567                              LED_CTL_POWER_OFF);
0568             }
0569             break;
0570         }
0571     case ERFSLEEP:
0572             if (ppsc->rfpwr_state == ERFOFF)
0573                 return false;
0574 
0575             for (queue_id = 0, i = 0;
0576                  queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
0577                 ring = &pcipriv->dev.tx_ring[queue_id];
0578                 if (skb_queue_len(&ring->queue) == 0 ||
0579                     queue_id == BEACON_QUEUE) {
0580                     queue_id++;
0581                     continue;
0582                 } else {
0583                     rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
0584                         "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
0585                         i + 1, queue_id,
0586                         skb_queue_len(&ring->queue));
0587 
0588                     udelay(10);
0589                     i++;
0590                 }
0591 
0592                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
0593                     rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
0594                         "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
0595                         MAX_DOZE_WAITING_TIMES_9x,
0596                         queue_id,
0597                         skb_queue_len(&ring->queue));
0598                     break;
0599                 }
0600             }
0601 
0602             rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
0603                 "Set ERFSLEEP awaked:%d ms\n",
0604                 jiffies_to_msecs(jiffies -
0605                          ppsc->last_awake_jiffies));
0606 
0607             rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
0608                 "sleep awaked:%d ms state_inap:%x\n",
0609                 jiffies_to_msecs(jiffies -
0610                          ppsc->last_awake_jiffies),
0611                  rtlpriv->psc.state_inap);
0612             ppsc->last_sleep_jiffies = jiffies;
0613             _rtl92se_phy_set_rf_sleep(hw);
0614             break;
0615     default:
0616         pr_err("switch case %#x not processed\n",
0617                rfpwr_state);
0618         bresult = false;
0619         break;
0620     }
0621 
0622     if (bresult)
0623         ppsc->rfpwr_state = rfpwr_state;
0624 
0625     return bresult;
0626 }
0627 
0628 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw,
0629                          enum radio_path rfpath)
0630 {
0631     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0632     bool rtstatus = true;
0633     u32 tmpval = 0;
0634 
0635     /* If inferiority IC, we have to increase the PA bias current */
0636     if (rtlhal->ic_class != IC_INFERIORITY_A) {
0637         tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf);
0638         rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1);
0639     }
0640 
0641     return rtstatus;
0642 }
0643 
0644 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
0645         u32 reg_addr, u32 bitmask, u32 data)
0646 {
0647     struct rtl_priv *rtlpriv = rtl_priv(hw);
0648     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0649     int index;
0650 
0651     if (reg_addr == RTXAGC_RATE18_06)
0652         index = 0;
0653     else if (reg_addr == RTXAGC_RATE54_24)
0654         index = 1;
0655     else if (reg_addr == RTXAGC_CCK_MCS32)
0656         index = 6;
0657     else if (reg_addr == RTXAGC_MCS03_MCS00)
0658         index = 2;
0659     else if (reg_addr == RTXAGC_MCS07_MCS04)
0660         index = 3;
0661     else if (reg_addr == RTXAGC_MCS11_MCS08)
0662         index = 4;
0663     else if (reg_addr == RTXAGC_MCS15_MCS12)
0664         index = 5;
0665     else
0666         return;
0667 
0668     rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
0669     if (index == 5)
0670         rtlphy->pwrgroup_cnt++;
0671 }
0672 
0673 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw)
0674 {
0675     struct rtl_priv *rtlpriv = rtl_priv(hw);
0676     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0677 
0678     /*RF Interface Sowrtware Control */
0679     rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
0680     rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
0681     rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
0682     rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
0683 
0684     /* RF Interface Readback Value */
0685     rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
0686     rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
0687     rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
0688     rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
0689 
0690     /* RF Interface Output (and Enable) */
0691     rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
0692     rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
0693     rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;
0694     rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE;
0695 
0696     /* RF Interface (Output and)  Enable */
0697     rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
0698     rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
0699     rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;
0700     rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE;
0701 
0702     /* Addr of LSSI. Wirte RF register by driver */
0703     rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
0704                          RFPGA0_XA_LSSIPARAMETER;
0705     rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
0706                          RFPGA0_XB_LSSIPARAMETER;
0707     rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =
0708                          RFPGA0_XC_LSSIPARAMETER;
0709     rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset =
0710                          RFPGA0_XD_LSSIPARAMETER;
0711 
0712     /* RF parameter */
0713     rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
0714     rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
0715     rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
0716     rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
0717 
0718     /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
0719     rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0720     rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0721     rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0722     rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0723 
0724     /* Tranceiver A~D HSSI Parameter-1 */
0725     rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
0726     rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
0727     rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;
0728     rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1;
0729 
0730     /* Tranceiver A~D HSSI Parameter-2 */
0731     rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
0732     rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
0733     rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;
0734     rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2;
0735 
0736     /* RF switch Control */
0737     rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
0738     rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
0739     rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
0740     rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
0741 
0742     /* AGC control 1  */
0743     rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
0744     rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
0745     rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
0746     rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
0747 
0748     /* AGC control 2  */
0749     rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
0750     rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
0751     rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
0752     rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
0753 
0754     /* RX AFE control 1  */
0755     rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
0756     rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
0757     rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
0758     rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
0759 
0760     /* RX AFE control 1   */
0761     rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
0762     rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
0763     rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
0764     rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
0765 
0766     /* Tx AFE control 1  */
0767     rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
0768     rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
0769     rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
0770     rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
0771 
0772     /* Tx AFE control 2  */
0773     rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
0774     rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
0775     rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
0776     rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
0777 
0778     /* Tranceiver LSSI Readback */
0779     rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
0780     rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
0781     rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
0782     rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
0783 
0784     /* Tranceiver LSSI Readback PI mode  */
0785     rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
0786     rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
0787 }
0788 
0789 
0790 static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
0791 {
0792     int i;
0793     u32 *phy_reg_table;
0794     u32 *agc_table;
0795     u16 phy_reg_len, agc_len;
0796 
0797     agc_len = AGCTAB_ARRAYLENGTH;
0798     agc_table = rtl8192seagctab_array;
0799     /* Default RF_type: 2T2R */
0800     phy_reg_len = PHY_REG_2T2RARRAYLENGTH;
0801     phy_reg_table = rtl8192sephy_reg_2t2rarray;
0802 
0803     if (configtype == BASEBAND_CONFIG_PHY_REG) {
0804         for (i = 0; i < phy_reg_len; i = i + 2) {
0805             rtl_addr_delay(phy_reg_table[i]);
0806 
0807             /* Add delay for ECS T20 & LG malow platform, */
0808             udelay(1);
0809 
0810             rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD,
0811                     phy_reg_table[i + 1]);
0812         }
0813     } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
0814         for (i = 0; i < agc_len; i = i + 2) {
0815             rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD,
0816                     agc_table[i + 1]);
0817 
0818             /* Add delay for ECS T20 & LG malow platform */
0819             udelay(1);
0820         }
0821     }
0822 
0823     return true;
0824 }
0825 
0826 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
0827                       u8 configtype)
0828 {
0829     struct rtl_priv *rtlpriv = rtl_priv(hw);
0830     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0831     u32 *phy_regarray2xtxr_table;
0832     u16 phy_regarray2xtxr_len;
0833     int i;
0834 
0835     if (rtlphy->rf_type == RF_1T1R) {
0836         phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray;
0837         phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH;
0838     } else if (rtlphy->rf_type == RF_1T2R) {
0839         phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray;
0840         phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH;
0841     } else {
0842         return false;
0843     }
0844 
0845     if (configtype == BASEBAND_CONFIG_PHY_REG) {
0846         for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
0847             rtl_addr_delay(phy_regarray2xtxr_table[i]);
0848 
0849             rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
0850                 phy_regarray2xtxr_table[i + 1],
0851                 phy_regarray2xtxr_table[i + 2]);
0852         }
0853     }
0854 
0855     return true;
0856 }
0857 
0858 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
0859                       u8 configtype)
0860 {
0861     int i;
0862     u32 *phy_table_pg;
0863     u16 phy_pg_len;
0864 
0865     phy_pg_len = PHY_REG_ARRAY_PGLENGTH;
0866     phy_table_pg = rtl8192sephy_reg_array_pg;
0867 
0868     if (configtype == BASEBAND_CONFIG_PHY_REG) {
0869         for (i = 0; i < phy_pg_len; i = i + 3) {
0870             rtl_addr_delay(phy_table_pg[i]);
0871 
0872             _rtl92s_store_pwrindex_diffrate_offset(hw,
0873                     phy_table_pg[i],
0874                     phy_table_pg[i + 1],
0875                     phy_table_pg[i + 2]);
0876             rtl92s_phy_set_bb_reg(hw, phy_table_pg[i],
0877                     phy_table_pg[i + 1],
0878                     phy_table_pg[i + 2]);
0879         }
0880     }
0881 
0882     return true;
0883 }
0884 
0885 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw)
0886 {
0887     struct rtl_priv *rtlpriv = rtl_priv(hw);
0888     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0889     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0890     bool rtstatus = true;
0891 
0892     /* 1. Read PHY_REG.TXT BB INIT!! */
0893     /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */
0894     if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R ||
0895         rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) {
0896         rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG);
0897 
0898         if (rtlphy->rf_type != RF_2T2R &&
0899             rtlphy->rf_type != RF_2T2R_GREEN)
0900             /* so we should reconfig BB reg with the right
0901              * PHY parameters. */
0902             rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw,
0903                         BASEBAND_CONFIG_PHY_REG);
0904     } else {
0905         rtstatus = false;
0906     }
0907 
0908     if (!rtstatus) {
0909         pr_err("Write BB Reg Fail!!\n");
0910         goto phy_bb8190_config_parafile_fail;
0911     }
0912 
0913     /* 2. If EEPROM or EFUSE autoload OK, We must config by
0914      *    PHY_REG_PG.txt */
0915     if (rtlefuse->autoload_failflag == false) {
0916         rtlphy->pwrgroup_cnt = 0;
0917 
0918         rtstatus = _rtl92s_phy_config_bb_with_pg(hw,
0919                          BASEBAND_CONFIG_PHY_REG);
0920     }
0921     if (!rtstatus) {
0922         pr_err("_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
0923         goto phy_bb8190_config_parafile_fail;
0924     }
0925 
0926     /* 3. BB AGC table Initialization */
0927     rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
0928 
0929     if (!rtstatus) {
0930         pr_err("%s(): AGC Table Fail\n", __func__);
0931         goto phy_bb8190_config_parafile_fail;
0932     }
0933 
0934     /* Check if the CCK HighPower is turned ON. */
0935     /* This is used to calculate PWDB. */
0936     rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
0937             RFPGA0_XA_HSSIPARAMETER2, 0x200));
0938 
0939 phy_bb8190_config_parafile_fail:
0940     return rtstatus;
0941 }
0942 
0943 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
0944 {
0945     struct rtl_priv *rtlpriv = rtl_priv(hw);
0946     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0947     int i;
0948     bool rtstatus = true;
0949     u32 *radio_a_table;
0950     u32 *radio_b_table;
0951     u16 radio_a_tblen, radio_b_tblen;
0952 
0953     radio_a_tblen = RADIOA_1T_ARRAYLENGTH;
0954     radio_a_table = rtl8192seradioa_1t_array;
0955 
0956     /* Using Green mode array table for RF_2T2R_GREEN */
0957     if (rtlphy->rf_type == RF_2T2R_GREEN) {
0958         radio_b_table = rtl8192seradiob_gm_array;
0959         radio_b_tblen = RADIOB_GM_ARRAYLENGTH;
0960     } else {
0961         radio_b_table = rtl8192seradiob_array;
0962         radio_b_tblen = RADIOB_ARRAYLENGTH;
0963     }
0964 
0965     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
0966     rtstatus = true;
0967 
0968     switch (rfpath) {
0969     case RF90_PATH_A:
0970         for (i = 0; i < radio_a_tblen; i = i + 2) {
0971             rtl_rfreg_delay(hw, rfpath, radio_a_table[i],
0972                     MASK20BITS, radio_a_table[i + 1]);
0973 
0974         }
0975 
0976         /* PA Bias current for inferiority IC */
0977         _rtl92s_phy_config_rfpa_bias_current(hw, rfpath);
0978         break;
0979     case RF90_PATH_B:
0980         for (i = 0; i < radio_b_tblen; i = i + 2) {
0981             rtl_rfreg_delay(hw, rfpath, radio_b_table[i],
0982                     MASK20BITS, radio_b_table[i + 1]);
0983         }
0984         break;
0985     case RF90_PATH_C:
0986         ;
0987         break;
0988     case RF90_PATH_D:
0989         ;
0990         break;
0991     default:
0992         break;
0993     }
0994 
0995     return rtstatus;
0996 }
0997 
0998 
0999 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw)
1000 {
1001     struct rtl_priv *rtlpriv = rtl_priv(hw);
1002     u32 i;
1003     u32 arraylength;
1004     u32 *ptrarray;
1005 
1006     arraylength = MAC_2T_ARRAYLENGTH;
1007     ptrarray = rtl8192semac_2t_array;
1008 
1009     for (i = 0; i < arraylength; i = i + 2)
1010         rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
1011 
1012     return true;
1013 }
1014 
1015 
1016 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw)
1017 {
1018     struct rtl_priv *rtlpriv = rtl_priv(hw);
1019     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1020     bool rtstatus;
1021     u8 pathmap, index, rf_num = 0;
1022     u8 path1, path2;
1023 
1024     _rtl92s_phy_init_register_definition(hw);
1025 
1026     /* Config BB and AGC */
1027     rtstatus = _rtl92s_phy_bb_config_parafile(hw);
1028 
1029 
1030     /* Check BB/RF confiuration setting. */
1031     /* We only need to configure RF which is turned on. */
1032     path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf));
1033     mdelay(10);
1034     path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
1035     pathmap = path1 | path2;
1036 
1037     rtlphy->rf_pathmap = pathmap;
1038     for (index = 0; index < 4; index++) {
1039         if ((pathmap >> index) & 0x1)
1040             rf_num++;
1041     }
1042 
1043     if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) ||
1044         (rtlphy->rf_type == RF_1T2R && rf_num != 2) ||
1045         (rtlphy->rf_type == RF_2T2R && rf_num != 2) ||
1046         (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) {
1047         pr_err("RF_Type(%x) does not match RF_Num(%x)!!\n",
1048                rtlphy->rf_type, rf_num);
1049         pr_err("path1 0x%x, path2 0x%x, pathmap 0x%x\n",
1050                path1, path2, pathmap);
1051     }
1052 
1053     return rtstatus;
1054 }
1055 
1056 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw)
1057 {
1058     struct rtl_priv *rtlpriv = rtl_priv(hw);
1059     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1060 
1061     /* Initialize general global value */
1062     if (rtlphy->rf_type == RF_1T1R)
1063         rtlphy->num_total_rfpath = 1;
1064     else
1065         rtlphy->num_total_rfpath = 2;
1066 
1067     /* Config BB and RF */
1068     return rtl92s_phy_rf6052_config(hw);
1069 }
1070 
1071 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1072 {
1073     struct rtl_priv *rtlpriv = rtl_priv(hw);
1074     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1075 
1076     /* read rx initial gain */
1077     rtlphy->default_initialgain[0] = rtl_get_bbreg(hw,
1078             ROFDM0_XAAGCCORE1, MASKBYTE0);
1079     rtlphy->default_initialgain[1] = rtl_get_bbreg(hw,
1080             ROFDM0_XBAGCCORE1, MASKBYTE0);
1081     rtlphy->default_initialgain[2] = rtl_get_bbreg(hw,
1082             ROFDM0_XCAGCCORE1, MASKBYTE0);
1083     rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
1084             ROFDM0_XDAGCCORE1, MASKBYTE0);
1085     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1086         "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1087         rtlphy->default_initialgain[0],
1088         rtlphy->default_initialgain[1],
1089         rtlphy->default_initialgain[2],
1090         rtlphy->default_initialgain[3]);
1091 
1092     /* read framesync */
1093     rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
1094     rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1095                           MASKDWORD);
1096     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1097         "Default framesync (0x%x) = 0x%x\n",
1098         ROFDM0_RXDETECTOR3, rtlphy->framesync);
1099 
1100 }
1101 
1102 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1103                       u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1104 {
1105     struct rtl_priv *rtlpriv = rtl_priv(hw);
1106     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1107     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1108     u8 index = (channel - 1);
1109 
1110     /* 1. CCK */
1111     /* RF-A */
1112     cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index];
1113     /* RF-B */
1114     cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index];
1115 
1116     /* 2. OFDM for 1T or 2T */
1117     if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1118         /* Read HT 40 OFDM TX power */
1119         ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1120         ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
1121     } else if (rtlphy->rf_type == RF_2T2R) {
1122         /* Read HT 40 OFDM TX power */
1123         ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1124         ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1125     } else {
1126         ofdmpowerlevel[0] = 0;
1127         ofdmpowerlevel[1] = 0;
1128     }
1129 }
1130 
1131 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw,
1132         u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1133 {
1134     struct rtl_priv *rtlpriv = rtl_priv(hw);
1135     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1136 
1137     rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1138     rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1139 }
1140 
1141 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel)
1142 {
1143     struct rtl_priv *rtlpriv = rtl_priv(hw);
1144     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1145     /* [0]:RF-A, [1]:RF-B */
1146     u8 cckpowerlevel[2], ofdmpowerlevel[2];
1147 
1148     if (!rtlefuse->txpwr_fromeprom)
1149         return;
1150 
1151     /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1152      * but the RF-B Tx Power must be calculated by the antenna diff.
1153      * So we have to rewrite Antenna gain offset register here.
1154      * Please refer to BB register 0x80c
1155      * 1. For CCK.
1156      * 2. For OFDM 1T or 2T */
1157     _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
1158             &ofdmpowerlevel[0]);
1159 
1160     rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1161         "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1162         channel, cckpowerlevel[0], cckpowerlevel[1],
1163         ofdmpowerlevel[0], ofdmpowerlevel[1]);
1164 
1165     _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1166             &ofdmpowerlevel[0]);
1167 
1168     rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
1169     rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerlevel[0], channel);
1170 
1171 }
1172 
1173 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw)
1174 {
1175     struct rtl_priv *rtlpriv = rtl_priv(hw);
1176     u16 pollingcnt = 10000;
1177     u32 tmpvalue;
1178 
1179     /* Make sure that CMD IO has be accepted by FW. */
1180     do {
1181         udelay(10);
1182 
1183         tmpvalue = rtl_read_dword(rtlpriv, WFM5);
1184         if (tmpvalue == 0)
1185             break;
1186     } while (--pollingcnt);
1187 
1188     if (pollingcnt == 0)
1189         pr_err("Set FW Cmd fail!!\n");
1190 }
1191 
1192 
1193 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1194 {
1195     struct rtl_priv *rtlpriv = rtl_priv(hw);
1196     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1197     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1198     u32 input, current_aid = 0;
1199 
1200     if (is_hal_stop(rtlhal))
1201         return;
1202 
1203     if (hal_get_firmwareversion(rtlpriv) < 0x34)
1204         goto skip;
1205     /* We re-map RA related CMD IO to combinational ones */
1206     /* if FW version is v.52 or later. */
1207     switch (rtlhal->current_fwcmd_io) {
1208     case FW_CMD_RA_REFRESH_N:
1209         rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB;
1210         break;
1211     case FW_CMD_RA_REFRESH_BG:
1212         rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB;
1213         break;
1214     default:
1215         break;
1216     }
1217 
1218 skip:
1219     switch (rtlhal->current_fwcmd_io) {
1220     case FW_CMD_RA_RESET:
1221         rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
1222         rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1223         rtl92s_phy_chk_fwcmd_iodone(hw);
1224         break;
1225     case FW_CMD_RA_ACTIVE:
1226         rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
1227         rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1228         rtl92s_phy_chk_fwcmd_iodone(hw);
1229         break;
1230     case FW_CMD_RA_REFRESH_N:
1231         rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
1232         input = FW_RA_REFRESH;
1233         rtl_write_dword(rtlpriv, WFM5, input);
1234         rtl92s_phy_chk_fwcmd_iodone(hw);
1235         rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK);
1236         rtl92s_phy_chk_fwcmd_iodone(hw);
1237         break;
1238     case FW_CMD_RA_REFRESH_BG:
1239         rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG,
1240             "FW_CMD_RA_REFRESH_BG\n");
1241         rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1242         rtl92s_phy_chk_fwcmd_iodone(hw);
1243         rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
1244         rtl92s_phy_chk_fwcmd_iodone(hw);
1245         break;
1246     case FW_CMD_RA_REFRESH_N_COMB:
1247         rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG,
1248             "FW_CMD_RA_REFRESH_N_COMB\n");
1249         input = FW_RA_IOT_N_COMB;
1250         rtl_write_dword(rtlpriv, WFM5, input);
1251         rtl92s_phy_chk_fwcmd_iodone(hw);
1252         break;
1253     case FW_CMD_RA_REFRESH_BG_COMB:
1254         rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG,
1255             "FW_CMD_RA_REFRESH_BG_COMB\n");
1256         input = FW_RA_IOT_BG_COMB;
1257         rtl_write_dword(rtlpriv, WFM5, input);
1258         rtl92s_phy_chk_fwcmd_iodone(hw);
1259         break;
1260     case FW_CMD_IQK_ENABLE:
1261         rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
1262         rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
1263         rtl92s_phy_chk_fwcmd_iodone(hw);
1264         break;
1265     case FW_CMD_PAUSE_DM_BY_SCAN:
1266         /* Lower initial gain */
1267         rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1268         rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1269         /* CCA threshold */
1270         rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1271         break;
1272     case FW_CMD_RESUME_DM_BY_SCAN:
1273         /* CCA threshold */
1274         rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1275         rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1276         break;
1277     case FW_CMD_HIGH_PWR_DISABLE:
1278         if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE)
1279             break;
1280 
1281         /* Lower initial gain */
1282         rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1283         rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1284         /* CCA threshold */
1285         rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1286         break;
1287     case FW_CMD_HIGH_PWR_ENABLE:
1288         if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1289             rtlpriv->dm.dynamic_txpower_enable)
1290             break;
1291 
1292         /* CCA threshold */
1293         rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1294         break;
1295     case FW_CMD_LPS_ENTER:
1296         rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
1297         current_aid = rtlpriv->mac80211.assoc_id;
1298         rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
1299                 ((current_aid | 0xc000) << 8)));
1300         rtl92s_phy_chk_fwcmd_iodone(hw);
1301         /* FW set TXOP disable here, so disable EDCA
1302          * turbo mode until driver leave LPS */
1303         break;
1304     case FW_CMD_LPS_LEAVE:
1305         rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
1306         rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
1307         rtl92s_phy_chk_fwcmd_iodone(hw);
1308         break;
1309     case FW_CMD_ADD_A2_ENTRY:
1310         rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
1311         rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
1312         rtl92s_phy_chk_fwcmd_iodone(hw);
1313         break;
1314     case FW_CMD_CTRL_DM_BY_DRIVER:
1315         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1316             "FW_CMD_CTRL_DM_BY_DRIVER\n");
1317         rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
1318         rtl92s_phy_chk_fwcmd_iodone(hw);
1319         break;
1320 
1321     default:
1322         break;
1323     }
1324 
1325     rtl92s_phy_chk_fwcmd_iodone(hw);
1326 
1327     /* Clear FW CMD operation flag. */
1328     rtlhal->set_fwcmd_inprogress = false;
1329 }
1330 
1331 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1332 {
1333     struct rtl_priv *rtlpriv = rtl_priv(hw);
1334     struct dig_t *digtable = &rtlpriv->dm_digtable;
1335     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1336     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1337     u32 fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv);
1338     u16 fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
1339     bool postprocessing = false;
1340 
1341     rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1342         "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1343         fw_cmdio, rtlhal->set_fwcmd_inprogress);
1344 
1345     do {
1346         /* We re-map to combined FW CMD ones if firmware version */
1347         /* is v.53 or later. */
1348         if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1349             switch (fw_cmdio) {
1350             case FW_CMD_RA_REFRESH_N:
1351                 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB;
1352                 break;
1353             case FW_CMD_RA_REFRESH_BG:
1354                 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB;
1355                 break;
1356             default:
1357                 break;
1358             }
1359         } else {
1360             if ((fw_cmdio == FW_CMD_IQK_ENABLE) ||
1361                 (fw_cmdio == FW_CMD_RA_REFRESH_N) ||
1362                 (fw_cmdio == FW_CMD_RA_REFRESH_BG)) {
1363                 postprocessing = true;
1364                 break;
1365             }
1366         }
1367 
1368         /* If firmware version is v.62 or later,
1369          * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
1370         if (hal_get_firmwareversion(rtlpriv) >= 0x3E) {
1371             if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER)
1372                 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
1373         }
1374 
1375 
1376         /* We shall revise all FW Cmd IO into Reg0x364
1377          * DM map table in the future. */
1378         switch (fw_cmdio) {
1379         case FW_CMD_RA_INIT:
1380             rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
1381             fw_cmdmap |= FW_RA_INIT_CTL;
1382             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1383             /* Clear control flag to sync with FW. */
1384             FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL);
1385             break;
1386         case FW_CMD_DIG_DISABLE:
1387             rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1388                 "Set DIG disable!!\n");
1389             fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1390             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1391             break;
1392         case FW_CMD_DIG_ENABLE:
1393         case FW_CMD_DIG_RESUME:
1394             if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1395                 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1396                     "Set DIG enable or resume!!\n");
1397                 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
1398                 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1399             }
1400             break;
1401         case FW_CMD_DIG_HALT:
1402             rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1403                 "Set DIG halt!!\n");
1404             fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
1405             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1406             break;
1407         case FW_CMD_TXPWR_TRACK_THERMAL: {
1408             u8  thermalval = 0;
1409             fw_cmdmap |= FW_PWR_TRK_CTL;
1410 
1411             /* Clear FW parameter in terms of thermal parts. */
1412             fw_param &= FW_PWR_TRK_PARAM_CLR;
1413 
1414             thermalval = rtlpriv->dm.thermalvalue;
1415             fw_param |= ((thermalval << 24) |
1416                      (rtlefuse->thermalmeter[0] << 16));
1417 
1418             rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1419                 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1420                 fw_cmdmap, fw_param);
1421 
1422             FW_CMD_PARA_SET(rtlpriv, fw_param);
1423             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1424 
1425             /* Clear control flag to sync with FW. */
1426             FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL);
1427             }
1428             break;
1429         /* The following FW CMDs are only compatible to
1430          * v.53 or later. */
1431         case FW_CMD_RA_REFRESH_N_COMB:
1432             fw_cmdmap |= FW_RA_N_CTL;
1433 
1434             /* Clear RA BG mode control. */
1435             fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL);
1436 
1437             /* Clear FW parameter in terms of RA parts. */
1438             fw_param &= FW_RA_PARAM_CLR;
1439 
1440             rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1441                 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1442                 fw_cmdmap, fw_param);
1443 
1444             FW_CMD_PARA_SET(rtlpriv, fw_param);
1445             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1446 
1447             /* Clear control flag to sync with FW. */
1448             FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL);
1449             break;
1450         case FW_CMD_RA_REFRESH_BG_COMB:
1451             fw_cmdmap |= FW_RA_BG_CTL;
1452 
1453             /* Clear RA n-mode control. */
1454             fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL);
1455             /* Clear FW parameter in terms of RA parts. */
1456             fw_param &= FW_RA_PARAM_CLR;
1457 
1458             FW_CMD_PARA_SET(rtlpriv, fw_param);
1459             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1460 
1461             /* Clear control flag to sync with FW. */
1462             FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL);
1463             break;
1464         case FW_CMD_IQK_ENABLE:
1465             fw_cmdmap |= FW_IQK_CTL;
1466             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1467             /* Clear control flag to sync with FW. */
1468             FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL);
1469             break;
1470         /* The following FW CMD is compatible to v.62 or later.  */
1471         case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
1472             fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL;
1473             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1474             break;
1475         /*  The followed FW Cmds needs post-processing later. */
1476         case FW_CMD_RESUME_DM_BY_SCAN:
1477             fw_cmdmap |= (FW_DIG_ENABLE_CTL |
1478                       FW_HIGH_PWR_ENABLE_CTL |
1479                       FW_SS_CTL);
1480 
1481             if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE ||
1482                 !digtable->dig_enable_flag)
1483                 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1484 
1485             if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1486                 rtlpriv->dm.dynamic_txpower_enable)
1487                 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1488 
1489             if ((digtable->dig_ext_port_stage ==
1490                 DIG_EXT_PORT_STAGE_0) ||
1491                 (digtable->dig_ext_port_stage ==
1492                 DIG_EXT_PORT_STAGE_1))
1493                 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1494 
1495             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1496             postprocessing = true;
1497             break;
1498         case FW_CMD_PAUSE_DM_BY_SCAN:
1499             fw_cmdmap &= ~(FW_DIG_ENABLE_CTL |
1500                        FW_HIGH_PWR_ENABLE_CTL |
1501                        FW_SS_CTL);
1502             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1503             postprocessing = true;
1504             break;
1505         case FW_CMD_HIGH_PWR_DISABLE:
1506             fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1507             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1508             postprocessing = true;
1509             break;
1510         case FW_CMD_HIGH_PWR_ENABLE:
1511             if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
1512                 !rtlpriv->dm.dynamic_txpower_enable) {
1513                 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL |
1514                           FW_SS_CTL);
1515                 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1516                 postprocessing = true;
1517             }
1518             break;
1519         case FW_CMD_DIG_MODE_FA:
1520             fw_cmdmap |= FW_FA_CTL;
1521             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1522             break;
1523         case FW_CMD_DIG_MODE_SS:
1524             fw_cmdmap &= ~FW_FA_CTL;
1525             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1526             break;
1527         case FW_CMD_PAPE_CONTROL:
1528             rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1529                 "[FW CMD] Set PAPE Control\n");
1530             fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
1531 
1532             FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1533             break;
1534         default:
1535             /* Pass to original FW CMD processing callback
1536              * routine. */
1537             postprocessing = true;
1538             break;
1539         }
1540     } while (false);
1541 
1542     /* We shall post processing these FW CMD if
1543      * variable postprocessing is set.
1544      */
1545     if (postprocessing && !rtlhal->set_fwcmd_inprogress) {
1546         rtlhal->set_fwcmd_inprogress = true;
1547         /* Update current FW Cmd for callback use. */
1548         rtlhal->current_fwcmd_io = fw_cmdio;
1549     } else {
1550         return false;
1551     }
1552 
1553     _rtl92s_phy_set_fwcmd_io(hw);
1554     return true;
1555 }
1556 
1557 static  void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw)
1558 {
1559     struct rtl_priv *rtlpriv = rtl_priv(hw);
1560     u32 delay = 100;
1561     u8  regu1;
1562 
1563     regu1 = rtl_read_byte(rtlpriv, 0x554);
1564     while ((regu1 & BIT(5)) && (delay > 0)) {
1565         regu1 = rtl_read_byte(rtlpriv, 0x554);
1566         delay--;
1567         /* We delay only 50us to prevent
1568          * being scheduled out. */
1569         udelay(50);
1570     }
1571 }
1572 
1573 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw)
1574 {
1575     struct rtl_priv *rtlpriv = rtl_priv(hw);
1576     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1577 
1578     /* The way to be capable to switch clock request
1579      * when the PG setting does not support clock request.
1580      * This is the backdoor solution to switch clock
1581      * request before ASPM or D3. */
1582     rtl_write_dword(rtlpriv, 0x540, 0x73c11);
1583     rtl_write_dword(rtlpriv, 0x548, 0x2407c);
1584 
1585     /* Switch EPHY parameter!!!! */
1586     rtl_write_word(rtlpriv, 0x550, 0x1000);
1587     rtl_write_byte(rtlpriv, 0x554, 0x20);
1588     _rtl92s_phy_check_ephy_switchready(hw);
1589 
1590     rtl_write_word(rtlpriv, 0x550, 0xa0eb);
1591     rtl_write_byte(rtlpriv, 0x554, 0x3e);
1592     _rtl92s_phy_check_ephy_switchready(hw);
1593 
1594     rtl_write_word(rtlpriv, 0x550, 0xff80);
1595     rtl_write_byte(rtlpriv, 0x554, 0x39);
1596     _rtl92s_phy_check_ephy_switchready(hw);
1597 
1598     /* Delay L1 enter time */
1599     if (ppsc->support_aspm && !ppsc->support_backdoor)
1600         rtl_write_byte(rtlpriv, 0x560, 0x40);
1601     else
1602         rtl_write_byte(rtlpriv, 0x560, 0x00);
1603 
1604 }
1605 
1606 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval)
1607 {
1608     struct rtl_priv *rtlpriv = rtl_priv(hw);
1609     u32 new_bcn_num = 0;
1610 
1611     if (hal_get_firmwareversion(rtlpriv) >= 0x33) {
1612         /* Fw v.51 and later. */
1613         rtl_write_dword(rtlpriv, WFM5, 0xF1000000 |
1614                 (beaconinterval << 8));
1615     } else {
1616         new_bcn_num = beaconinterval * 32 - 64;
1617         rtl_write_dword(rtlpriv, WFM3 + 4, new_bcn_num);
1618         rtl_write_dword(rtlpriv, WFM3, 0xB026007C);
1619     }
1620 }
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