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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003 
0004 #ifndef __REALTEK_FIRMWARE92S_H__
0005 #define __REALTEK_FIRMWARE92S_H__
0006 
0007 #define RTL8190_MAX_FIRMWARE_CODE_SIZE      64000
0008 #define RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE  90000
0009 #define RTL8190_CPU_START_OFFSET        0x80
0010 /* Firmware Local buffer size. 64k */
0011 #define MAX_FIRMWARE_CODE_SIZE          0xFF00
0012 
0013 #define RT_8192S_FIRMWARE_HDR_SIZE      80
0014 #define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE  32
0015 
0016 /* support till 64 bit bus width OS */
0017 #define MAX_DEV_ADDR_SIZE           8
0018 #define MAX_FIRMWARE_INFORMATION_SIZE       32
0019 #define MAX_802_11_HEADER_LENGTH        (40 + \
0020                         MAX_FIRMWARE_INFORMATION_SIZE)
0021 #define ENCRYPTION_MAX_OVERHEAD         128
0022 #define MAX_FRAGMENT_COUNT          8
0023 #define MAX_TRANSMIT_BUFFER_SIZE        (1600 + \
0024                         (MAX_802_11_HEADER_LENGTH + \
0025                         ENCRYPTION_MAX_OVERHEAD) *\
0026                         MAX_FRAGMENT_COUNT)
0027 
0028 #define H2C_TX_CMD_HDR_LEN          8
0029 
0030 /* The following DM control code are for Reg0x364, */
0031 #define FW_DIG_ENABLE_CTL           BIT(0)
0032 #define FW_HIGH_PWR_ENABLE_CTL          BIT(1)
0033 #define FW_SS_CTL               BIT(2)
0034 #define FW_RA_INIT_CTL              BIT(3)
0035 #define FW_RA_BG_CTL                BIT(4)
0036 #define FW_RA_N_CTL             BIT(5)
0037 #define FW_PWR_TRK_CTL              BIT(6)
0038 #define FW_IQK_CTL              BIT(7)
0039 #define FW_FA_CTL               BIT(8)
0040 #define FW_DRIVER_CTRL_DM_CTL           BIT(9)
0041 #define FW_PAPE_CTL_BY_SW_HW            BIT(10)
0042 #define FW_DISABLE_ALL_DM           0
0043 #define FW_PWR_TRK_PARAM_CLR            0x0000ffff
0044 #define FW_RA_PARAM_CLR             0xffff0000
0045 
0046 enum desc_packet_type {
0047     DESC_PACKET_TYPE_INIT = 0,
0048     DESC_PACKET_TYPE_NORMAL = 1,
0049 };
0050 
0051 /* 8-bytes alignment required */
0052 struct fw_priv {
0053     /* --- long word 0 ---- */
0054     /* 0x12: CE product, 0x92: IT product */
0055     u8 signature_0;
0056     /* 0x87: CE product, 0x81: IT product */
0057     u8 signature_1;
0058     /* 0x81: PCI-AP, 01:PCIe, 02: 92S-U,
0059      * 0x82: USB-AP, 0x12: 72S-U, 03:SDIO */
0060     u8 hci_sel;
0061     /* the same value as reigster value  */
0062     u8 chip_version;
0063     /* customer  ID low byte */
0064     u8 customer_id_0;
0065     /* customer  ID high byte */
0066     u8 customer_id_1;
0067     /* 0x11:  1T1R, 0x12: 1T2R,
0068      * 0x92: 1T2R turbo, 0x22: 2T2R */
0069     u8 rf_config;
0070     /* 4: 4EP, 6: 6EP, 11: 11EP */
0071     u8 usb_ep_num;
0072 
0073     /* --- long word 1 ---- */
0074     /* regulatory class bit map 0 */
0075     u8 regulatory_class_0;
0076     /* regulatory class bit map 1 */
0077     u8 regulatory_class_1;
0078     /* regulatory class bit map 2 */
0079     u8 regulatory_class_2;
0080     /* regulatory class bit map 3 */
0081     u8 regulatory_class_3;
0082     /* 0:SWSI, 1:HWSI, 2:HWPI */
0083     u8 rfintfs;
0084     u8 def_nettype;
0085     u8 rsvd010;
0086     u8 rsvd011;
0087 
0088     /* --- long word 2 ---- */
0089     /* 0x00: normal, 0x03: MACLBK, 0x01: PHYLBK */
0090     u8 lbk_mode;
0091     /* 1: for MP use, 0: for normal
0092      * driver (to be discussed) */
0093     u8 mp_mode;
0094     u8 rsvd020;
0095     u8 rsvd021;
0096     u8 rsvd022;
0097     u8 rsvd023;
0098     u8 rsvd024;
0099     u8 rsvd025;
0100 
0101     /* --- long word 3 ---- */
0102     /* QoS enable */
0103     u8 qos_en;
0104     /* 40MHz BW enable */
0105     /* 4181 convert AMSDU to AMPDU, 0: disable */
0106     u8 bw_40mhz_en;
0107     u8 amsdu2ampdu_en;
0108     /* 11n AMPDU enable */
0109     u8 ampdu_en;
0110     /* FW offloads, 0: driver handles */
0111     u8 rate_control_offload;
0112     /* FW offloads, 0: driver handles */
0113     u8 aggregation_offload;
0114     u8 rsvd030;
0115     u8 rsvd031;
0116 
0117     /* --- long word 4 ---- */
0118     /* 1. FW offloads, 0: driver handles */
0119     u8 beacon_offload;
0120     /* 2. FW offloads, 0: driver handles */
0121     u8 mlme_offload;
0122     /* 3. FW offloads, 0: driver handles */
0123     u8 hwpc_offload;
0124     /* 4. FW offloads, 0: driver handles */
0125     u8 tcp_checksum_offload;
0126     /* 5. FW offloads, 0: driver handles */
0127     u8 tcp_offload;
0128     /* 6. FW offloads, 0: driver handles */
0129     u8 ps_control_offload;
0130     /* 7. FW offloads, 0: driver handles */
0131     u8 wwlan_offload;
0132     u8 rsvd040;
0133 
0134     /* --- long word 5 ---- */
0135     /* tcp tx packet length low byte */
0136     u8 tcp_tx_frame_len_L;
0137     /* tcp tx packet length high byte */
0138     u8 tcp_tx_frame_len_H;
0139     /* tcp rx packet length low byte */
0140     u8 tcp_rx_frame_len_L;
0141     /* tcp rx packet length high byte */
0142     u8 tcp_rx_frame_len_H;
0143     u8 rsvd050;
0144     u8 rsvd051;
0145     u8 rsvd052;
0146     u8 rsvd053;
0147 };
0148 
0149 /* 8-byte alinment required */
0150 struct fw_hdr {
0151 
0152     /* --- LONG WORD 0 ---- */
0153     u16 signature;
0154     /* 0x8000 ~ 0x8FFF for FPGA version,
0155      * 0x0000 ~ 0x7FFF for ASIC version, */
0156     u16 version;
0157     /* define the size of boot loader */
0158     u32 dmem_size;
0159 
0160 
0161     /* --- LONG WORD 1 ---- */
0162     /* define the size of FW in IMEM */
0163     u32 img_imem_size;
0164     /* define the size of FW in SRAM */
0165     u32 img_sram_size;
0166 
0167     /* --- LONG WORD 2 ---- */
0168     /* define the size of DMEM variable */
0169     u32 fw_priv_size;
0170     u32 rsvd0;
0171 
0172     /* --- LONG WORD 3 ---- */
0173     u32 rsvd1;
0174     u32 rsvd2;
0175 
0176     struct fw_priv fwpriv;
0177 
0178 } ;
0179 
0180 enum fw_status {
0181     FW_STATUS_INIT = 0,
0182     FW_STATUS_LOAD_IMEM = 1,
0183     FW_STATUS_LOAD_EMEM = 2,
0184     FW_STATUS_LOAD_DMEM = 3,
0185     FW_STATUS_READY = 4,
0186 };
0187 
0188 struct rt_firmware {
0189     struct fw_hdr *pfwheader;
0190     enum fw_status fwstatus;
0191     u16 firmwareversion;
0192     u8 fw_imem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
0193     u8 fw_emem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
0194     u32 fw_imem_len;
0195     u32 fw_emem_len;
0196     u8 sz_fw_tmpbuffer[RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE];
0197     u32 sz_fw_tmpbufferlen;
0198     u16 cmdpacket_fragthresold;
0199 };
0200 
0201 struct h2c_set_pwrmode_parm {
0202     u8 mode;
0203     u8 flag_low_traffic_en;
0204     u8 flag_lpnav_en;
0205     u8 flag_rf_low_snr_en;
0206     /* 1: dps, 0: 32k */
0207     u8 flag_dps_en;
0208     u8 bcn_rx_en;
0209     u8 bcn_pass_cnt;
0210     /* beacon TO (ms). ¡§=0¡¨ no limit. */
0211     u8 bcn_to;
0212     u16 bcn_itv;
0213     /* only for VOIP mode. */
0214     u8 app_itv;
0215     u8 awake_bcn_itvl;
0216     u8 smart_ps;
0217     /* unit: 100 ms */
0218     u8 bcn_pass_period;
0219 };
0220 
0221 struct h2c_joinbss_rpt_parm {
0222     u8 opmode;
0223     u8 ps_qos_info;
0224     u8 bssid[6];
0225     u16 bcnitv;
0226     u16 aid;
0227 } ;
0228 
0229 struct h2c_wpa_ptk {
0230     /* EAPOL-Key Key Confirmation Key (KCK) */
0231     u8 kck[16];
0232     /* EAPOL-Key Key Encryption Key (KEK) */
0233     u8 kek[16];
0234     /* Temporal Key 1 (TK1) */
0235     u8 tk1[16];
0236     union {
0237         /* Temporal Key 2 (TK2) */
0238         u8 tk2[16];
0239         struct {
0240             u8 tx_mic_key[8];
0241             u8 rx_mic_key[8];
0242         } athu;
0243     } u;
0244 };
0245 
0246 struct h2c_wpa_two_way_parm {
0247     /* algorithm TKIP or AES */
0248     u8 pairwise_en_alg;
0249     u8 group_en_alg;
0250     struct h2c_wpa_ptk wpa_ptk_value;
0251 } ;
0252 
0253 enum h2c_cmd {
0254     FW_H2C_SETPWRMODE = 0,
0255     FW_H2C_JOINBSSRPT = 1,
0256     FW_H2C_WOWLAN_UPDATE_GTK = 2,
0257     FW_H2C_WOWLAN_UPDATE_IV = 3,
0258     FW_H2C_WOWLAN_OFFLOAD = 4,
0259 };
0260 
0261 enum fw_h2c_cmd {
0262     H2C_READ_MACREG_CMD,                /*0*/
0263     H2C_WRITE_MACREG_CMD,
0264     H2C_READBB_CMD,
0265     H2C_WRITEBB_CMD,
0266     H2C_READRF_CMD,
0267     H2C_WRITERF_CMD,                /*5*/
0268     H2C_READ_EEPROM_CMD,
0269     H2C_WRITE_EEPROM_CMD,
0270     H2C_READ_EFUSE_CMD,
0271     H2C_WRITE_EFUSE_CMD,
0272     H2C_READ_CAM_CMD,               /*10*/
0273     H2C_WRITE_CAM_CMD,
0274     H2C_SETBCNITV_CMD,
0275     H2C_SETMBIDCFG_CMD,
0276     H2C_JOINBSS_CMD,
0277     H2C_DISCONNECT_CMD,             /*15*/
0278     H2C_CREATEBSS_CMD,
0279     H2C_SETOPMODE_CMD,
0280     H2C_SITESURVEY_CMD,
0281     H2C_SETAUTH_CMD,
0282     H2C_SETKEY_CMD,                 /*20*/
0283     H2C_SETSTAKEY_CMD,
0284     H2C_SETASSOCSTA_CMD,
0285     H2C_DELASSOCSTA_CMD,
0286     H2C_SETSTAPWRSTATE_CMD,
0287     H2C_SETBASICRATE_CMD,               /*25*/
0288     H2C_GETBASICRATE_CMD,
0289     H2C_SETDATARATE_CMD,
0290     H2C_GETDATARATE_CMD,
0291     H2C_SETPHYINFO_CMD,
0292     H2C_GETPHYINFO_CMD,             /*30*/
0293     H2C_SETPHY_CMD,
0294     H2C_GETPHY_CMD,
0295     H2C_READRSSI_CMD,
0296     H2C_READGAIN_CMD,
0297     H2C_SETATIM_CMD,                /*35*/
0298     H2C_SETPWRMODE_CMD,
0299     H2C_JOINBSSRPT_CMD,
0300     H2C_SETRATABLE_CMD,
0301     H2C_GETRATABLE_CMD,
0302     H2C_GETCCXREPORT_CMD,               /*40*/
0303     H2C_GETDTMREPORT_CMD,
0304     H2C_GETTXRATESTATICS_CMD,
0305     H2C_SETUSBSUSPEND_CMD,
0306     H2C_SETH2CLBK_CMD,
0307     H2C_TMP1,                   /*45*/
0308     H2C_WOWLAN_UPDATE_GTK_CMD,
0309     H2C_WOWLAN_FW_OFFLOAD,
0310     H2C_TMP2,
0311     H2C_TMP3,
0312     H2C_WOWLAN_UPDATE_IV_CMD,           /*50*/
0313     H2C_TMP4,
0314 };
0315 
0316 /* The following macros are used for FW
0317  * CMD map and parameter updated. */
0318 #define FW_CMD_IO_CLR(rtlpriv, _bit)                \
0319     do {                            \
0320         udelay(1000);                   \
0321         rtlpriv->rtlhal.fwcmd_iomap &= (~_bit);     \
0322     } while (0)
0323 
0324 #define FW_CMD_IO_UPDATE(rtlpriv, _val)             \
0325     rtlpriv->rtlhal.fwcmd_iomap = _val;
0326 
0327 #define FW_CMD_IO_SET(rtlpriv, _val)                \
0328     do {                            \
0329         rtl_write_word(rtlpriv, LBUS_MON_ADDR, (u16)_val);  \
0330         FW_CMD_IO_UPDATE(rtlpriv, _val);        \
0331     } while (0)
0332 
0333 #define FW_CMD_PARA_SET(rtlpriv, _val)              \
0334     do {                            \
0335         rtl_write_dword(rtlpriv, LBUS_ADDR_MASK, _val); \
0336         rtlpriv->rtlhal.fwcmd_ioparam = _val;       \
0337     } while (0)
0338 
0339 #define FW_CMD_IO_QUERY(rtlpriv)                \
0340     (u16)(rtlpriv->rtlhal.fwcmd_iomap)
0341 #define FW_CMD_IO_PARA_QUERY(rtlpriv)               \
0342     ((u32)(rtlpriv->rtlhal.fwcmd_ioparam))
0343 
0344 int rtl92s_download_fw(struct ieee80211_hw *hw);
0345 void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
0346 void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
0347                       u8 mstatus, u8 ps_qosinfo);
0348 
0349 #endif
0350
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