rtlwifi/rtl8192se/dm.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003
0004 #ifndef __RTL_92S_DM_H__
0005 #define __RTL_92S_DM_H__
0006
0007 enum dm_dig_alg {
0008     DIG_ALGO_BY_FALSE_ALARM = 0,
0009     DIG_ALGO_BY_RSSI    = 1,
0010     DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM = 2,
0011     DIG_ALGO_BY_TOW_PORT = 3,
0012     DIG_ALGO_MAX
0013 };
0014
0015 enum dm_dig_two_port_alg {
0016     DIG_TWO_PORT_ALGO_RSSI = 0,
0017     DIG_TWO_PORT_ALGO_FALSE_ALARM = 1,
0018 };
0019
0020 enum dm_dig_dbg {
0021     DM_DBG_OFF = 0,
0022     DM_DBG_ON = 1,
0023     DM_DBG_MAX
0024 };
0025
0026 enum dm_dig_sta {
0027     DM_STA_DIG_OFF = 0,
0028     DM_STA_DIG_ON,
0029     DM_STA_DIG_MAX
0030 };
0031
0032 enum dm_ratr_sta {
0033     DM_RATR_STA_HIGH = 0,
0034     DM_RATR_STA_MIDDLEHIGH = 1,
0035     DM_RATR_STA_MIDDLE = 2,
0036     DM_RATR_STA_MIDDLELOW = 3,
0037     DM_RATR_STA_LOW = 4,
0038     DM_RATR_STA_ULTRALOW = 5,
0039     DM_RATR_STA_MAX
0040 };
0041
0042 #define DM_TYPE_BYFW            0
0043 #define DM_TYPE_BYDRIVER        1
0044
0045 #define TX_HIGH_PWR_LEVEL_NORMAL    0
0046 #define TX_HIGH_PWR_LEVEL_LEVEL1    1
0047 #define TX_HIGH_PWR_LEVEL_LEVEL2    2
0048
0049 #define HAL_DM_DIG_DISABLE      BIT(0)  /* Disable Dig */
0050 #define HAL_DM_HIPWR_DISABLE        BIT(1)  /* Disable High Power */
0051
0052 #define TX_HIGHPWR_LEVEL_NORMAL     0
0053 #define TX_HIGHPWR_LEVEL_NORMAL1    1
0054 #define TX_HIGHPWR_LEVEL_NORMAL2    2
0055
0056 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
0057 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
0058
0059 #define DM_DIG_HIGH_PWR_THRESH_HIGH 75
0060 #define DM_DIG_HIGH_PWR_THRESH_LOW  70
0061 #define DM_DIG_MIN_NETCORE      0x12
0062
0063 void rtl92s_dm_watchdog(struct ieee80211_hw *hw);
0064 void rtl92s_dm_init(struct ieee80211_hw *hw);
0065 void rtl92s_dm_init_edca_turbo(struct ieee80211_hw *hw);
0066
0067 #endif