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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2014  Realtek Corporation.*/
0003 
0004 #ifndef __RTL92E_TRX_H__
0005 #define __RTL92E_TRX_H__
0006 
0007 #define TX_DESC_SIZE                    64
0008 
0009 #define RX_DRV_INFO_SIZE_UNIT               8
0010 
0011 #define TX_DESC_NEXT_DESC_OFFSET            40
0012 #define USB_HWDESC_HEADER_LEN               40
0013 
0014 #define RX_DESC_SIZE                    24
0015 #define MAX_RECEIVE_BUFFER_SIZE             8192
0016 
0017 static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32 __val)
0018 {
0019     le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));
0020 }
0021 
0022 static inline void set_tx_desc_offset(__le32 *__pdesc, u32 __val)
0023 {
0024     le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));
0025 }
0026 
0027 static inline void set_tx_desc_bmc(__le32 *__pdesc, u32 __val)
0028 {
0029     le32p_replace_bits(__pdesc, __val, BIT(24));
0030 }
0031 
0032 static inline void set_tx_desc_htc(__le32 *__pdesc, u32 __val)
0033 {
0034     le32p_replace_bits(__pdesc, __val, BIT(25));
0035 }
0036 
0037 static inline void set_tx_desc_last_seg(__le32 *__pdesc, u32 __val)
0038 {
0039     le32p_replace_bits(__pdesc, __val, BIT(26));
0040 }
0041 
0042 static inline void set_tx_desc_first_seg(__le32 *__pdesc, u32 __val)
0043 {
0044     le32p_replace_bits(__pdesc, __val, BIT(27));
0045 }
0046 
0047 static inline void set_tx_desc_linip(__le32 *__pdesc, u32 __val)
0048 {
0049     le32p_replace_bits(__pdesc, __val, BIT(28));
0050 }
0051 
0052 static inline void set_tx_desc_own(__le32 *__pdesc, u32 __val)
0053 {
0054     le32p_replace_bits(__pdesc, __val, BIT(31));
0055 }
0056 
0057 static inline int get_tx_desc_own(__le32 *__pdesc)
0058 {
0059     return le32_get_bits(*(__pdesc), BIT(31));
0060 }
0061 
0062 static inline void set_tx_desc_macid(__le32 *__pdesc, u32 __val)
0063 {
0064     le32p_replace_bits((__pdesc + 1), __val, GENMASK(6, 0));
0065 }
0066 
0067 static inline void set_tx_desc_queue_sel(__le32 *__pdesc, u32 __val)
0068 {
0069     le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));
0070 }
0071 
0072 static inline void set_tx_desc_rate_id(__le32 *__pdesc, u32 __val)
0073 {
0074     le32p_replace_bits((__pdesc + 1), __val, GENMASK(20, 16));
0075 }
0076 
0077 static inline void set_tx_desc_sec_type(__le32 *__pdesc, u32 __val)
0078 {
0079     le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));
0080 }
0081 
0082 static inline void set_tx_desc_pkt_offset(__le32 *__pdesc, u32 __val)
0083 {
0084     le32p_replace_bits((__pdesc + 1), __val, GENMASK(28, 24));
0085 }
0086 
0087 static inline void set_tx_desc_agg_enable(__le32 *__pdesc, u32 __val)
0088 {
0089     le32p_replace_bits((__pdesc + 2), __val, BIT(12));
0090 }
0091 
0092 static inline void set_tx_desc_rdg_enable(__le32 *__pdesc, u32 __val)
0093 {
0094     le32p_replace_bits((__pdesc + 2), __val, BIT(13));
0095 }
0096 
0097 static inline void set_tx_desc_more_frag(__le32 *__pdesc, u32 __val)
0098 {
0099     le32p_replace_bits((__pdesc + 2), __val, BIT(17));
0100 }
0101 
0102 static inline void set_tx_desc_ampdu_density(__le32 *__pdesc, u32 __val)
0103 {
0104     le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20));
0105 }
0106 
0107 static inline void set_tx_desc_use_rate(__le32 *__pdesc, u32 __val)
0108 {
0109     le32p_replace_bits((__pdesc + 3), __val, BIT(8));
0110 }
0111 
0112 static inline void set_tx_desc_disable_fb(__le32 *__pdesc, u32 __val)
0113 {
0114     le32p_replace_bits((__pdesc + 3), __val, BIT(10));
0115 }
0116 
0117 static inline void set_tx_desc_cts2self(__le32 *__pdesc, u32 __val)
0118 {
0119     le32p_replace_bits((__pdesc + 3), __val, BIT(11));
0120 }
0121 
0122 static inline void set_tx_desc_rts_enable(__le32 *__pdesc, u32 __val)
0123 {
0124     le32p_replace_bits((__pdesc + 3), __val, BIT(12));
0125 }
0126 
0127 static inline void set_tx_desc_hw_rts_enable(__le32 *__pdesc, u32 __val)
0128 {
0129     le32p_replace_bits((__pdesc + 3), __val, BIT(13));
0130 }
0131 
0132 static inline void set_tx_desc_nav_use_hdr(__le32 *__pdesc, u32 __val)
0133 {
0134     le32p_replace_bits((__pdesc + 3), __val, BIT(15));
0135 }
0136 
0137 static inline void set_tx_desc_max_agg_num(__le32 *__pdesc, u32 __val)
0138 {
0139     le32p_replace_bits((__pdesc + 3), __val, GENMASK(21, 17));
0140 }
0141 
0142 /* Dword 4 */
0143 static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val)
0144 {
0145     le32p_replace_bits((__pdesc + 4), __val, GENMASK(6, 0));
0146 }
0147 
0148 static inline void set_tx_desc_data_rate_fb_limit(__le32 *__pdesc, u32 __val)
0149 {
0150     le32p_replace_bits((__pdesc + 4), __val, GENMASK(12, 8));
0151 }
0152 
0153 static inline void set_tx_desc_rts_rate_fb_limit(__le32 *__pdesc, u32 __val)
0154 {
0155     le32p_replace_bits((__pdesc + 4), __val, GENMASK(16, 13));
0156 }
0157 
0158 static inline void set_tx_desc_rts_rate(__le32 *__pdesc, u32 __val)
0159 {
0160     le32p_replace_bits((__pdesc + 4), __val, GENMASK(28, 24));
0161 }
0162 
0163 /* Dword 5 */
0164 static inline void set_tx_desc_tx_sub_carrier(__le32 *__pdesc, u32 __val)
0165 {
0166     le32p_replace_bits((__pdesc + 5), __val, GENMASK(3, 0));
0167 }
0168 
0169 static inline void set_tx_desc_data_bw(__le32 *__pdesc, u32 __val)
0170 {
0171     le32p_replace_bits((__pdesc + 4), __val, GENMASK(6, 5));
0172 }
0173 
0174 static inline void set_tx_desc_rts_short(__le32 *__pdesc, u32 __val)
0175 {
0176     le32p_replace_bits((__pdesc + 5), __val, BIT(12));
0177 }
0178 
0179 static inline void set_tx_desc_rts_sc(__le32 *__pdesc, u32 __val)
0180 {
0181     le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13));
0182 }
0183 
0184 /* Dword 7 */
0185 static inline void set_tx_desc_tx_buffer_size(__le32 *__pdesc, u32 __val)
0186 {
0187     le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));
0188 }
0189 
0190 /* Dword 9 */
0191 static inline void set_tx_desc_seq(__le32 *__pdesc, u32 __val)
0192 {
0193     le32p_replace_bits((__pdesc + 9), __val, GENMASK(23, 12));
0194 }
0195 
0196 /* Dword 10 */
0197 static inline void set_tx_desc_tx_buffer_address(__le32 *__pdesc, u32 __val)
0198 {
0199     *(__pdesc + 10) = cpu_to_le32(__val);
0200 }
0201 
0202 /* Dword 11*/
0203 static inline void set_tx_desc_next_desc_address(__le32 *__pdesc, u32 __val)
0204 {
0205     *(__pdesc + 12) = cpu_to_le32(__val);
0206 }
0207 
0208 static inline void set_earlymode_pktnum(__le32 *__paddr, u32 __val)
0209 {
0210     le32p_replace_bits(__paddr, __val, GENMASK(3, 0));
0211 }
0212 
0213 static inline void set_earlymode_len0(__le32 *__paddr, u32 __val)
0214 {
0215     le32p_replace_bits(__paddr, __val, GENMASK(18, 4));
0216 }
0217 
0218 static inline void set_earlymode_len1(__le32 *__paddr, u32 __val)
0219 {
0220     le32p_replace_bits(__paddr, __val, GENMASK(17, 16));
0221 }
0222 
0223 static inline void set_earlymode_len2_1(__le32 *__paddr, u32 __val)
0224 {
0225     le32p_replace_bits(__paddr, __val, GENMASK(5, 2));
0226 }
0227 
0228 static inline void set_earlymode_len2_2(__le32 *__paddr, u32 __val)
0229 {
0230     le32p_replace_bits((__paddr + 1), __val, GENMASK(7, 0));
0231 }
0232 
0233 static inline void set_earlymode_len3(__le32 *__paddr, u32 __val)
0234 {
0235     le32p_replace_bits((__paddr + 1), __val, GENMASK(31, 17));
0236 }
0237 
0238 static inline void set_earlymode_len4(__le32 *__paddr, u32 __val)
0239 {
0240     le32p_replace_bits((__paddr + 1), __val, GENMASK(31, 20));
0241 }
0242 
0243 /* TX/RX buffer descriptor */
0244 
0245 /* for Txfilldescroptor92ee, fill the desc content. */
0246 static inline void set_txbuffer_desc_len_with_offset(__le32 *__pdesc,
0247                              u8 __offset, u32 __val)
0248 {
0249     le32p_replace_bits((__pdesc + 4 * __offset), __val,
0250                GENMASK(15, 0));
0251 }
0252 
0253 static inline void set_txbuffer_desc_amsdu_with_offset(__le32 *__pdesc,
0254                                u8 __offset, u32 __val)
0255 {
0256     le32p_replace_bits((__pdesc + 4 * __offset), __val, BIT(31));
0257 }
0258 
0259 static inline void set_txbuffer_desc_add_low_with_offset(__le32 *__pdesc,
0260                              u8 __offset,
0261                              u32 __val)
0262 {
0263     *(__pdesc + 4 * __offset + 1) = cpu_to_le32(__val);
0264 }
0265 
0266 static inline void set_txbuffer_desc_add_high_with_offset(__le32 *pbd, u8 off,
0267                               u32 val, bool dma64)
0268 {
0269     if (dma64)
0270         *(pbd + 4 * off + 2) = cpu_to_le32(val);
0271     else
0272         *(pbd + 4 * off + 2) = 0;
0273 }
0274 
0275 static inline u32 get_txbuffer_desc_addr_low(__le32 *__pdesc, u8 __offset)
0276 {
0277     return le32_to_cpu(*((__pdesc + 4 * __offset + 1)));
0278 }
0279 
0280 static inline u32 get_txbuffer_desc_addr_high(__le32 *pbd, u32 off, bool dma64)
0281 {
0282     if (dma64)
0283         return le32_to_cpu(*((pbd + 4 * off + 2)));
0284     return 0;
0285 }
0286 
0287 /* Dword 0 */
0288 static inline void set_tx_buff_desc_len_0(__le32 *__pdesc, u32 __val)
0289 {
0290     le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));
0291 }
0292 
0293 static inline void set_tx_buff_desc_psb(__le32 *__pdesc, u32 __val)
0294 {
0295     le32p_replace_bits(__pdesc, __val, GENMASK(30, 16));
0296 }
0297 
0298 static inline void set_tx_buff_desc_own(__le32 *__pdesc, u32 __val)
0299 {
0300     le32p_replace_bits(__pdesc, __val, BIT(31));
0301 }
0302 
0303 /* Dword 1 */
0304 static inline void set_tx_buff_desc_addr_low_0(__le32 *__pdesc, u32 __val)
0305 {
0306     *(__pdesc + 1) = cpu_to_le32(__val);
0307 }
0308 
0309 /* Dword 2 */
0310 static inline void set_tx_buff_desc_addr_high_0(__le32 *pdesc, u32 val,
0311                         bool dma64)
0312 {
0313     if (dma64)
0314         *(pdesc + 2) = cpu_to_le32(val);
0315     else
0316         *(pdesc + 2) = 0;
0317 }
0318 
0319 /* RX buffer  */
0320 
0321 /* DWORD 0 */
0322 static inline void set_rx_buffer_desc_data_length(__le32 *__status, u32 __val)
0323 {
0324     le32p_replace_bits(__status, __val, GENMASK(13, 0));
0325 }
0326 
0327 static inline void set_rx_buffer_desc_ls(__le32 *__status, u32 __val)
0328 {
0329     le32p_replace_bits(__status, __val, BIT(15));
0330 }
0331 
0332 static inline void set_rx_buffer_desc_fs(__le32 *__status, u32 __val)
0333 {
0334     le32p_replace_bits(__status, __val, BIT(16));
0335 }
0336 
0337 static inline void set_rx_buffer_desc_total_length(__le32 *__status, u32 __val)
0338 {
0339     le32p_replace_bits(__status, __val, GENMASK(30, 16));
0340 }
0341 
0342 static inline int get_rx_buffer_desc_ls(__le32 *__status)
0343 {
0344     return le32_get_bits(*(__status), BIT(15));
0345 }
0346 
0347 static inline int get_rx_buffer_desc_fs(__le32 *__status)
0348 {
0349     return le32_get_bits(*(__status), BIT(16));
0350 }
0351 
0352 static inline int get_rx_buffer_desc_total_length(__le32 *__status)
0353 {
0354     return le32_get_bits(*(__status), GENMASK(30, 16));
0355 }
0356 
0357 /* DWORD 1 */
0358 static inline void set_rx_buffer_physical_low(__le32 *__status, u32 __val)
0359 {
0360     *(__status + 1) = cpu_to_le32(__val);
0361 }
0362 
0363 /* DWORD 2 */
0364 static inline void set_rx_buffer_physical_high(__le32 *__rx_status_desc,
0365                            u32 __val, bool dma64)
0366 {
0367     if (dma64)
0368         *(__rx_status_desc + 2) = cpu_to_le32(__val);
0369     else
0370         *(__rx_status_desc + 2) = 0;
0371 }
0372 
0373 static inline int get_rx_desc_pkt_len(__le32 *__pdesc)
0374 {
0375     return le32_get_bits(*__pdesc, GENMASK(13, 0));
0376 }
0377 
0378 static inline int get_rx_desc_crc32(__le32 *__pdesc)
0379 {
0380     return le32_get_bits(*__pdesc, BIT(14));
0381 }
0382 
0383 static inline int get_rx_desc_icv(__le32 *__pdesc)
0384 {
0385     return le32_get_bits(*__pdesc, BIT(15));
0386 }
0387 
0388 static inline int get_rx_desc_drv_info_size(__le32 *__pdesc)
0389 {
0390     return le32_get_bits(*__pdesc, GENMASK(19, 16));
0391 }
0392 
0393 static inline int get_rx_desc_shift(__le32 *__pdesc)
0394 {
0395     return le32_get_bits(*__pdesc, GENMASK(25, 24));
0396 }
0397 
0398 static inline int get_rx_desc_physt(__le32 *__pdesc)
0399 {
0400     return le32_get_bits(*__pdesc, BIT(26));
0401 }
0402 
0403 static inline int get_rx_desc_swdec(__le32 *__pdesc)
0404 {
0405     return le32_get_bits(*__pdesc, BIT(27));
0406 }
0407 
0408 static inline int get_rx_desc_own(__le32 *__pdesc)
0409 {
0410     return le32_get_bits(*__pdesc, BIT(31));
0411 }
0412 
0413 static inline void set_rx_desc_eor(__le32 *__pdesc, u32 __val)
0414 {
0415     le32p_replace_bits(__pdesc, __val, BIT(30));
0416 }
0417 
0418 static inline int get_rx_desc_macid(__le32 *__pdesc)
0419 {
0420     return le32_get_bits(*(__pdesc + 1), GENMASK(6, 0));
0421 }
0422 
0423 static inline int get_rx_desc_paggr(__le32 *__pdesc)
0424 {
0425     return le32_get_bits(*(__pdesc + 1), BIT(15));
0426 }
0427 
0428 static inline int get_rx_status_desc_rpt_sel(__le32 *__pdesc)
0429 {
0430     return le32_get_bits(*(__pdesc + 2), BIT(28));
0431 }
0432 
0433 static inline int get_rx_desc_rxmcs(__le32 *__pdesc)
0434 {
0435     return le32_get_bits(*(__pdesc + 3), GENMASK(6, 0));
0436 }
0437 
0438 static inline int get_rx_status_desc_pattern_match(__le32 *__pdesc)
0439 {
0440     return le32_get_bits(*(__pdesc + 3), BIT(29));
0441 }
0442 
0443 static inline int get_rx_status_desc_unicast_match(__le32 *__pdesc)
0444 {
0445     return le32_get_bits(*(__pdesc + 3), BIT(30));
0446 }
0447 
0448 static inline int get_rx_status_desc_magic_match(__le32 *__pdesc)
0449 {
0450     return le32_get_bits(*(__pdesc + 3), BIT(31));
0451 }
0452 
0453 static inline u32 get_rx_desc_tsfl(__le32 *__pdesc)
0454 {
0455     return le32_to_cpu(*((__pdesc + 5)));
0456 }
0457 
0458 static inline u32 get_rx_desc_buff_addr(__le32 *__pdesc)
0459 {
0460     return le32_to_cpu(*((__pdesc + 6)));
0461 }
0462 
0463 /* TX report 2 format in Rx desc*/
0464 
0465 static inline u32 get_rx_rpt2_desc_macid_valid_1(__le32 *__status)
0466 {
0467     return le32_to_cpu(*((__status + 4)));
0468 }
0469 
0470 static inline u32 get_rx_rpt2_desc_macid_valid_2(__le32 *__status)
0471 {
0472     return le32_to_cpu(*((__status + 5)));
0473 }
0474 
0475 static inline void clear_pci_tx_desc_content(__le32 *__pdesc, int _size)
0476 {
0477     if (_size > TX_DESC_NEXT_DESC_OFFSET)
0478         memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET);
0479     else
0480         memset(__pdesc, 0, _size);
0481 }
0482 
0483 #define RTL92EE_RX_HAL_IS_CCK_RATE(rxmcs)\
0484     (rxmcs == DESC_RATE1M ||\
0485      rxmcs == DESC_RATE2M ||\
0486      rxmcs == DESC_RATE5_5M ||\
0487      rxmcs == DESC_RATE11M)
0488 
0489 #define IS_LITTLE_ENDIAN    1
0490 
0491 struct phy_rx_agc_info_t {
0492     #if IS_LITTLE_ENDIAN
0493         u8 gain:7, trsw:1;
0494     #else
0495         u8 trsw:1, gain:7;
0496     #endif
0497 };
0498 
0499 struct phy_status_rpt {
0500     struct phy_rx_agc_info_t path_agc[2];
0501     u8 ch_corr[2];
0502     u8 cck_sig_qual_ofdm_pwdb_all;
0503     u8 cck_agc_rpt_ofdm_cfosho_a;
0504     u8 cck_rpt_b_ofdm_cfosho_b;
0505     u8 rsvd_1;
0506     u8 noise_power_db_msb;
0507     u8 path_cfotail[2];
0508     u8 pcts_mask[2];
0509     u8 stream_rxevm[2];
0510     u8 path_rxsnr[2];
0511     u8 noise_power_db_lsb;
0512     u8 rsvd_2[3];
0513     u8 stream_csi[2];
0514     u8 stream_target_csi[2];
0515     u8 sig_evm;
0516     u8 rsvd_3;
0517 #if IS_LITTLE_ENDIAN
0518     u8 antsel_rx_keep_2:1;  /*ex_intf_flg:1;*/
0519     u8 sgi_en:1;
0520     u8 rxsc:2;
0521     u8 idle_long:1;
0522     u8 r_ant_train_en:1;
0523     u8 ant_sel_b:1;
0524     u8 ant_sel:1;
0525 #else   /* _BIG_ENDIAN_ */
0526     u8 ant_sel:1;
0527     u8 ant_sel_b:1;
0528     u8 r_ant_train_en:1;
0529     u8 idle_long:1;
0530     u8 rxsc:2;
0531     u8 sgi_en:1;
0532     u8 antsel_rx_keep_2:1;  /*ex_intf_flg:1;*/
0533 #endif
0534 } __packed;
0535 
0536 struct rx_fwinfo {
0537     u8 gain_trsw[4];
0538     u8 pwdb_all;
0539     u8 cfosho[4];
0540     u8 cfotail[4];
0541     s8 rxevm[2];
0542     s8 rxsnr[4];
0543     u8 pdsnr[2];
0544     u8 csi_current[2];
0545     u8 csi_target[2];
0546     u8 sigevm;
0547     u8 max_ex_pwr;
0548     u8 ex_intf_flag:1;
0549     u8 sgi_en:1;
0550     u8 rxsc:2;
0551     u8 reserve:4;
0552 } __packed;
0553 
0554 struct tx_desc {
0555     u32 pktsize:16;
0556     u32 offset:8;
0557     u32 bmc:1;
0558     u32 htc:1;
0559     u32 lastseg:1;
0560     u32 firstseg:1;
0561     u32 linip:1;
0562     u32 noacm:1;
0563     u32 gf:1;
0564     u32 own:1;
0565 
0566     u32 macid:6;
0567     u32 rsvd0:2;
0568     u32 queuesel:5;
0569     u32 rd_nav_ext:1;
0570     u32 lsig_txop_en:1;
0571     u32 pifs:1;
0572     u32 rateid:4;
0573     u32 nav_usehdr:1;
0574     u32 en_descid:1;
0575     u32 sectype:2;
0576     u32 pktoffset:8;
0577 
0578     u32 rts_rc:6;
0579     u32 data_rc:6;
0580     u32 agg_en:1;
0581     u32 rdg_en:1;
0582     u32 bar_retryht:2;
0583     u32 agg_break:1;
0584     u32 morefrag:1;
0585     u32 raw:1;
0586     u32 ccx:1;
0587     u32 ampdudensity:3;
0588     u32 bt_int:1;
0589     u32 ant_sela:1;
0590     u32 ant_selb:1;
0591     u32 txant_cck:2;
0592     u32 txant_l:2;
0593     u32 txant_ht:2;
0594 
0595     u32 nextheadpage:8;
0596     u32 tailpage:8;
0597     u32 seq:12;
0598     u32 cpu_handle:1;
0599     u32 tag1:1;
0600     u32 trigger_int:1;
0601     u32 hwseq_en:1;
0602 
0603     u32 rtsrate:5;
0604     u32 apdcfe:1;
0605     u32 qos:1;
0606     u32 hwseq_ssn:1;
0607     u32 userrate:1;
0608     u32 dis_rtsfb:1;
0609     u32 dis_datafb:1;
0610     u32 cts2self:1;
0611     u32 rts_en:1;
0612     u32 hwrts_en:1;
0613     u32 portid:1;
0614     u32 pwr_status:3;
0615     u32 waitdcts:1;
0616     u32 cts2ap_en:1;
0617     u32 txsc:2;
0618     u32 stbc:2;
0619     u32 txshort:1;
0620     u32 txbw:1;
0621     u32 rtsshort:1;
0622     u32 rtsbw:1;
0623     u32 rtssc:2;
0624     u32 rtsstbc:2;
0625 
0626     u32 txrate:6;
0627     u32 shortgi:1;
0628     u32 ccxt:1;
0629     u32 txrate_fb_lmt:5;
0630     u32 rtsrate_fb_lmt:4;
0631     u32 retrylmt_en:1;
0632     u32 txretrylmt:6;
0633     u32 usb_txaggnum:8;
0634 
0635     u32 txagca:5;
0636     u32 txagcb:5;
0637     u32 usemaxlen:1;
0638     u32 maxaggnum:5;
0639     u32 mcsg1maxlen:4;
0640     u32 mcsg2maxlen:4;
0641     u32 mcsg3maxlen:4;
0642     u32 mcs7sgimaxlen:4;
0643 
0644     u32 txbuffersize:16;
0645     u32 sw_offset30:8;
0646     u32 sw_offset31:4;
0647     u32 rsvd1:1;
0648     u32 antsel_c:1;
0649     u32 null_0:1;
0650     u32 null_1:1;
0651 
0652     u32 txbuffaddr;
0653     u32 txbufferaddr64;
0654     u32 nextdescaddress;
0655     u32 nextdescaddress64;
0656 
0657     u32 reserve_pass_pcie_mm_limit[4];
0658 } __packed;
0659 
0660 struct rx_desc {
0661     u32 length:14;
0662     u32 crc32:1;
0663     u32 icverror:1;
0664     u32 drv_infosize:4;
0665     u32 security:3;
0666     u32 qos:1;
0667     u32 shift:2;
0668     u32 phystatus:1;
0669     u32 swdec:1;
0670     u32 lastseg:1;
0671     u32 firstseg:1;
0672     u32 eor:1;
0673     u32 own:1;
0674 
0675     u32 macid:6;
0676     u32 tid:4;
0677     u32 hwrsvd:5;
0678     u32 paggr:1;
0679     u32 faggr:1;
0680     u32 a1_fit:4;
0681     u32 a2_fit:4;
0682     u32 pam:1;
0683     u32 pwr:1;
0684     u32 moredata:1;
0685     u32 morefrag:1;
0686     u32 type:2;
0687     u32 mc:1;
0688     u32 bc:1;
0689 
0690     u32 seq:12;
0691     u32 frag:4;
0692     u32 nextpktlen:14;
0693     u32 nextind:1;
0694     u32 rsvd:1;
0695 
0696     u32 rxmcs:6;
0697     u32 rxht:1;
0698     u32 amsdu:1;
0699     u32 splcp:1;
0700     u32 bandwidth:1;
0701     u32 htc:1;
0702     u32 tcpchk_rpt:1;
0703     u32 ipcchk_rpt:1;
0704     u32 tcpchk_valid:1;
0705     u32 hwpcerr:1;
0706     u32 hwpcind:1;
0707     u32 iv0:16;
0708 
0709     u32 iv1;
0710 
0711     u32 tsfl;
0712 
0713     u32 bufferaddress;
0714     u32 bufferaddress64;
0715 
0716 } __packed;
0717 
0718 void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
0719                  u8 queue_index);
0720 u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw,
0721                       u8 queue_index);
0722 u16 rtl92ee_get_available_desc(struct ieee80211_hw *hw, u8 queue_index);
0723 void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
0724                  u8 *tx_bd_desc, u8 *desc, u8 queue_index,
0725                  struct sk_buff *skb, dma_addr_t addr);
0726 
0727 void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw,
0728               struct ieee80211_hdr *hdr, u8 *pdesc_tx,
0729               u8 *pbd_desc_tx,
0730               struct ieee80211_tx_info *info,
0731               struct ieee80211_sta *sta,
0732               struct sk_buff *skb,
0733               u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
0734 bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,
0735                struct rtl_stats *status,
0736                struct ieee80211_rx_status *rx_status,
0737                u8 *pdesc, struct sk_buff *skb);
0738 void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
0739               u8 desc_name, u8 *val);
0740 
0741 u64 rtl92ee_get_desc(struct ieee80211_hw *hw,
0742              u8 *pdesc, bool istx, u8 desc_name);
0743 bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index);
0744 void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
0745 void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
0746                  bool firstseg, bool lastseg,
0747                  struct sk_buff *skb);
0748 #endif
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