rtlwifi/rtl8192ee/sw.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 2009-2014  Realtek Corporation.*/
0003
0004 #include "../wifi.h"
0005 #include "../core.h"
0006 #include "../pci.h"
0007 #include "reg.h"
0008 #include "def.h"
0009 #include "phy.h"
0010 #include "dm.h"
0011 #include "hw.h"
0012 #include "fw.h"
0013 #include "trx.h"
0014 #include "led.h"
0015 #include "table.h"
0016
0017 #include "../btcoexist/rtl_btc.h"
0018
0019 #include <linux/vmalloc.h>
0020 #include <linux/module.h>
0021
0022 static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw)
0023 {
0024     struct rtl_priv *rtlpriv = rtl_priv(hw);
0025     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0026
0027     /*close ASPM for AMD defaultly */
0028     rtlpci->const_amdpci_aspm = 0;
0029
0030     /**
0031      * ASPM PS mode.
0032      * 0 - Disable ASPM,
0033      * 1 - Enable ASPM without Clock Req,
0034      * 2 - Enable ASPM with Clock Req,
0035      * 3 - Alwyas Enable ASPM with Clock Req,
0036      * 4 - Always Enable ASPM without Clock Req.
0037      * set defult to RTL8192CE:3 RTL8192E:2
0038      */
0039     rtlpci->const_pci_aspm = 3;
0040
0041     /*Setting for PCI-E device */
0042     rtlpci->const_devicepci_aspm_setting = 0x03;
0043
0044     /*Setting for PCI-E bridge */
0045     rtlpci->const_hostpci_aspm_setting = 0x02;
0046
0047     /**
0048      * In Hw/Sw Radio Off situation.
0049      * 0 - Default,
0050      * 1 - From ASPM setting without low Mac Pwr,
0051      * 2 - From ASPM setting with low Mac Pwr,
0052      * 3 - Bus D3
0053      * set default to RTL8192CE:0 RTL8192SE:2
0054      */
0055     rtlpci->const_hwsw_rfoff_d3 = 0;
0056
0057     /**
0058      * This setting works for those device with
0059      * backdoor ASPM setting such as EPHY setting.
0060      * 0 - Not support ASPM,
0061      * 1 - Support ASPM,
0062      * 2 - According to chipset.
0063      */
0064     rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
0065 }
0066
0067 static int rtl92ee_init_sw_vars(struct ieee80211_hw *hw)
0068 {
0069     struct rtl_priv *rtlpriv = rtl_priv(hw);
0070     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0071     int err = 0;
0072     char *fw_name;
0073
0074     rtl92ee_bt_reg_init(hw);
0075     rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
0076     rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
0077
0078     rtlpriv->dm.dm_initialgain_enable = true;
0079     rtlpriv->dm.dm_flag = 0;
0080     rtlpriv->dm.disable_framebursting = false;
0081     rtlpci->transmit_config = CFENDFORM | BIT(15);
0082
0083     /*just 2.4G band*/
0084     rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
0085     rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
0086     rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
0087
0088     rtlpci->receive_config = (RCR_APPFCS            |
0089                   RCR_APP_MIC           |
0090                   RCR_APP_ICV           |
0091                   RCR_APP_PHYST_RXFF        |
0092                   RCR_HTC_LOC_CTRL      |
0093                   RCR_AMF           |
0094                   RCR_ACF           |
0095                   RCR_ACRC32            |
0096                   RCR_AB            |
0097                   RCR_AM            |
0098                   RCR_APM           |
0099                   0);
0100
0101     rtlpci->irq_mask[0] = (u32)(IMR_PSTIMEOUT       |
0102                      IMR_C2HCMD         |
0103                      IMR_HIGHDOK        |
0104                      IMR_MGNTDOK        |
0105                      IMR_BKDOK          |
0106                      IMR_BEDOK          |
0107                      IMR_VIDOK          |
0108                      IMR_VODOK          |
0109                      IMR_RDU            |
0110                      IMR_ROK            |
0111                      0);
0112     rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);
0113
0114     /* for LPS & IPS */
0115     rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
0116     rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
0117     rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
0118     rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
0119     if (rtlpriv->cfg->mod_params->disable_watchdog)
0120         pr_info("watchdog disabled\n");
0121     rtlpriv->psc.reg_fwctrl_lps = 3;
0122     rtlpriv->psc.reg_max_lps_awakeintvl = 5;
0123     /* for ASPM, you can close aspm through
0124      * set const_support_pciaspm = 0
0125      */
0126     rtl92ee_init_aspm_vars(hw);
0127
0128     if (rtlpriv->psc.reg_fwctrl_lps == 1)
0129         rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
0130     else if (rtlpriv->psc.reg_fwctrl_lps == 2)
0131         rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
0132     else if (rtlpriv->psc.reg_fwctrl_lps == 3)
0133         rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
0134
0135     /* for early mode */
0136     rtlpriv->rtlhal.earlymode_enable = false;
0137
0138     /*low power */
0139     rtlpriv->psc.low_power_enable = false;
0140
0141     /* for firmware buf */
0142     rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
0143     if (!rtlpriv->rtlhal.pfirmware) {
0144         pr_err("Can't alloc buffer for fw\n");
0145         return 1;
0146     }
0147
0148     /* request fw */
0149     fw_name = "rtlwifi/rtl8192eefw.bin";
0150
0151     rtlpriv->max_fw_size = 0x8000;
0152     pr_info("Using firmware %s\n", fw_name);
0153     err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
0154                       rtlpriv->io.dev, GFP_KERNEL, hw,
0155                       rtl_fw_cb);
0156     if (err) {
0157         pr_err("Failed to request firmware!\n");
0158         vfree(rtlpriv->rtlhal.pfirmware);
0159         rtlpriv->rtlhal.pfirmware = NULL;
0160         return 1;
0161     }
0162
0163     return 0;
0164 }
0165
0166 static void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw)
0167 {
0168     struct rtl_priv *rtlpriv = rtl_priv(hw);
0169
0170     if (rtlpriv->rtlhal.pfirmware) {
0171         vfree(rtlpriv->rtlhal.pfirmware);
0172         rtlpriv->rtlhal.pfirmware = NULL;
0173     }
0174 }
0175
0176 /* get bt coexist status */
0177 static bool rtl92ee_get_btc_status(void)
0178 {
0179     return true;
0180 }
0181
0182 static struct rtl_hal_ops rtl8192ee_hal_ops = {
0183     .init_sw_vars = rtl92ee_init_sw_vars,
0184     .deinit_sw_vars = rtl92ee_deinit_sw_vars,
0185     .read_eeprom_info = rtl92ee_read_eeprom_info,
0186     .interrupt_recognized = rtl92ee_interrupt_recognized,/*need check*/
0187     .hw_init = rtl92ee_hw_init,
0188     .hw_disable = rtl92ee_card_disable,
0189     .hw_suspend = rtl92ee_suspend,
0190     .hw_resume = rtl92ee_resume,
0191     .enable_interrupt = rtl92ee_enable_interrupt,
0192     .disable_interrupt = rtl92ee_disable_interrupt,
0193     .set_network_type = rtl92ee_set_network_type,
0194     .set_chk_bssid = rtl92ee_set_check_bssid,
0195     .set_qos = rtl92ee_set_qos,
0196     .set_bcn_reg = rtl92ee_set_beacon_related_registers,
0197     .set_bcn_intv = rtl92ee_set_beacon_interval,
0198     .update_interrupt_mask = rtl92ee_update_interrupt_mask,
0199     .get_hw_reg = rtl92ee_get_hw_reg,
0200     .set_hw_reg = rtl92ee_set_hw_reg,
0201     .update_rate_tbl = rtl92ee_update_hal_rate_tbl,
0202     .pre_fill_tx_bd_desc = rtl92ee_pre_fill_tx_bd_desc,
0203     .rx_desc_buff_remained_cnt = rtl92ee_rx_desc_buff_remained_cnt,
0204     .rx_check_dma_ok = rtl92ee_rx_check_dma_ok,
0205     .fill_tx_desc = rtl92ee_tx_fill_desc,
0206     .fill_tx_cmddesc = rtl92ee_tx_fill_cmddesc,
0207     .query_rx_desc = rtl92ee_rx_query_desc,
0208     .set_channel_access = rtl92ee_update_channel_access_setting,
0209     .radio_onoff_checking = rtl92ee_gpio_radio_on_off_checking,
0210     .set_bw_mode = rtl92ee_phy_set_bw_mode,
0211     .switch_channel = rtl92ee_phy_sw_chnl,
0212     .dm_watchdog = rtl92ee_dm_watchdog,
0213     .scan_operation_backup = rtl92ee_phy_scan_operation_backup,
0214     .set_rf_power_state = rtl92ee_phy_set_rf_power_state,
0215     .led_control = rtl92ee_led_control,
0216     .set_desc = rtl92ee_set_desc,
0217     .get_desc = rtl92ee_get_desc,
0218     .is_tx_desc_closed = rtl92ee_is_tx_desc_closed,
0219     .get_available_desc = rtl92ee_get_available_desc,
0220     .tx_polling = rtl92ee_tx_polling,
0221     .enable_hw_sec = rtl92ee_enable_hw_security_config,
0222     .set_key = rtl92ee_set_key,
0223     .init_sw_leds = rtl92ee_init_sw_leds,
0224     .get_bbreg = rtl92ee_phy_query_bb_reg,
0225     .set_bbreg = rtl92ee_phy_set_bb_reg,
0226     .get_rfreg = rtl92ee_phy_query_rf_reg,
0227     .set_rfreg = rtl92ee_phy_set_rf_reg,
0228     .fill_h2c_cmd = rtl92ee_fill_h2c_cmd,
0229     .get_btc_status = rtl92ee_get_btc_status,
0230     .c2h_ra_report_handler = rtl92ee_c2h_ra_report_handler,
0231 };
0232
0233 static struct rtl_mod_params rtl92ee_mod_params = {
0234     .sw_crypto = false,
0235     .inactiveps = true,
0236     .swctrl_lps = false,
0237     .fwctrl_lps = true,
0238     .msi_support = true,
0239     .dma64 = false,
0240     .aspm_support = 1,
0241     .debug_level = 0,
0242     .debug_mask = 0,
0243 };
0244
0245 static const struct rtl_hal_cfg rtl92ee_hal_cfg = {
0246     .bar_id = 2,
0247     .write_readback = true,
0248     .name = "rtl92ee_pci",
0249     .ops = &rtl8192ee_hal_ops,
0250     .mod_params = &rtl92ee_mod_params,
0251
0252     .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
0253     .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
0254     .maps[SYS_CLK] = REG_SYS_CLKR,
0255     .maps[MAC_RCR_AM] = AM,
0256     .maps[MAC_RCR_AB] = AB,
0257     .maps[MAC_RCR_ACRC32] = ACRC32,
0258     .maps[MAC_RCR_ACF] = ACF,
0259     .maps[MAC_RCR_AAP] = AAP,
0260     .maps[MAC_HIMR] = REG_HIMR,
0261     .maps[MAC_HIMRE] = REG_HIMRE,
0262
0263     .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
0264
0265     .maps[EFUSE_TEST] = REG_EFUSE_TEST,
0266     .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
0267     .maps[EFUSE_CLK] = 0,
0268     .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
0269     .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
0270     .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
0271     .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
0272     .maps[EFUSE_ANA8M] = ANA8M,
0273     .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
0274     .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
0275     .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
0276     .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
0277
0278     .maps[RWCAM] = REG_CAMCMD,
0279     .maps[WCAMI] = REG_CAMWRITE,
0280     .maps[RCAMO] = REG_CAMREAD,
0281     .maps[CAMDBG] = REG_CAMDBG,
0282     .maps[SECR] = REG_SECCFG,
0283     .maps[SEC_CAM_NONE] = CAM_NONE,
0284     .maps[SEC_CAM_WEP40] = CAM_WEP40,
0285     .maps[SEC_CAM_TKIP] = CAM_TKIP,
0286     .maps[SEC_CAM_AES] = CAM_AES,
0287     .maps[SEC_CAM_WEP104] = CAM_WEP104,
0288
0289     .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
0290     .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
0291     .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
0292     .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
0293     .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
0294     .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
0295     .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
0296     .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
0297     .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
0298     .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
0299     .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
0300     .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
0301     .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
0302
0303     .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
0304     .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
0305     .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
0306     .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
0307     .maps[RTL_IMR_RDU] = IMR_RDU,
0308     .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
0309     .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
0310     .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
0311     .maps[RTL_IMR_TBDER] = IMR_TBDER,
0312     .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
0313     .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
0314     .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
0315     .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
0316     .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
0317     .maps[RTL_IMR_VODOK] = IMR_VODOK,
0318     .maps[RTL_IMR_ROK] = IMR_ROK,
0319     .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
0320
0321     .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
0322     .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
0323     .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
0324     .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
0325     .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
0326     .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
0327     .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
0328     .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
0329     .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
0330     .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
0331     .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
0332     .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
0333
0334     .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
0335     .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
0336 };
0337
0338 static const struct pci_device_id rtl92ee_pci_ids[] = {
0339     {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x818B, rtl92ee_hal_cfg)},
0340     {},
0341 };
0342
0343 MODULE_DEVICE_TABLE(pci, rtl92ee_pci_ids);
0344
0345 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
0346 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
0347 MODULE_LICENSE("GPL");
0348 MODULE_DESCRIPTION("Realtek 8192EE 802.11n PCI wireless");
0349 MODULE_FIRMWARE("rtlwifi/rtl8192eefw.bin");
0350
0351 module_param_named(swenc, rtl92ee_mod_params.sw_crypto, bool, 0444);
0352 module_param_named(debug_level, rtl92ee_mod_params.debug_level, int, 0644);
0353 module_param_named(debug_mask, rtl92ee_mod_params.debug_mask, ullong, 0644);
0354 module_param_named(ips, rtl92ee_mod_params.inactiveps, bool, 0444);
0355 module_param_named(swlps, rtl92ee_mod_params.swctrl_lps, bool, 0444);
0356 module_param_named(fwlps, rtl92ee_mod_params.fwctrl_lps, bool, 0444);
0357 module_param_named(msi, rtl92ee_mod_params.msi_support, bool, 0444);
0358 module_param_named(dma64, rtl92ee_mod_params.dma64, bool, 0444);
0359 module_param_named(aspm, rtl92ee_mod_params.aspm_support, int, 0444);
0360 module_param_named(disable_watchdog, rtl92ee_mod_params.disable_watchdog,
0361            bool, 0444);
0362 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
0363 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
0364 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
0365 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
0366 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
0367 MODULE_PARM_DESC(dma64, "Set to 1 to use DMA 64 (default 0)\n");
0368 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
0369 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
0370 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
0371 MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
0372
0373 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
0374
0375 static struct pci_driver rtl92ee_driver = {
0376     .name = KBUILD_MODNAME,
0377     .id_table = rtl92ee_pci_ids,
0378     .probe = rtl_pci_probe,
0379     .remove = rtl_pci_disconnect,
0380     .driver.pm = &rtlwifi_pm_ops,
0381 };
0382
0383 module_pci_driver(rtl92ee_driver);