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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2014  Realtek Corporation.*/
0003 
0004 #ifndef __RTL92E_PWRSEQ_H__
0005 #define __RTL92E_PWRSEQ_H__
0006 
0007 #include "../pwrseqcmd.h"
0008 /**
0009  *  Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd
0010  *  There are 6 HW Power States:
0011  *  0: POFF--Power Off
0012  *  1: PDN--Power Down
0013  *  2: CARDEMU--Card Emulation
0014  *  3: ACT--Active Mode
0015  *  4: LPS--Low Power State
0016  *  5: SUS--Suspend
0017  *
0018  *  The transision from different states are defined below
0019  *  TRANS_CARDEMU_TO_ACT
0020  *  TRANS_ACT_TO_CARDEMU
0021  *  TRANS_CARDEMU_TO_SUS
0022  *  TRANS_SUS_TO_CARDEMU
0023  *  TRANS_CARDEMU_TO_PDN
0024  *  TRANS_ACT_TO_LPS
0025  *  TRANS_LPS_TO_ACT
0026  *
0027  *  TRANS_END
0028  *  PWR SEQ Version: rtl8192E_PwrSeq_V09.h
0029  */
0030 
0031 #define RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS 18
0032 #define RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS 18
0033 #define RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS 18
0034 #define RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS 18
0035 #define RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS 18
0036 #define RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS 18
0037 #define RTL8192E_TRANS_ACT_TO_LPS_STEPS     23
0038 #define RTL8192E_TRANS_LPS_TO_ACT_STEPS     23
0039 #define RTL8192E_TRANS_END_STEPS        1
0040 
0041 #define RTL8192E_TRANS_CARDEMU_TO_ACT                   \
0042     /* format */                            \
0043     /* comments here */                     \
0044     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
0045     /* disable HWPDN 0x04[15]=0*/                   \
0046     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0047      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},          \
0048     /* disable SW LPS 0x04[10]=0*/                  \
0049     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0050      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0},          \
0051     /* disable WL suspend*/                     \
0052     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0053      PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},     \
0054     /* wait till 0x04[17] = 1    power ready*/          \
0055     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0056      PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)},       \
0057     /* release WLON reset  0x04[16]=1*/             \
0058     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0059      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)},     \
0060     /* polling until return 0*/                 \
0061     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0062      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)},     \
0063     /**/                                \
0064     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0065      PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0},
0066 
0067 #define RTL8192E_TRANS_ACT_TO_CARDEMU                   \
0068     /* format */                            \
0069     /* comments here */                     \
0070     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
0071     /*0x1F[7:0] = 0 turn off RF*/                   \
0072     {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0073      PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0},            \
0074     /*0x4C[23]=0x4E[7]=0, switch DPDT_SEL_P output from register 0x65[2] */\
0075     {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0076      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},          \
0077     /*0x04[9] = 1 turn off MAC by HW state machine*/        \
0078     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0079      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)},     \
0080     /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
0081     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0082      PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), 0},
0083 
0084 #define RTL8192E_TRANS_CARDEMU_TO_SUS                   \
0085     /* format */                            \
0086     /* comments here */                     \
0087     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
0088     /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/      \
0089     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0090      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\
0091     /*0x04[12:11] = 2b'01 enable WL suspend*/           \
0092     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0093      PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,    \
0094      PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},             \
0095     /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/      \
0096     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0097      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
0098     /*Set SDIO suspend local register*/             \
0099     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0100      PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)},        \
0101      /*wait power state to suspend*/                \
0102     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0103      PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
0104 
0105 #define RTL8192E_TRANS_SUS_TO_CARDEMU                   \
0106     /* format */                            \
0107     /* comments here */                     \
0108     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
0109     /*Set SDIO suspend local register*/             \
0110     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0111      PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0},         \
0112     /*wait power state to suspend*/                 \
0113     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0114      PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)},      \
0115     /*0x04[12:11] = 2b'00 disable WL suspend*/          \
0116     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0117      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
0118 
0119 #define RTL8192E_TRANS_CARDEMU_TO_CARDDIS               \
0120     /* format */                            \
0121     /* comments here */                     \
0122     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
0123     /*0x07=0x20 , SOP option to disable BG/MB*/         \
0124     {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0125      PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x20},         \
0126     /*Unlock small LDO Register*/                   \
0127     {0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0128      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)},     \
0129     /*Disable small LDO*/                       \
0130     {0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0131      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0},          \
0132     /*0x04[12:11] = 2b'01 enable WL suspend*/           \
0133     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0134      PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,      \
0135      PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},             \
0136     /*0x04[10] = 1, enable SW LPS*/                 \
0137     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0138      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)},     \
0139     /*Set SDIO suspend local register*/             \
0140     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0141      PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)},        \
0142     /*wait power state to suspend*/                 \
0143     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0144      PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
0145 
0146 #define RTL8192E_TRANS_CARDDIS_TO_CARDEMU               \
0147     /* format */                            \
0148     /* comments here */                     \
0149     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
0150     /*Set SDIO suspend local register*/             \
0151     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0152      PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0},         \
0153     /*wait power state to suspend*/                 \
0154     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0155      PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)},      \
0156     /*Enable small LDO*/                        \
0157     {0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0158      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)},     \
0159     /*Lock small LDO Register*/                 \
0160     {0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0161      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0},          \
0162     /*0x04[12:11] = 2b'00 disable WL suspend*/          \
0163     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0164      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
0165 
0166 #define RTL8192E_TRANS_CARDEMU_TO_PDN                   \
0167     /* format */                            \
0168     /* comments here */                     \
0169     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
0170     /* 0x04[16] = 0*/                       \
0171     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0172      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0},          \
0173     /* 0x04[15] = 1*/                       \
0174     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0175      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), BIT(7)},
0176 
0177 #define RTL8192E_TRANS_PDN_TO_CARDEMU                   \
0178     /* format */                            \
0179     /* comments here */                     \
0180     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
0181     /* 0x04[15] = 0*/                       \
0182     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0183      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},
0184 
0185 #define RTL8192E_TRANS_ACT_TO_LPS                   \
0186     /* format */                            \
0187     /* comments here */                     \
0188     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
0189     /*PCIe DMA stop*/                       \
0190     {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0191      PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},         \
0192     /*Tx Pause*/                            \
0193     {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0194      PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},         \
0195     /*Should be zero if no packet is transmitting*/         \
0196     {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0197      PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},          \
0198     /*Should be zero if no packet is transmitting*/         \
0199     {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0200      PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},          \
0201     /*Should be zero if no packet is transmitting*/         \
0202     {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0203      PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},          \
0204     /*Should be zero if no packet is transmitting*/         \
0205     {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0206      PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},          \
0207     /*CCK and OFDM are disabled,and clock are gated*/       \
0208     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0209      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0},          \
0210     /*Delay 1us*/                           \
0211     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0212      PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},     \
0213     /*Whole BB is reset*/                       \
0214     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0215      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0},          \
0216     /*Reset MAC TRX*/                       \
0217     {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0218      PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x03},         \
0219     /*check if removed later*/                  \
0220     {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0221      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0},          \
0222     /*When driver enter Sus/ Disable, enable LOP for BT*/       \
0223     {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0224      PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x00},         \
0225     /*Respond TxOK to scheduler*/                   \
0226     {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0227      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(5), BIT(5)},
0228 
0229 #define RTL8192E_TRANS_LPS_TO_ACT                   \
0230     /* format */                            \
0231     /* comments here */                     \
0232     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
0233     /*SDIO RPWM, For Repeatly In and out, Taggle bit should be changed*/\
0234     {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0235      PWR_BASEADDR_SDIO , PWR_CMD_WRITE, 0xFF, 0x84},        \
0236     /*USB RPWM*/                            \
0237     {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
0238      PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84},         \
0239     /*PCIe RPWM*/                           \
0240     {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0241      PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84},         \
0242     /*Delay*/                           \
0243     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0244      PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS},     \
0245     /*0x08[4] = 0 switch TSF to 40M*/               \
0246     {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0247      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4), 0},          \
0248     /*Polling 0x109[7]=0  TSF in 40M*/              \
0249     {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0250      PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(7), 0},        \
0251     /*0x101[1] = 1*/                        \
0252     {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0253      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)},     \
0254     /*0x100[7:0] = 0xFF  enable WMAC TRX*/              \
0255     {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0256      PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},         \
0257     /* 0x02[1:0] = 2b'11 enable BB macro*/              \
0258     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0259      PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\
0260     /*0x522 = 0*/                           \
0261     {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0262      PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0},            \
0263     /*Clear ISR*/                           \
0264     {0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0265      PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},
0266 
0267 #define RTL8192E_TRANS_END                      \
0268     /* format */                            \
0269     /* comments here */                     \
0270     /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
0271     {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0272      0, PWR_CMD_END, 0, 0},
0273 
0274 extern struct wlan_pwr_cfg rtl8192E_power_on_flow
0275                     [RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS +
0276                      RTL8192E_TRANS_END_STEPS];
0277 extern struct wlan_pwr_cfg rtl8192E_radio_off_flow
0278                     [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
0279                      RTL8192E_TRANS_END_STEPS];
0280 extern struct wlan_pwr_cfg rtl8192E_card_disable_flow
0281                     [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
0282                      RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
0283                      RTL8192E_TRANS_END_STEPS];
0284 extern struct wlan_pwr_cfg rtl8192E_card_enable_flow
0285                     [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
0286                      RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
0287                      RTL8192E_TRANS_END_STEPS];
0288 extern struct wlan_pwr_cfg rtl8192E_suspend_flow
0289                     [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
0290                      RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
0291                      RTL8192E_TRANS_END_STEPS];
0292 extern struct wlan_pwr_cfg rtl8192E_resume_flow
0293                     [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
0294                      RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
0295                      RTL8192E_TRANS_END_STEPS];
0296 extern struct wlan_pwr_cfg rtl8192E_hwpdn_flow
0297                     [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
0298                      RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
0299                      RTL8192E_TRANS_END_STEPS];
0300 extern struct wlan_pwr_cfg rtl8192E_enter_lps_flow
0301                     [RTL8192E_TRANS_ACT_TO_LPS_STEPS +
0302                      RTL8192E_TRANS_END_STEPS];
0303 extern struct wlan_pwr_cfg rtl8192E_leave_lps_flow
0304                     [RTL8192E_TRANS_LPS_TO_ACT_STEPS +
0305                      RTL8192E_TRANS_END_STEPS];
0306 
0307 /* RTL8192EE Power Configuration CMDs for PCIe interface */
0308 #define RTL8192E_NIC_PWR_ON_FLOW    rtl8192E_power_on_flow
0309 #define RTL8192E_NIC_RF_OFF_FLOW    rtl8192E_radio_off_flow
0310 #define RTL8192E_NIC_DISABLE_FLOW   rtl8192E_card_disable_flow
0311 #define RTL8192E_NIC_ENABLE_FLOW    rtl8192E_card_enable_flow
0312 #define RTL8192E_NIC_SUSPEND_FLOW   rtl8192E_suspend_flow
0313 #define RTL8192E_NIC_RESUME_FLOW    rtl8192E_resume_flow
0314 #define RTL8192E_NIC_PDN_FLOW       rtl8192E_hwpdn_flow
0315 #define RTL8192E_NIC_LPS_ENTER_FLOW rtl8192E_enter_lps_flow
0316 #define RTL8192E_NIC_LPS_LEAVE_FLOW rtl8192E_leave_lps_flow
0317 
0318 #endif
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