rtlwifi/rtl8192ee/phy.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2014  Realtek Corporation.*/
0003
0004 #ifndef __RTL92E_PHY_H__
0005 #define __RTL92E_PHY_H__
0006
0007 /* MAX_TX_COUNT must always set to 4, otherwise read efuse table sequence
0008  * will be wrong.
0009  */
0010 #define MAX_TX_COUNT                4
0011 #define TX_1S                   0
0012 #define TX_2S                   1
0013 #define TX_3S                   2
0014 #define TX_4S                   3
0015
0016 #define MAX_POWER_INDEX             0x3f
0017
0018 #define MAX_PRECMD_CNT              16
0019 #define MAX_RFDEPENDCMD_CNT         16
0020 #define MAX_POSTCMD_CNT             16
0021
0022 #define MAX_DOZE_WAITING_TIMES_9x       64
0023
0024 #define RT_CANNOT_IO(hw)            false
0025 #define HIGHPOWER_RADIOA_ARRAYLEN       22
0026
0027 #define IQK_ADDA_REG_NUM            16
0028 #define IQK_MAC_REG_NUM             4
0029 #define IQK_BB_REG_NUM              9
0030 #define MAX_TOLERANCE               5
0031 #define IQK_DELAY_TIME              10
0032 #define index_mapping_NUM           15
0033
0034 #define APK_BB_REG_NUM              5
0035 #define APK_AFE_REG_NUM             16
0036 #define APK_CURVE_REG_NUM           4
0037 #define PATH_NUM                2
0038
0039 #define LOOP_LIMIT              5
0040 #define MAX_STALL_TIME              50
0041 #define ANTENNADIVERSITYVALUE           0x80
0042 #define MAX_TXPWR_IDX_NMODE_92S         63
0043 #define RESET_CNT_LIMIT             3
0044
0045 #define RF6052_MAX_PATH             2
0046
0047 #define CT_OFFSET_MAC_ADDR          0X16
0048
0049 #define CT_OFFSET_CCK_TX_PWR_IDX        0x5A
0050 #define CT_OFFSET_HT401S_TX_PWR_IDX     0x60
0051 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF    0x66
0052 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF      0x69
0053 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF      0x6C
0054
0055 #define CT_OFFSET_HT40_MAX_PWR_OFFSET       0x6F
0056 #define CT_OFFSET_HT20_MAX_PWR_OFFSET       0x72
0057
0058 #define CT_OFFSET_CHANNEL_PLAH          0x75
0059 #define CT_OFFSET_THERMAL_METER         0x78
0060 #define CT_OFFSET_RF_OPTION         0x79
0061 #define CT_OFFSET_VERSION           0x7E
0062 #define CT_OFFSET_CUSTOMER_ID           0x7F
0063
0064 #define RTL92C_MAX_PATH_NUM         2
0065
0066 enum swchnlcmd_id {
0067     CMDID_END,
0068     CMDID_SET_TXPOWEROWER_LEVEL,
0069     CMDID_BBREGWRITE10,
0070     CMDID_WRITEPORT_ULONG,
0071     CMDID_WRITEPORT_USHORT,
0072     CMDID_WRITEPORT_UCHAR,
0073     CMDID_RF_WRITEREG,
0074 };
0075
0076 struct swchnlcmd {
0077     enum swchnlcmd_id cmdid;
0078     u32 para1;
0079     u32 para2;
0080     u32 msdelay;
0081 };
0082
0083 enum baseband_config_type {
0084     BASEBAND_CONFIG_PHY_REG = 0,
0085     BASEBAND_CONFIG_AGC_TAB = 1,
0086 };
0087
0088 enum ant_div_type {
0089     NO_ANTDIV = 0xFF,
0090     CG_TRX_HW_ANTDIV = 0x01,
0091     CGCS_RX_HW_ANTDIV = 0x02,
0092     FIXED_HW_ANTDIV = 0x03,
0093     CG_TRX_SMART_ANTDIV = 0x04,
0094     CGCS_RX_SW_ANTDIV = 0x05,
0095 };
0096
0097 u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw,
0098                  u32 regaddr, u32 bitmask);
0099 void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw,
0100                 u32 regaddr, u32 bitmask, u32 data);
0101 u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw,
0102                  enum radio_path rfpath, u32 regaddr,
0103                  u32 bitmask);
0104 void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw,
0105                 enum radio_path rfpath, u32 regaddr,
0106                 u32 bitmask, u32 data);
0107 bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw);
0108 bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw);
0109 bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw);
0110 void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
0111 void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw,
0112                    long *powerlevel);
0113 void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
0114 void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw,
0115                        u8 operation);
0116 void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
0117 void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw,
0118                  enum nl80211_channel_type ch_type);
0119 void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw);
0120 u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw);
0121 void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
0122 void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta);
0123 void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw);
0124 void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
0125 bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
0126                        enum radio_path rfpath);
0127 bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
0128 bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
0129                     enum rf_pwrstate rfpwr_state);
0130
0131 #endif