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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 2009-2014  Realtek Corporation.*/
0003 
0004 #include "../wifi.h"
0005 #include "../pci.h"
0006 #include "../ps.h"
0007 #include "reg.h"
0008 #include "def.h"
0009 #include "phy.h"
0010 #include "rf.h"
0011 #include "dm.h"
0012 #include "table.h"
0013 
0014 static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw,
0015                        enum radio_path rfpath, u32 offset);
0016 static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw,
0017                      enum radio_path rfpath, u32 offset,
0018                      u32 data);
0019 static u32 _rtl92ee_phy_calculate_bit_shift(u32 bitmask);
0020 static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw);
0021 static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
0022 static bool phy_config_bb_with_hdr_file(struct ieee80211_hw *hw,
0023                     u8 configtype);
0024 static bool phy_config_bb_with_pghdrfile(struct ieee80211_hw *hw,
0025                      u8 configtype);
0026 static void phy_init_bb_rf_register_def(struct ieee80211_hw *hw);
0027 static bool _rtl92ee_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
0028                           u32 cmdtableidx, u32 cmdtablesz,
0029                           enum swchnlcmd_id cmdid,
0030                           u32 para1, u32 para2,
0031                           u32 msdelay);
0032 static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
0033                           u8 channel, u8 *stage,
0034                           u8 *step, u32 *delay);
0035 static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
0036                       enum wireless_mode wirelessmode,
0037                       u8 txpwridx);
0038 static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw);
0039 static void rtl92ee_phy_set_io(struct ieee80211_hw *hw);
0040 
0041 u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
0042 {
0043     struct rtl_priv *rtlpriv = rtl_priv(hw);
0044     u32 returnvalue, originalvalue, bitshift;
0045 
0046     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0047         "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
0048     originalvalue = rtl_read_dword(rtlpriv, regaddr);
0049     bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
0050     returnvalue = (originalvalue & bitmask) >> bitshift;
0051 
0052     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0053         "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
0054         bitmask, regaddr, originalvalue);
0055 
0056     return returnvalue;
0057 }
0058 
0059 void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
0060                 u32 bitmask, u32 data)
0061 {
0062     struct rtl_priv *rtlpriv = rtl_priv(hw);
0063     u32 originalvalue, bitshift;
0064 
0065     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0066         "regaddr(%#x), bitmask(%#x), data(%#x)\n",
0067         regaddr, bitmask, data);
0068 
0069     if (bitmask != MASKDWORD) {
0070         originalvalue = rtl_read_dword(rtlpriv, regaddr);
0071         bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
0072         data = ((originalvalue & (~bitmask)) | (data << bitshift));
0073     }
0074 
0075     rtl_write_dword(rtlpriv, regaddr, data);
0076 
0077     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0078         "regaddr(%#x), bitmask(%#x), data(%#x)\n",
0079         regaddr, bitmask, data);
0080 }
0081 
0082 u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw,
0083                  enum radio_path rfpath, u32 regaddr, u32 bitmask)
0084 {
0085     struct rtl_priv *rtlpriv = rtl_priv(hw);
0086     u32 original_value, readback_value, bitshift;
0087 
0088     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0089         "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
0090         regaddr, rfpath, bitmask);
0091 
0092     spin_lock(&rtlpriv->locks.rf_lock);
0093 
0094     original_value = _rtl92ee_phy_rf_serial_read(hw , rfpath, regaddr);
0095     bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
0096     readback_value = (original_value & bitmask) >> bitshift;
0097 
0098     spin_unlock(&rtlpriv->locks.rf_lock);
0099 
0100     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0101         "regaddr(%#x),rfpath(%#x),bitmask(%#x),original_value(%#x)\n",
0102         regaddr, rfpath, bitmask, original_value);
0103 
0104     return readback_value;
0105 }
0106 
0107 void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw,
0108                 enum radio_path rfpath,
0109                 u32 addr, u32 bitmask, u32 data)
0110 {
0111     struct rtl_priv *rtlpriv = rtl_priv(hw);
0112     u32 original_value, bitshift;
0113 
0114     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0115         "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
0116         addr, bitmask, data, rfpath);
0117 
0118     spin_lock(&rtlpriv->locks.rf_lock);
0119 
0120     if (bitmask != RFREG_OFFSET_MASK) {
0121         original_value = _rtl92ee_phy_rf_serial_read(hw, rfpath, addr);
0122         bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
0123         data = (original_value & (~bitmask)) | (data << bitshift);
0124     }
0125 
0126     _rtl92ee_phy_rf_serial_write(hw, rfpath, addr, data);
0127 
0128     spin_unlock(&rtlpriv->locks.rf_lock);
0129 
0130     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0131         "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
0132         addr, bitmask, data, rfpath);
0133 }
0134 
0135 static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw,
0136                        enum radio_path rfpath, u32 offset)
0137 {
0138     struct rtl_priv *rtlpriv = rtl_priv(hw);
0139     struct rtl_phy *rtlphy = &rtlpriv->phy;
0140     struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
0141     u32 newoffset;
0142     u32 tmplong, tmplong2;
0143     u8 rfpi_enable = 0;
0144     u32 retvalue;
0145 
0146     offset &= 0xff;
0147     newoffset = offset;
0148     if (RT_CANNOT_IO(hw)) {
0149         pr_err("return all one\n");
0150         return 0xFFFFFFFF;
0151     }
0152     tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
0153     if (rfpath == RF90_PATH_A)
0154         tmplong2 = tmplong;
0155     else
0156         tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
0157     tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
0158            (newoffset << 23) | BLSSIREADEDGE;
0159     rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
0160               tmplong & (~BLSSIREADEDGE));
0161     rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
0162     udelay(20);
0163     if (rfpath == RF90_PATH_A)
0164         rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
0165                         BIT(8));
0166     else if (rfpath == RF90_PATH_B)
0167         rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
0168                         BIT(8));
0169     if (rfpi_enable)
0170         retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
0171                      BLSSIREADBACKDATA);
0172     else
0173         retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
0174                      BLSSIREADBACKDATA);
0175     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0176         "RFR-%d Addr[0x%x]=0x%x\n",
0177         rfpath, pphyreg->rf_rb, retvalue);
0178     return retvalue;
0179 }
0180 
0181 static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw,
0182                      enum radio_path rfpath, u32 offset,
0183                      u32 data)
0184 {
0185     u32 data_and_addr;
0186     u32 newoffset;
0187     struct rtl_priv *rtlpriv = rtl_priv(hw);
0188     struct rtl_phy *rtlphy = &rtlpriv->phy;
0189     struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
0190 
0191     if (RT_CANNOT_IO(hw)) {
0192         pr_err("stop\n");
0193         return;
0194     }
0195     offset &= 0xff;
0196     newoffset = offset;
0197     data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
0198     rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
0199     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0200         "RFW-%d Addr[0x%x]=0x%x\n", rfpath,
0201         pphyreg->rf3wire_offset, data_and_addr);
0202 }
0203 
0204 static u32 _rtl92ee_phy_calculate_bit_shift(u32 bitmask)
0205 {
0206     u32 i = ffs(bitmask);
0207 
0208     return i ? i - 1 : 32;
0209 }
0210 
0211 bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw)
0212 {
0213     return _rtl92ee_phy_config_mac_with_headerfile(hw);
0214 }
0215 
0216 bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw)
0217 {
0218     struct rtl_priv *rtlpriv = rtl_priv(hw);
0219     bool rtstatus = true;
0220     u16 regval;
0221     u32 tmp;
0222     u8 crystal_cap;
0223 
0224     phy_init_bb_rf_register_def(hw);
0225     regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
0226     rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
0227                regval | BIT(13) | BIT(0) | BIT(1));
0228 
0229     rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
0230     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
0231                FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
0232                FEN_BB_GLB_RSTN | FEN_BBRSTB);
0233 
0234     rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
0235 
0236     tmp = rtl_read_dword(rtlpriv, 0x4c);
0237     rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23));
0238 
0239     rtstatus = _rtl92ee_phy_bb8192ee_config_parafile(hw);
0240 
0241     crystal_cap = rtlpriv->efuse.eeprom_crystalcap & 0x3F;
0242     rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
0243               (crystal_cap | (crystal_cap << 6)));
0244     return rtstatus;
0245 }
0246 
0247 bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw)
0248 {
0249     return rtl92ee_phy_rf6052_config(hw);
0250 }
0251 
0252 static bool _check_condition(struct ieee80211_hw *hw,
0253                  const u32  condition)
0254 {
0255     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0256     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0257     u32 _board = rtlefuse->board_type; /*need efuse define*/
0258     u32 _interface = rtlhal->interface;
0259     u32 _platform = 0x08;/*SupportPlatform */
0260     u32 cond = condition;
0261 
0262     if (condition == 0xCDCDCDCD)
0263         return true;
0264 
0265     cond = condition & 0xFF;
0266     if ((_board != cond) && (cond != 0xFF))
0267         return false;
0268 
0269     cond = condition & 0xFF00;
0270     cond = cond >> 8;
0271     if ((_interface & cond) == 0 && cond != 0x07)
0272         return false;
0273 
0274     cond = condition & 0xFF0000;
0275     cond = cond >> 16;
0276     if ((_platform & cond) == 0 && cond != 0x0F)
0277         return false;
0278 
0279     return true;
0280 }
0281 
0282 static void _rtl92ee_config_rf_reg(struct ieee80211_hw *hw, u32 addr, u32 data,
0283                    enum radio_path rfpath, u32 regaddr)
0284 {
0285     if (addr == 0xfe || addr == 0xffe) {
0286         mdelay(50);
0287     } else {
0288         rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data);
0289         udelay(1);
0290 
0291         if (addr == 0xb6) {
0292             u32 getvalue;
0293             u8 count = 0;
0294 
0295             getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);
0296             udelay(1);
0297 
0298             while ((getvalue >> 8) != (data >> 8)) {
0299                 count++;
0300                 rtl_set_rfreg(hw, rfpath, regaddr,
0301                           RFREG_OFFSET_MASK, data);
0302                 udelay(1);
0303                 getvalue = rtl_get_rfreg(hw, rfpath, addr,
0304                              MASKDWORD);
0305                 if (count > 5)
0306                     break;
0307             }
0308         }
0309 
0310         if (addr == 0xb2) {
0311             u32 getvalue;
0312             u8 count = 0;
0313 
0314             getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);
0315             udelay(1);
0316 
0317             while (getvalue != data) {
0318                 count++;
0319                 rtl_set_rfreg(hw, rfpath, regaddr,
0320                           RFREG_OFFSET_MASK, data);
0321                 udelay(1);
0322                 rtl_set_rfreg(hw, rfpath, 0x18,
0323                           RFREG_OFFSET_MASK, 0x0fc07);
0324                 udelay(1);
0325                 getvalue = rtl_get_rfreg(hw, rfpath, addr,
0326                              MASKDWORD);
0327                 if (count > 5)
0328                     break;
0329             }
0330         }
0331     }
0332 }
0333 
0334 static void _rtl92ee_config_rf_radio_a(struct ieee80211_hw *hw,
0335                        u32 addr, u32 data)
0336 {
0337     u32 content = 0x1000; /*RF Content: radio_a_txt*/
0338     u32 maskforphyset = (u32)(content & 0xE000);
0339 
0340     _rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_A,
0341                    addr | maskforphyset);
0342 }
0343 
0344 static void _rtl92ee_config_rf_radio_b(struct ieee80211_hw *hw,
0345                        u32 addr, u32 data)
0346 {
0347     u32 content = 0x1001; /*RF Content: radio_b_txt*/
0348     u32 maskforphyset = (u32)(content & 0xE000);
0349 
0350     _rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_B,
0351                    addr | maskforphyset);
0352 }
0353 
0354 static void _rtl92ee_config_bb_reg(struct ieee80211_hw *hw,
0355                    u32 addr, u32 data)
0356 {
0357     if (addr == 0xfe)
0358         mdelay(50);
0359     else if (addr == 0xfd)
0360         mdelay(5);
0361     else if (addr == 0xfc)
0362         mdelay(1);
0363     else if (addr == 0xfb)
0364         udelay(50);
0365     else if (addr == 0xfa)
0366         udelay(5);
0367     else if (addr == 0xf9)
0368         udelay(1);
0369     else
0370         rtl_set_bbreg(hw, addr, MASKDWORD , data);
0371 
0372     udelay(1);
0373 }
0374 
0375 static void _rtl92ee_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
0376 {
0377     struct rtl_priv *rtlpriv = rtl_priv(hw);
0378     struct rtl_phy *rtlphy = &rtlpriv->phy;
0379 
0380     u8 band = BAND_ON_2_4G, rf = 0, txnum = 0, sec = 0;
0381 
0382     for (; band <= BAND_ON_5G; ++band)
0383         for (; rf < TX_PWR_BY_RATE_NUM_RF; ++rf)
0384             for (; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum)
0385                 for (; sec < TX_PWR_BY_RATE_NUM_SECTION; ++sec)
0386                     rtlphy->tx_power_by_rate_offset
0387                          [band][rf][txnum][sec] = 0;
0388 }
0389 
0390 static void _rtl92ee_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw,
0391                           u8 band, u8 path,
0392                           u8 rate_section, u8 txnum,
0393                           u8 value)
0394 {
0395     struct rtl_priv *rtlpriv = rtl_priv(hw);
0396     struct rtl_phy *rtlphy = &rtlpriv->phy;
0397 
0398     if (path > RF90_PATH_D) {
0399         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0400             "Invalid Rf Path %d\n", path);
0401         return;
0402     }
0403 
0404     if (band == BAND_ON_2_4G) {
0405         switch (rate_section) {
0406         case CCK:
0407             rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value;
0408             break;
0409         case OFDM:
0410             rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value;
0411             break;
0412         case HT_MCS0_MCS7:
0413             rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value;
0414             break;
0415         case HT_MCS8_MCS15:
0416             rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value;
0417             break;
0418         default:
0419             rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0420                 "Invalid RateSection %d in 2.4G,Rf %d,%dTx\n",
0421                 rate_section, path, txnum);
0422             break;
0423         }
0424     } else {
0425         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0426             "Invalid Band %d\n", band);
0427     }
0428 }
0429 
0430 static u8 _rtl92ee_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw,
0431                         u8 band, u8 path, u8 txnum,
0432                         u8 rate_section)
0433 {
0434     struct rtl_priv *rtlpriv = rtl_priv(hw);
0435     struct rtl_phy *rtlphy = &rtlpriv->phy;
0436     u8 value = 0;
0437 
0438     if (path > RF90_PATH_D) {
0439         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0440             "Invalid Rf Path %d\n", path);
0441         return 0;
0442     }
0443 
0444     if (band == BAND_ON_2_4G) {
0445         switch (rate_section) {
0446         case CCK:
0447             value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0];
0448             break;
0449         case OFDM:
0450             value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1];
0451             break;
0452         case HT_MCS0_MCS7:
0453             value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2];
0454             break;
0455         case HT_MCS8_MCS15:
0456             value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3];
0457             break;
0458         default:
0459             rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0460                 "Invalid RateSection %d in 2.4G,Rf %d,%dTx\n",
0461                 rate_section, path, txnum);
0462             break;
0463         }
0464     } else {
0465         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0466             "Invalid Band %d()\n", band);
0467     }
0468     return value;
0469 }
0470 
0471 static void _rtl92ee_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
0472 {
0473     struct rtl_priv *rtlpriv = rtl_priv(hw);
0474     struct rtl_phy *rtlphy = &rtlpriv->phy;
0475     u16 raw = 0;
0476     u8 base = 0, path = 0;
0477 
0478     for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
0479         if (path == RF90_PATH_A) {
0480             raw = (u16)(rtlphy->tx_power_by_rate_offset
0481                     [BAND_ON_2_4G][path][RF_1TX][3] >> 24) &
0482                     0xFF;
0483             base = (raw >> 4) * 10 + (raw & 0xF);
0484             _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
0485                                   path, CCK, RF_1TX,
0486                                   base);
0487         } else if (path == RF90_PATH_B) {
0488             raw = (u16)(rtlphy->tx_power_by_rate_offset
0489                     [BAND_ON_2_4G][path][RF_1TX][3] >> 0) &
0490                     0xFF;
0491             base = (raw >> 4) * 10 + (raw & 0xF);
0492             _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
0493                                   path, CCK, RF_1TX,
0494                                   base);
0495         }
0496         raw = (u16)(rtlphy->tx_power_by_rate_offset
0497                 [BAND_ON_2_4G][path][RF_1TX][1] >> 24) & 0xFF;
0498         base = (raw >> 4) * 10 + (raw & 0xF);
0499         _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path,
0500                               OFDM, RF_1TX, base);
0501 
0502         raw = (u16)(rtlphy->tx_power_by_rate_offset
0503                 [BAND_ON_2_4G][path][RF_1TX][5] >> 24) & 0xFF;
0504         base = (raw >> 4) * 10 + (raw & 0xF);
0505         _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path,
0506                               HT_MCS0_MCS7, RF_1TX,
0507                               base);
0508 
0509         raw = (u16)(rtlphy->tx_power_by_rate_offset
0510                 [BAND_ON_2_4G][path][RF_2TX][7] >> 24) & 0xFF;
0511         base = (raw >> 4) * 10 + (raw & 0xF);
0512         _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path,
0513                               HT_MCS8_MCS15, RF_2TX,
0514                               base);
0515     }
0516 }
0517 
0518 static void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start,
0519                                u8 end, u8 base)
0520 {
0521     s8 i = 0;
0522     u8 tmp = 0;
0523     u32 temp_data = 0;
0524 
0525     for (i = 3; i >= 0; --i) {
0526         if (i >= start && i <= end) {
0527             /* Get the exact value */
0528             tmp = (u8)(*data >> (i * 8)) & 0xF;
0529             tmp += ((u8)((*data >> (i * 8 + 4)) & 0xF)) * 10;
0530 
0531             /* Change the value to a relative value */
0532             tmp = (tmp > base) ? tmp - base : base - tmp;
0533         } else {
0534             tmp = (u8)(*data >> (i * 8)) & 0xFF;
0535         }
0536         temp_data <<= 8;
0537         temp_data |= tmp;
0538     }
0539     *data = temp_data;
0540 }
0541 
0542 static void phy_convert_txpwr_dbm_to_rel_val(struct ieee80211_hw *hw)
0543 {
0544     struct rtl_priv *rtlpriv = rtl_priv(hw);
0545     struct rtl_phy *rtlphy = &rtlpriv->phy;
0546     u8 base = 0, rf = 0, band = BAND_ON_2_4G;
0547 
0548     for (rf = RF90_PATH_A; rf <= RF90_PATH_B; ++rf) {
0549         if (rf == RF90_PATH_A) {
0550             base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band,
0551                                      rf, RF_1TX,
0552                                      CCK);
0553             _phy_convert_txpower_dbm_to_relative_value(
0554                 &rtlphy->tx_power_by_rate_offset
0555                 [band][rf][RF_1TX][2],
0556                 1, 1, base);
0557             _phy_convert_txpower_dbm_to_relative_value(
0558                 &rtlphy->tx_power_by_rate_offset
0559                 [band][rf][RF_1TX][3],
0560                 1, 3, base);
0561         } else if (rf == RF90_PATH_B) {
0562             base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band,
0563                                      rf, RF_1TX,
0564                                      CCK);
0565             _phy_convert_txpower_dbm_to_relative_value(
0566                 &rtlphy->tx_power_by_rate_offset
0567                 [band][rf][RF_1TX][3],
0568                 0, 0, base);
0569             _phy_convert_txpower_dbm_to_relative_value(
0570                 &rtlphy->tx_power_by_rate_offset
0571                 [band][rf][RF_1TX][2],
0572                 1, 3, base);
0573         }
0574         base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf,
0575                                  RF_1TX, OFDM);
0576         _phy_convert_txpower_dbm_to_relative_value(
0577             &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][0],
0578             0, 3, base);
0579         _phy_convert_txpower_dbm_to_relative_value(
0580             &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][1],
0581             0, 3, base);
0582 
0583         base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf,
0584                                  RF_1TX,
0585                                  HT_MCS0_MCS7);
0586         _phy_convert_txpower_dbm_to_relative_value(
0587             &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][4],
0588             0, 3, base);
0589         _phy_convert_txpower_dbm_to_relative_value(
0590             &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][5],
0591             0, 3, base);
0592 
0593         base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf,
0594                                  RF_2TX,
0595                                  HT_MCS8_MCS15);
0596         _phy_convert_txpower_dbm_to_relative_value(
0597             &rtlphy->tx_power_by_rate_offset[band][rf][RF_2TX][6],
0598             0, 3, base);
0599 
0600         _phy_convert_txpower_dbm_to_relative_value(
0601             &rtlphy->tx_power_by_rate_offset[band][rf][RF_2TX][7],
0602             0, 3, base);
0603     }
0604 
0605     rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
0606         "<==%s\n", __func__);
0607 }
0608 
0609 static void _rtl92ee_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw)
0610 {
0611     _rtl92ee_phy_store_txpower_by_rate_base(hw);
0612     phy_convert_txpwr_dbm_to_rel_val(hw);
0613 }
0614 
0615 static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw)
0616 {
0617     struct rtl_priv *rtlpriv = rtl_priv(hw);
0618     struct rtl_phy *rtlphy = &rtlpriv->phy;
0619     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0620     bool rtstatus;
0621 
0622     rtstatus = phy_config_bb_with_hdr_file(hw, BASEBAND_CONFIG_PHY_REG);
0623     if (!rtstatus) {
0624         pr_err("Write BB Reg Fail!!\n");
0625         return false;
0626     }
0627 
0628     _rtl92ee_phy_init_tx_power_by_rate(hw);
0629     if (!rtlefuse->autoload_failflag) {
0630         rtlphy->pwrgroup_cnt = 0;
0631         rtstatus =
0632           phy_config_bb_with_pghdrfile(hw, BASEBAND_CONFIG_PHY_REG);
0633     }
0634     _rtl92ee_phy_txpower_by_rate_configuration(hw);
0635     if (!rtstatus) {
0636         pr_err("BB_PG Reg Fail!!\n");
0637         return false;
0638     }
0639     rtstatus = phy_config_bb_with_hdr_file(hw, BASEBAND_CONFIG_AGC_TAB);
0640     if (!rtstatus) {
0641         pr_err("AGC Table Fail\n");
0642         return false;
0643     }
0644     rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw,
0645                               RFPGA0_XA_HSSIPARAMETER2,
0646                               0x200));
0647 
0648     return true;
0649 }
0650 
0651 static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
0652 {
0653     struct rtl_priv *rtlpriv = rtl_priv(hw);
0654     u32 i;
0655     u32 arraylength;
0656     u32 *ptrarray;
0657 
0658     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl8192EMACPHY_Array\n");
0659     arraylength = RTL8192EE_MAC_ARRAY_LEN;
0660     ptrarray = RTL8192EE_MAC_ARRAY;
0661     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0662         "Img:RTL8192EE_MAC_ARRAY LEN %d\n", arraylength);
0663     for (i = 0; i < arraylength; i = i + 2)
0664         rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
0665     return true;
0666 }
0667 
0668 #define READ_NEXT_PAIR(v1, v2, i) \
0669     do { \
0670         i += 2; \
0671         v1 = array[i]; \
0672         v2 = array[i+1]; \
0673     } while (0)
0674 
0675 static bool phy_config_bb_with_hdr_file(struct ieee80211_hw *hw,
0676                     u8 configtype)
0677 {
0678     int i;
0679     u32 *array;
0680     u16 len;
0681     struct rtl_priv *rtlpriv = rtl_priv(hw);
0682     u32 v1 = 0, v2 = 0;
0683 
0684     if (configtype == BASEBAND_CONFIG_PHY_REG) {
0685         len = RTL8192EE_PHY_REG_ARRAY_LEN;
0686         array = RTL8192EE_PHY_REG_ARRAY;
0687 
0688         for (i = 0; i < len; i = i + 2) {
0689             v1 = array[i];
0690             v2 = array[i+1];
0691             if (v1 < 0xcdcdcdcd) {
0692                 _rtl92ee_config_bb_reg(hw, v1, v2);
0693             } else {/*This line is the start line of branch.*/
0694                 /* to protect READ_NEXT_PAIR not overrun */
0695                 if (i >= len - 2)
0696                     break;
0697 
0698                 if (!_check_condition(hw , array[i])) {
0699                     /*Discard the following pairs*/
0700                     READ_NEXT_PAIR(v1, v2, i);
0701                     while (v2 != 0xDEAD &&
0702                            v2 != 0xCDEF &&
0703                            v2 != 0xCDCD && i < len - 2) {
0704                         READ_NEXT_PAIR(v1, v2, i);
0705                     }
0706                     i -= 2; /* prevent from for-loop += 2*/
0707                 } else {
0708                     /* Configure matched pairs and
0709                      * skip to end of if-else.
0710                      */
0711                     READ_NEXT_PAIR(v1, v2, i);
0712                     while (v2 != 0xDEAD &&
0713                            v2 != 0xCDEF &&
0714                            v2 != 0xCDCD && i < len - 2) {
0715                         _rtl92ee_config_bb_reg(hw, v1,
0716                                        v2);
0717                         READ_NEXT_PAIR(v1, v2, i);
0718                     }
0719 
0720                     while (v2 != 0xDEAD && i < len - 2)
0721                         READ_NEXT_PAIR(v1, v2, i);
0722                 }
0723             }
0724         }
0725     } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
0726         len = RTL8192EE_AGC_TAB_ARRAY_LEN;
0727         array = RTL8192EE_AGC_TAB_ARRAY;
0728 
0729         for (i = 0; i < len; i = i + 2) {
0730             v1 = array[i];
0731             v2 = array[i+1];
0732             if (v1 < 0xCDCDCDCD) {
0733                 rtl_set_bbreg(hw, array[i], MASKDWORD,
0734                           array[i + 1]);
0735                 udelay(1);
0736                 continue;
0737             } else{/*This line is the start line of branch.*/
0738               /* to protect READ_NEXT_PAIR not overrun */
0739                 if (i >= len - 2)
0740                     break;
0741 
0742                 if (!_check_condition(hw , array[i])) {
0743                     /*Discard the following pairs*/
0744                     READ_NEXT_PAIR(v1, v2, i);
0745                     while (v2 != 0xDEAD &&
0746                            v2 != 0xCDEF &&
0747                            v2 != 0xCDCD &&
0748                            i < len - 2) {
0749                         READ_NEXT_PAIR(v1, v2, i);
0750                     }
0751                     i -= 2; /* prevent from for-loop += 2*/
0752                 } else {
0753                     /* Configure matched pairs and
0754                      * skip to end of if-else.
0755                      */
0756                     READ_NEXT_PAIR(v1, v2, i);
0757                     while (v2 != 0xDEAD &&
0758                            v2 != 0xCDEF &&
0759                            v2 != 0xCDCD &&
0760                            i < len - 2) {
0761                         rtl_set_bbreg(hw,
0762                                   array[i],
0763                                   MASKDWORD,
0764                                   array[i + 1]);
0765                         udelay(1);
0766                         READ_NEXT_PAIR(v1 , v2 , i);
0767                     }
0768 
0769                     while (v2 != 0xDEAD &&
0770                            i < len - 2) {
0771                         READ_NEXT_PAIR(v1 , v2 , i);
0772                     }
0773                 }
0774             }
0775             rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0776                 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
0777                 array[i],
0778                 array[i + 1]);
0779         }
0780     }
0781     return true;
0782 }
0783 
0784 static u8 _rtl92ee_get_rate_section_index(u32 regaddr)
0785 {
0786     u8 index = 0;
0787 
0788     switch (regaddr) {
0789     case RTXAGC_A_RATE18_06:
0790     case RTXAGC_B_RATE18_06:
0791         index = 0;
0792         break;
0793     case RTXAGC_A_RATE54_24:
0794     case RTXAGC_B_RATE54_24:
0795         index = 1;
0796         break;
0797     case RTXAGC_A_CCK1_MCS32:
0798     case RTXAGC_B_CCK1_55_MCS32:
0799         index = 2;
0800         break;
0801     case RTXAGC_B_CCK11_A_CCK2_11:
0802         index = 3;
0803         break;
0804     case RTXAGC_A_MCS03_MCS00:
0805     case RTXAGC_B_MCS03_MCS00:
0806         index = 4;
0807         break;
0808     case RTXAGC_A_MCS07_MCS04:
0809     case RTXAGC_B_MCS07_MCS04:
0810         index = 5;
0811         break;
0812     case RTXAGC_A_MCS11_MCS08:
0813     case RTXAGC_B_MCS11_MCS08:
0814         index = 6;
0815         break;
0816     case RTXAGC_A_MCS15_MCS12:
0817     case RTXAGC_B_MCS15_MCS12:
0818         index = 7;
0819         break;
0820     default:
0821         regaddr &= 0xFFF;
0822         if (regaddr >= 0xC20 && regaddr <= 0xC4C)
0823             index = (u8)((regaddr - 0xC20) / 4);
0824         else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
0825             index = (u8)((regaddr - 0xE20) / 4);
0826         break;
0827     }
0828     return index;
0829 }
0830 
0831 static void _rtl92ee_store_tx_power_by_rate(struct ieee80211_hw *hw,
0832                         enum band_type band,
0833                         enum radio_path rfpath,
0834                         u32 txnum, u32 regaddr,
0835                         u32 bitmask, u32 data)
0836 {
0837     struct rtl_priv *rtlpriv = rtl_priv(hw);
0838     struct rtl_phy *rtlphy = &rtlpriv->phy;
0839     u8 section = _rtl92ee_get_rate_section_index(regaddr);
0840 
0841     if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
0842         rtl_dbg(rtlpriv, FPHY, PHY_TXPWR, "Invalid Band %d\n", band);
0843         return;
0844     }
0845 
0846     if (rfpath > MAX_RF_PATH - 1) {
0847         rtl_dbg(rtlpriv, FPHY, PHY_TXPWR,
0848             "Invalid RfPath %d\n", rfpath);
0849         return;
0850     }
0851     if (txnum > MAX_RF_PATH - 1) {
0852         rtl_dbg(rtlpriv, FPHY, PHY_TXPWR, "Invalid TxNum %d\n", txnum);
0853         return;
0854     }
0855 
0856     rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][section] = data;
0857 }
0858 
0859 static bool phy_config_bb_with_pghdrfile(struct ieee80211_hw *hw,
0860                      u8 configtype)
0861 {
0862     struct rtl_priv *rtlpriv = rtl_priv(hw);
0863     int i;
0864     u32 *phy_regarray_table_pg;
0865     u16 phy_regarray_pg_len;
0866     u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0;
0867 
0868     phy_regarray_pg_len = RTL8192EE_PHY_REG_ARRAY_PG_LEN;
0869     phy_regarray_table_pg = RTL8192EE_PHY_REG_ARRAY_PG;
0870 
0871     if (configtype == BASEBAND_CONFIG_PHY_REG) {
0872         for (i = 0; i < phy_regarray_pg_len; i = i + 6) {
0873             v1 = phy_regarray_table_pg[i];
0874             v2 = phy_regarray_table_pg[i+1];
0875             v3 = phy_regarray_table_pg[i+2];
0876             v4 = phy_regarray_table_pg[i+3];
0877             v5 = phy_regarray_table_pg[i+4];
0878             v6 = phy_regarray_table_pg[i+5];
0879 
0880             if (v1 < 0xcdcdcdcd) {
0881                 _rtl92ee_store_tx_power_by_rate(hw, v1, v2, v3,
0882                                 v4, v5, v6);
0883                 continue;
0884             }
0885         }
0886     } else {
0887         rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,
0888             "configtype != BaseBand_Config_PHY_REG\n");
0889     }
0890     return true;
0891 }
0892 
0893 #define READ_NEXT_RF_PAIR(v1, v2, i) \
0894     do { \
0895         i += 2; \
0896         v1 = array[i]; \
0897         v2 = array[i+1]; \
0898     } while (0)
0899 
0900 bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw  *hw,
0901                        enum radio_path rfpath)
0902 {
0903     struct rtl_priv *rtlpriv = rtl_priv(hw);
0904     int i;
0905     u32 *array;
0906     u16 len;
0907     u32 v1 = 0, v2 = 0;
0908 
0909     switch (rfpath) {
0910     case RF90_PATH_A:
0911         len = RTL8192EE_RADIOA_ARRAY_LEN;
0912         array = RTL8192EE_RADIOA_ARRAY;
0913         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0914             "Radio_A:RTL8192EE_RADIOA_ARRAY %d\n", len);
0915         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
0916         for (i = 0; i < len; i = i + 2) {
0917             v1 = array[i];
0918             v2 = array[i+1];
0919             if (v1 < 0xcdcdcdcd) {
0920                 _rtl92ee_config_rf_radio_a(hw, v1, v2);
0921                 continue;
0922             } else {/*This line is the start line of branch.*/
0923                 /* to protect READ_NEXT_PAIR not overrun */
0924                 if (i >= len - 2)
0925                     break;
0926 
0927                 if (!_check_condition(hw , array[i])) {
0928                     /*Discard the following pairs*/
0929                     READ_NEXT_RF_PAIR(v1, v2, i);
0930                     while (v2 != 0xDEAD &&
0931                            v2 != 0xCDEF &&
0932                            v2 != 0xCDCD && i < len - 2) {
0933                         READ_NEXT_RF_PAIR(v1, v2, i);
0934                     }
0935                     i -= 2; /* prevent from for-loop += 2*/
0936                 } else {
0937                     /* Configure matched pairs and
0938                      * skip to end of if-else.
0939                      */
0940                     READ_NEXT_RF_PAIR(v1, v2, i);
0941                     while (v2 != 0xDEAD &&
0942                            v2 != 0xCDEF &&
0943                            v2 != 0xCDCD && i < len - 2) {
0944                         _rtl92ee_config_rf_radio_a(hw,
0945                                        v1,
0946                                        v2);
0947                         READ_NEXT_RF_PAIR(v1, v2, i);
0948                     }
0949 
0950                     while (v2 != 0xDEAD && i < len - 2)
0951                         READ_NEXT_RF_PAIR(v1, v2, i);
0952                 }
0953             }
0954         }
0955         break;
0956 
0957     case RF90_PATH_B:
0958         len = RTL8192EE_RADIOB_ARRAY_LEN;
0959         array = RTL8192EE_RADIOB_ARRAY;
0960         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0961             "Radio_A:RTL8192EE_RADIOB_ARRAY %d\n", len);
0962         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
0963         for (i = 0; i < len; i = i + 2) {
0964             v1 = array[i];
0965             v2 = array[i+1];
0966             if (v1 < 0xcdcdcdcd) {
0967                 _rtl92ee_config_rf_radio_b(hw, v1, v2);
0968                 continue;
0969             } else {/*This line is the start line of branch.*/
0970                 /* to protect READ_NEXT_PAIR not overrun */
0971                 if (i >= len - 2)
0972                     break;
0973 
0974                 if (!_check_condition(hw , array[i])) {
0975                     /*Discard the following pairs*/
0976                     READ_NEXT_RF_PAIR(v1, v2, i);
0977                     while (v2 != 0xDEAD &&
0978                            v2 != 0xCDEF &&
0979                            v2 != 0xCDCD && i < len - 2) {
0980                         READ_NEXT_RF_PAIR(v1, v2, i);
0981                     }
0982                     i -= 2; /* prevent from for-loop += 2*/
0983                 } else {
0984                     /* Configure matched pairs and
0985                      * skip to end of if-else.
0986                      */
0987                     READ_NEXT_RF_PAIR(v1, v2, i);
0988                     while (v2 != 0xDEAD &&
0989                            v2 != 0xCDEF &&
0990                            v2 != 0xCDCD && i < len - 2) {
0991                         _rtl92ee_config_rf_radio_b(hw,
0992                                        v1,
0993                                        v2);
0994                         READ_NEXT_RF_PAIR(v1, v2, i);
0995                     }
0996 
0997                     while (v2 != 0xDEAD && i < len - 2)
0998                         READ_NEXT_RF_PAIR(v1, v2, i);
0999                 }
1000             }
1001         }
1002         break;
1003     case RF90_PATH_C:
1004     case RF90_PATH_D:
1005         break;
1006     }
1007     return true;
1008 }
1009 
1010 void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1011 {
1012     struct rtl_priv *rtlpriv = rtl_priv(hw);
1013     struct rtl_phy *rtlphy = &rtlpriv->phy;
1014 
1015     rtlphy->default_initialgain[0] =
1016         (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
1017     rtlphy->default_initialgain[1] =
1018         (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
1019     rtlphy->default_initialgain[2] =
1020         (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
1021     rtlphy->default_initialgain[3] =
1022         (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
1023 
1024     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1025         "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
1026         rtlphy->default_initialgain[0],
1027         rtlphy->default_initialgain[1],
1028         rtlphy->default_initialgain[2],
1029         rtlphy->default_initialgain[3]);
1030 
1031     rtlphy->framesync = (u8)rtl_get_bbreg(hw,
1032                           ROFDM0_RXDETECTOR3, MASKBYTE0);
1033     rtlphy->framesync_c34 = rtl_get_bbreg(hw,
1034                           ROFDM0_RXDETECTOR2, MASKDWORD);
1035 
1036     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1037         "Default framesync (0x%x) = 0x%x\n",
1038         ROFDM0_RXDETECTOR3, rtlphy->framesync);
1039 }
1040 
1041 static void phy_init_bb_rf_register_def(struct ieee80211_hw *hw)
1042 {
1043     struct rtl_priv *rtlpriv = rtl_priv(hw);
1044     struct rtl_phy *rtlphy = &rtlpriv->phy;
1045 
1046     rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
1047     rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
1048 
1049     rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
1050     rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
1051 
1052     rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
1053     rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
1054 
1055     rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
1056                             RFPGA0_XA_LSSIPARAMETER;
1057     rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
1058                             RFPGA0_XB_LSSIPARAMETER;
1059 
1060     rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
1061     rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
1062 
1063     rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
1064     rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
1065 
1066     rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
1067     rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
1068 }
1069 
1070 void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
1071 {
1072     struct rtl_priv *rtlpriv = rtl_priv(hw);
1073     struct rtl_phy *rtlphy = &rtlpriv->phy;
1074     u8 txpwr_level;
1075     long txpwr_dbm;
1076 
1077     txpwr_level = rtlphy->cur_cck_txpwridx;
1078     txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B,
1079                           txpwr_level);
1080     txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
1081     if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) >
1082         txpwr_dbm)
1083         txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
1084                               txpwr_level);
1085     txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
1086     if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
1087                       txpwr_level) > txpwr_dbm)
1088         txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw,
1089                               WIRELESS_MODE_N_24G,
1090                               txpwr_level);
1091     *powerlevel = txpwr_dbm;
1092 }
1093 
1094 static u8 _rtl92ee_phy_get_ratesection_intxpower_byrate(enum radio_path path,
1095                             u8 rate)
1096 {
1097     u8 rate_section = 0;
1098 
1099     switch (rate) {
1100     case DESC92C_RATE1M:
1101         rate_section = 2;
1102         break;
1103     case DESC92C_RATE2M:
1104     case DESC92C_RATE5_5M:
1105         if (path == RF90_PATH_A)
1106             rate_section = 3;
1107         else if (path == RF90_PATH_B)
1108             rate_section = 2;
1109         break;
1110     case DESC92C_RATE11M:
1111         rate_section = 3;
1112         break;
1113     case DESC92C_RATE6M:
1114     case DESC92C_RATE9M:
1115     case DESC92C_RATE12M:
1116     case DESC92C_RATE18M:
1117         rate_section = 0;
1118         break;
1119     case DESC92C_RATE24M:
1120     case DESC92C_RATE36M:
1121     case DESC92C_RATE48M:
1122     case DESC92C_RATE54M:
1123         rate_section = 1;
1124         break;
1125     case DESC92C_RATEMCS0:
1126     case DESC92C_RATEMCS1:
1127     case DESC92C_RATEMCS2:
1128     case DESC92C_RATEMCS3:
1129         rate_section = 4;
1130         break;
1131     case DESC92C_RATEMCS4:
1132     case DESC92C_RATEMCS5:
1133     case DESC92C_RATEMCS6:
1134     case DESC92C_RATEMCS7:
1135         rate_section = 5;
1136         break;
1137     case DESC92C_RATEMCS8:
1138     case DESC92C_RATEMCS9:
1139     case DESC92C_RATEMCS10:
1140     case DESC92C_RATEMCS11:
1141         rate_section = 6;
1142         break;
1143     case DESC92C_RATEMCS12:
1144     case DESC92C_RATEMCS13:
1145     case DESC92C_RATEMCS14:
1146     case DESC92C_RATEMCS15:
1147         rate_section = 7;
1148         break;
1149     default:
1150         WARN_ONCE(true, "rtl8192ee: Rate_Section is Illegal\n");
1151         break;
1152     }
1153     return rate_section;
1154 }
1155 
1156 static u8 _rtl92ee_get_txpower_by_rate(struct ieee80211_hw *hw,
1157                        enum band_type band,
1158                        enum radio_path rf, u8 rate)
1159 {
1160     struct rtl_priv *rtlpriv = rtl_priv(hw);
1161     struct rtl_phy *rtlphy = &rtlpriv->phy;
1162     u8 shift = 0, sec, tx_num;
1163     s8 diff = 0;
1164 
1165     sec = _rtl92ee_phy_get_ratesection_intxpower_byrate(rf, rate);
1166     tx_num = RF_TX_NUM_NONIMPLEMENT;
1167 
1168     if (tx_num == RF_TX_NUM_NONIMPLEMENT) {
1169         if ((rate >= DESC92C_RATEMCS8 && rate <= DESC92C_RATEMCS15))
1170             tx_num = RF_2TX;
1171         else
1172             tx_num = RF_1TX;
1173     }
1174 
1175     switch (rate) {
1176     case DESC92C_RATE1M:
1177     case DESC92C_RATE6M:
1178     case DESC92C_RATE24M:
1179     case DESC92C_RATEMCS0:
1180     case DESC92C_RATEMCS4:
1181     case DESC92C_RATEMCS8:
1182     case DESC92C_RATEMCS12:
1183         shift = 0;
1184         break;
1185     case DESC92C_RATE2M:
1186     case DESC92C_RATE9M:
1187     case DESC92C_RATE36M:
1188     case DESC92C_RATEMCS1:
1189     case DESC92C_RATEMCS5:
1190     case DESC92C_RATEMCS9:
1191     case DESC92C_RATEMCS13:
1192         shift = 8;
1193         break;
1194     case DESC92C_RATE5_5M:
1195     case DESC92C_RATE12M:
1196     case DESC92C_RATE48M:
1197     case DESC92C_RATEMCS2:
1198     case DESC92C_RATEMCS6:
1199     case DESC92C_RATEMCS10:
1200     case DESC92C_RATEMCS14:
1201         shift = 16;
1202         break;
1203     case DESC92C_RATE11M:
1204     case DESC92C_RATE18M:
1205     case DESC92C_RATE54M:
1206     case DESC92C_RATEMCS3:
1207     case DESC92C_RATEMCS7:
1208     case DESC92C_RATEMCS11:
1209     case DESC92C_RATEMCS15:
1210         shift = 24;
1211         break;
1212     default:
1213         WARN_ONCE(true, "rtl8192ee: Rate_Section is Illegal\n");
1214         break;
1215     }
1216 
1217     diff = (u8)(rtlphy->tx_power_by_rate_offset[band][rf][tx_num][sec] >>
1218             shift) & 0xff;
1219 
1220     return  diff;
1221 }
1222 
1223 static u8 _rtl92ee_get_txpower_index(struct ieee80211_hw *hw,
1224                      enum radio_path rfpath, u8 rate,
1225                      u8 bw, u8 channel)
1226 {
1227     struct rtl_priv *rtlpriv = rtl_priv(hw);
1228     struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
1229     u8 index = (channel - 1);
1230     u8 tx_power = 0;
1231     u8 diff = 0;
1232 
1233     if (channel < 1 || channel > 14) {
1234         index = 0;
1235         rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_DMESG,
1236             "Illegal channel!!\n");
1237     }
1238 
1239     if (IS_CCK_RATE((s8)rate))
1240         tx_power = rtlefuse->txpwrlevel_cck[rfpath][index];
1241     else if (DESC92C_RATE6M <= rate)
1242         tx_power = rtlefuse->txpwrlevel_ht40_1s[rfpath][index];
1243 
1244     /* OFDM-1T*/
1245     if (DESC92C_RATE6M <= rate && rate <= DESC92C_RATE54M &&
1246         !IS_CCK_RATE((s8)rate))
1247         tx_power += rtlefuse->txpwr_legacyhtdiff[rfpath][TX_1S];
1248 
1249     /* BW20-1S, BW20-2S */
1250     if (bw == HT_CHANNEL_WIDTH_20) {
1251         if (DESC92C_RATEMCS0 <= rate && rate <= DESC92C_RATEMCS15)
1252             tx_power += rtlefuse->txpwr_ht20diff[rfpath][TX_1S];
1253         if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15)
1254             tx_power += rtlefuse->txpwr_ht20diff[rfpath][TX_2S];
1255     } else if (bw == HT_CHANNEL_WIDTH_20_40) {/* BW40-1S, BW40-2S */
1256         if (DESC92C_RATEMCS0 <= rate && rate <= DESC92C_RATEMCS15)
1257             tx_power += rtlefuse->txpwr_ht40diff[rfpath][TX_1S];
1258         if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15)
1259             tx_power += rtlefuse->txpwr_ht40diff[rfpath][TX_2S];
1260     }
1261 
1262     if (rtlefuse->eeprom_regulatory != 2)
1263         diff = _rtl92ee_get_txpower_by_rate(hw, BAND_ON_2_4G,
1264                             rfpath, rate);
1265 
1266     tx_power += diff;
1267 
1268     if (tx_power > MAX_POWER_INDEX)
1269         tx_power = MAX_POWER_INDEX;
1270 
1271     return tx_power;
1272 }
1273 
1274 static void _rtl92ee_set_txpower_index(struct ieee80211_hw *hw, u8 pwr_idx,
1275                        enum radio_path rfpath, u8 rate)
1276 {
1277     struct rtl_priv *rtlpriv = rtl_priv(hw);
1278 
1279     if (rfpath == RF90_PATH_A) {
1280         switch (rate) {
1281         case DESC92C_RATE1M:
1282             rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1,
1283                       pwr_idx);
1284             break;
1285         case DESC92C_RATE2M:
1286             rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE1,
1287                       pwr_idx);
1288             break;
1289         case DESC92C_RATE5_5M:
1290             rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE2,
1291                       pwr_idx);
1292             break;
1293         case DESC92C_RATE11M:
1294             rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE3,
1295                       pwr_idx);
1296             break;
1297         case DESC92C_RATE6M:
1298             rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE0,
1299                       pwr_idx);
1300             break;
1301         case DESC92C_RATE9M:
1302             rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE1,
1303                       pwr_idx);
1304             break;
1305         case DESC92C_RATE12M:
1306             rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE2,
1307                       pwr_idx);
1308             break;
1309         case DESC92C_RATE18M:
1310             rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE3,
1311                       pwr_idx);
1312             break;
1313         case DESC92C_RATE24M:
1314             rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE0,
1315                       pwr_idx);
1316             break;
1317         case DESC92C_RATE36M:
1318             rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE1,
1319                       pwr_idx);
1320             break;
1321         case DESC92C_RATE48M:
1322             rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE2,
1323                       pwr_idx);
1324             break;
1325         case DESC92C_RATE54M:
1326             rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE3,
1327                       pwr_idx);
1328             break;
1329         case DESC92C_RATEMCS0:
1330             rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE0,
1331                       pwr_idx);
1332             break;
1333         case DESC92C_RATEMCS1:
1334             rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE1,
1335                       pwr_idx);
1336             break;
1337         case DESC92C_RATEMCS2:
1338             rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE2,
1339                       pwr_idx);
1340             break;
1341         case DESC92C_RATEMCS3:
1342             rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE3,
1343                       pwr_idx);
1344             break;
1345         case DESC92C_RATEMCS4:
1346             rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE0,
1347                       pwr_idx);
1348             break;
1349         case DESC92C_RATEMCS5:
1350             rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE1,
1351                       pwr_idx);
1352             break;
1353         case DESC92C_RATEMCS6:
1354             rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE2,
1355                       pwr_idx);
1356             break;
1357         case DESC92C_RATEMCS7:
1358             rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE3,
1359                       pwr_idx);
1360             break;
1361         case DESC92C_RATEMCS8:
1362             rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE0,
1363                       pwr_idx);
1364             break;
1365         case DESC92C_RATEMCS9:
1366             rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE1,
1367                       pwr_idx);
1368             break;
1369         case DESC92C_RATEMCS10:
1370             rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE2,
1371                       pwr_idx);
1372             break;
1373         case DESC92C_RATEMCS11:
1374             rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE3,
1375                       pwr_idx);
1376             break;
1377         case DESC92C_RATEMCS12:
1378             rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE0,
1379                       pwr_idx);
1380             break;
1381         case DESC92C_RATEMCS13:
1382             rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE1,
1383                       pwr_idx);
1384             break;
1385         case DESC92C_RATEMCS14:
1386             rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE2,
1387                       pwr_idx);
1388             break;
1389         case DESC92C_RATEMCS15:
1390             rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE3,
1391                       pwr_idx);
1392             break;
1393         default:
1394             rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1395                 "Invalid Rate!!\n");
1396             break;
1397         }
1398     } else if (rfpath == RF90_PATH_B) {
1399         switch (rate) {
1400         case DESC92C_RATE1M:
1401             rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE1,
1402                       pwr_idx);
1403             break;
1404         case DESC92C_RATE2M:
1405             rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE2,
1406                       pwr_idx);
1407             break;
1408         case DESC92C_RATE5_5M:
1409             rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE3,
1410                       pwr_idx);
1411             break;
1412         case DESC92C_RATE11M:
1413             rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0,
1414                       pwr_idx);
1415             break;
1416         case DESC92C_RATE6M:
1417             rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE0,
1418                       pwr_idx);
1419             break;
1420         case DESC92C_RATE9M:
1421             rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE1,
1422                       pwr_idx);
1423             break;
1424         case DESC92C_RATE12M:
1425             rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE2,
1426                       pwr_idx);
1427             break;
1428         case DESC92C_RATE18M:
1429             rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE3,
1430                       pwr_idx);
1431             break;
1432         case DESC92C_RATE24M:
1433             rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE0,
1434                       pwr_idx);
1435             break;
1436         case DESC92C_RATE36M:
1437             rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE1,
1438                       pwr_idx);
1439             break;
1440         case DESC92C_RATE48M:
1441             rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE2,
1442                       pwr_idx);
1443             break;
1444         case DESC92C_RATE54M:
1445             rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE3,
1446                       pwr_idx);
1447             break;
1448         case DESC92C_RATEMCS0:
1449             rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE0,
1450                       pwr_idx);
1451             break;
1452         case DESC92C_RATEMCS1:
1453             rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE1,
1454                       pwr_idx);
1455             break;
1456         case DESC92C_RATEMCS2:
1457             rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE2,
1458                       pwr_idx);
1459             break;
1460         case DESC92C_RATEMCS3:
1461             rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE3,
1462                       pwr_idx);
1463             break;
1464         case DESC92C_RATEMCS4:
1465             rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE0,
1466                       pwr_idx);
1467             break;
1468         case DESC92C_RATEMCS5:
1469             rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE1,
1470                       pwr_idx);
1471             break;
1472         case DESC92C_RATEMCS6:
1473             rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE2,
1474                       pwr_idx);
1475             break;
1476         case DESC92C_RATEMCS7:
1477             rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE3,
1478                       pwr_idx);
1479             break;
1480         case DESC92C_RATEMCS8:
1481             rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE0,
1482                       pwr_idx);
1483             break;
1484         case DESC92C_RATEMCS9:
1485             rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE1,
1486                       pwr_idx);
1487             break;
1488         case DESC92C_RATEMCS10:
1489             rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE2,
1490                       pwr_idx);
1491             break;
1492         case DESC92C_RATEMCS11:
1493             rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE3,
1494                       pwr_idx);
1495             break;
1496         case DESC92C_RATEMCS12:
1497             rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE0,
1498                       pwr_idx);
1499             break;
1500         case DESC92C_RATEMCS13:
1501             rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE1,
1502                       pwr_idx);
1503             break;
1504         case DESC92C_RATEMCS14:
1505             rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE2,
1506                       pwr_idx);
1507             break;
1508         case DESC92C_RATEMCS15:
1509             rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE3,
1510                       pwr_idx);
1511             break;
1512         default:
1513             rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1514                 "Invalid Rate!!\n");
1515             break;
1516         }
1517     } else {
1518         rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid RFPath!!\n");
1519     }
1520 }
1521 
1522 static void phy_set_txpower_index_by_rate_array(struct ieee80211_hw *hw,
1523                         enum radio_path rfpath, u8 bw,
1524                         u8 channel, u8 *rates, u8 size)
1525 {
1526     u8 i;
1527     u8 power_index;
1528 
1529     for (i = 0; i < size; i++) {
1530         power_index = _rtl92ee_get_txpower_index(hw, rfpath, rates[i],
1531                              bw, channel);
1532         _rtl92ee_set_txpower_index(hw, power_index, rfpath, rates[i]);
1533     }
1534 }
1535 
1536 static void phy_set_txpower_index_by_rate_section(struct ieee80211_hw *hw,
1537                           enum radio_path rfpath,
1538                           u8 channel,
1539                           enum rate_section section)
1540 {
1541     struct rtl_priv *rtlpriv = rtl_priv(hw);
1542     struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1543     struct rtl_phy *rtlphy = &rtlpriv->phy;
1544 
1545     if (section == CCK) {
1546         u8 cck_rates[] = {DESC92C_RATE1M, DESC92C_RATE2M,
1547                   DESC92C_RATE5_5M, DESC92C_RATE11M};
1548         if (rtlhal->current_bandtype == BAND_ON_2_4G)
1549             phy_set_txpower_index_by_rate_array(hw, rfpath,
1550                             rtlphy->current_chan_bw,
1551                             channel, cck_rates, 4);
1552     } else if (section == OFDM) {
1553         u8 ofdm_rates[] = {DESC92C_RATE6M, DESC92C_RATE9M,
1554                    DESC92C_RATE12M, DESC92C_RATE18M,
1555                    DESC92C_RATE24M, DESC92C_RATE36M,
1556                    DESC92C_RATE48M, DESC92C_RATE54M};
1557         phy_set_txpower_index_by_rate_array(hw, rfpath,
1558                             rtlphy->current_chan_bw,
1559                             channel, ofdm_rates, 8);
1560     } else if (section == HT_MCS0_MCS7) {
1561         u8 ht_rates1t[]  = {DESC92C_RATEMCS0, DESC92C_RATEMCS1,
1562                     DESC92C_RATEMCS2, DESC92C_RATEMCS3,
1563                     DESC92C_RATEMCS4, DESC92C_RATEMCS5,
1564                     DESC92C_RATEMCS6, DESC92C_RATEMCS7};
1565         phy_set_txpower_index_by_rate_array(hw, rfpath,
1566                             rtlphy->current_chan_bw,
1567                             channel, ht_rates1t, 8);
1568     } else if (section == HT_MCS8_MCS15) {
1569         u8 ht_rates2t[]  = {DESC92C_RATEMCS8, DESC92C_RATEMCS9,
1570                     DESC92C_RATEMCS10, DESC92C_RATEMCS11,
1571                     DESC92C_RATEMCS12, DESC92C_RATEMCS13,
1572                     DESC92C_RATEMCS14, DESC92C_RATEMCS15};
1573         phy_set_txpower_index_by_rate_array(hw, rfpath,
1574                             rtlphy->current_chan_bw,
1575                             channel, ht_rates2t, 8);
1576     } else
1577         rtl_dbg(rtlpriv, FPHY, PHY_TXPWR,
1578             "Invalid RateSection %d\n", section);
1579 }
1580 
1581 void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1582 {
1583     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1584     struct rtl_phy *rtlphy = &rtl_priv(hw)->phy;
1585     enum radio_path rfpath;
1586 
1587     if (!rtlefuse->txpwr_fromeprom)
1588         return;
1589     for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1590          rfpath++) {
1591         phy_set_txpower_index_by_rate_section(hw, rfpath,
1592                               channel, CCK);
1593         phy_set_txpower_index_by_rate_section(hw, rfpath,
1594                               channel, OFDM);
1595         phy_set_txpower_index_by_rate_section(hw, rfpath,
1596                               channel,
1597                               HT_MCS0_MCS7);
1598 
1599         if (rtlphy->num_total_rfpath >= 2)
1600             phy_set_txpower_index_by_rate_section(hw,
1601                                   rfpath, channel,
1602                                   HT_MCS8_MCS15);
1603     }
1604 }
1605 
1606 static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
1607                       enum wireless_mode wirelessmode,
1608                       u8 txpwridx)
1609 {
1610     long offset;
1611     long pwrout_dbm;
1612 
1613     switch (wirelessmode) {
1614     case WIRELESS_MODE_B:
1615         offset = -7;
1616         break;
1617     case WIRELESS_MODE_G:
1618     case WIRELESS_MODE_N_24G:
1619         offset = -8;
1620         break;
1621     default:
1622         offset = -8;
1623         break;
1624     }
1625     pwrout_dbm = txpwridx / 2 + offset;
1626     return pwrout_dbm;
1627 }
1628 
1629 void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1630 {
1631     struct rtl_priv *rtlpriv = rtl_priv(hw);
1632     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1633     enum io_type iotype;
1634 
1635     if (!is_hal_stop(rtlhal)) {
1636         switch (operation) {
1637         case SCAN_OPT_BACKUP_BAND0:
1638             iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
1639             rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1640                               (u8 *)&iotype);
1641 
1642             break;
1643         case SCAN_OPT_RESTORE:
1644             iotype = IO_CMD_RESUME_DM_BY_SCAN;
1645             rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1646                               (u8 *)&iotype);
1647             break;
1648         default:
1649             pr_err("Unknown Scan Backup operation.\n");
1650             break;
1651         }
1652     }
1653 }
1654 
1655 void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1656 {
1657     struct rtl_priv *rtlpriv = rtl_priv(hw);
1658     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1659     struct rtl_phy *rtlphy = &rtlpriv->phy;
1660     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1661     u8 reg_bw_opmode;
1662     u8 reg_prsr_rsc;
1663 
1664     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
1665         "Switch to %s bandwidth\n",
1666         rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1667         "20MHz" : "40MHz");
1668 
1669     if (is_hal_stop(rtlhal)) {
1670         rtlphy->set_bwmode_inprogress = false;
1671         return;
1672     }
1673 
1674     reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1675     reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1676 
1677     switch (rtlphy->current_chan_bw) {
1678     case HT_CHANNEL_WIDTH_20:
1679         reg_bw_opmode |= BW_OPMODE_20MHZ;
1680         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1681         break;
1682     case HT_CHANNEL_WIDTH_20_40:
1683         reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1684         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1685         reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
1686                    (mac->cur_40_prime_sc << 5);
1687         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1688         break;
1689     default:
1690         pr_err("unknown bandwidth: %#X\n",
1691                rtlphy->current_chan_bw);
1692         break;
1693     }
1694 
1695     switch (rtlphy->current_chan_bw) {
1696     case HT_CHANNEL_WIDTH_20:
1697         rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1698         rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1699         rtl_set_bbreg(hw, ROFDM0_TXPSEUDONOISEWGT,
1700                   (BIT(31) | BIT(30)), 0);
1701         break;
1702     case HT_CHANNEL_WIDTH_20_40:
1703         rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1704         rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1705         rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1706                   (mac->cur_40_prime_sc >> 1));
1707         rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00,
1708                   mac->cur_40_prime_sc);
1709 
1710         rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1711                   (mac->cur_40_prime_sc ==
1712                    HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1713         break;
1714     default:
1715         pr_err("unknown bandwidth: %#X\n",
1716                rtlphy->current_chan_bw);
1717         break;
1718     }
1719     rtl92ee_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1720     rtlphy->set_bwmode_inprogress = false;
1721     rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
1722 }
1723 
1724 void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw,
1725                  enum nl80211_channel_type ch_type)
1726 {
1727     struct rtl_priv *rtlpriv = rtl_priv(hw);
1728     struct rtl_phy *rtlphy = &rtlpriv->phy;
1729     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1730     u8 tmp_bw = rtlphy->current_chan_bw;
1731 
1732     if (rtlphy->set_bwmode_inprogress)
1733         return;
1734     rtlphy->set_bwmode_inprogress = true;
1735     if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1736         rtl92ee_phy_set_bw_mode_callback(hw);
1737     } else {
1738         rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1739             "false driver sleep or unload\n");
1740         rtlphy->set_bwmode_inprogress = false;
1741         rtlphy->current_chan_bw = tmp_bw;
1742     }
1743 }
1744 
1745 void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1746 {
1747     struct rtl_priv *rtlpriv = rtl_priv(hw);
1748     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1749     struct rtl_phy *rtlphy = &rtlpriv->phy;
1750     u32 delay;
1751 
1752     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
1753         "switch to channel%d\n", rtlphy->current_channel);
1754     if (is_hal_stop(rtlhal))
1755         return;
1756     do {
1757         if (!rtlphy->sw_chnl_inprogress)
1758             break;
1759         if (!_rtl92ee_phy_sw_chnl_step_by_step
1760             (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
1761              &rtlphy->sw_chnl_step, &delay)) {
1762             if (delay > 0)
1763                 mdelay(delay);
1764             else
1765                 continue;
1766         } else {
1767             rtlphy->sw_chnl_inprogress = false;
1768         }
1769         break;
1770     } while (true);
1771     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
1772 }
1773 
1774 u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw)
1775 {
1776     struct rtl_priv *rtlpriv = rtl_priv(hw);
1777     struct rtl_phy *rtlphy = &rtlpriv->phy;
1778     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1779 
1780     if (rtlphy->sw_chnl_inprogress)
1781         return 0;
1782     if (rtlphy->set_bwmode_inprogress)
1783         return 0;
1784     WARN_ONCE((rtlphy->current_channel > 14),
1785           "rtl8192ee: WIRELESS_MODE_G but channel>14");
1786     rtlphy->sw_chnl_inprogress = true;
1787     rtlphy->sw_chnl_stage = 0;
1788     rtlphy->sw_chnl_step = 0;
1789     if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1790         rtl92ee_phy_sw_chnl_callback(hw);
1791         rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
1792             "sw_chnl_inprogress false schedule workitem current channel %d\n",
1793             rtlphy->current_channel);
1794         rtlphy->sw_chnl_inprogress = false;
1795     } else {
1796         rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
1797             "sw_chnl_inprogress false driver sleep or unload\n");
1798         rtlphy->sw_chnl_inprogress = false;
1799     }
1800     return 1;
1801 }
1802 
1803 static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
1804                           u8 channel, u8 *stage, u8 *step,
1805                           u32 *delay)
1806 {
1807     struct rtl_priv *rtlpriv = rtl_priv(hw);
1808     struct rtl_phy *rtlphy = &rtlpriv->phy;
1809     struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
1810     u32 precommoncmdcnt;
1811     struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
1812     u32 postcommoncmdcnt;
1813     struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
1814     u32 rfdependcmdcnt;
1815     struct swchnlcmd *currentcmd = NULL;
1816     u8 rfpath;
1817     u8 num_total_rfpath = rtlphy->num_total_rfpath;
1818 
1819     precommoncmdcnt = 0;
1820     _rtl92ee_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1821                       MAX_PRECMD_CNT,
1822                       CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
1823     _rtl92ee_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1824                       MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1825 
1826     postcommoncmdcnt = 0;
1827 
1828     _rtl92ee_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1829                       MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
1830 
1831     rfdependcmdcnt = 0;
1832 
1833     WARN_ONCE((channel < 1 || channel > 14),
1834           "rtl8192ee: illegal channel for Zebra: %d\n", channel);
1835 
1836     _rtl92ee_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1837                       MAX_RFDEPENDCMD_CNT,
1838                       CMDID_RF_WRITEREG,
1839                       RF_CHNLBW, channel, 10);
1840 
1841     _rtl92ee_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1842                       MAX_RFDEPENDCMD_CNT, CMDID_END,
1843                       0, 0, 0);
1844 
1845     do {
1846         switch (*stage) {
1847         case 0:
1848             currentcmd = &precommoncmd[*step];
1849             break;
1850         case 1:
1851             currentcmd = &rfdependcmd[*step];
1852             break;
1853         case 2:
1854             currentcmd = &postcommoncmd[*step];
1855             break;
1856         default:
1857             pr_err("Invalid 'stage' = %d, Check it!\n",
1858                    *stage);
1859             return true;
1860         }
1861 
1862         if (currentcmd->cmdid == CMDID_END) {
1863             if ((*stage) == 2)
1864                 return true;
1865             (*stage)++;
1866             (*step) = 0;
1867             continue;
1868         }
1869 
1870         switch (currentcmd->cmdid) {
1871         case CMDID_SET_TXPOWEROWER_LEVEL:
1872             rtl92ee_phy_set_txpower_level(hw, channel);
1873             break;
1874         case CMDID_WRITEPORT_ULONG:
1875             rtl_write_dword(rtlpriv, currentcmd->para1,
1876                     currentcmd->para2);
1877             break;
1878         case CMDID_WRITEPORT_USHORT:
1879             rtl_write_word(rtlpriv, currentcmd->para1,
1880                        (u16)currentcmd->para2);
1881             break;
1882         case CMDID_WRITEPORT_UCHAR:
1883             rtl_write_byte(rtlpriv, currentcmd->para1,
1884                        (u8)currentcmd->para2);
1885             break;
1886         case CMDID_RF_WRITEREG:
1887             for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1888                 rtlphy->rfreg_chnlval[rfpath] =
1889                     ((rtlphy->rfreg_chnlval[rfpath] &
1890                       0xfffff00) | currentcmd->para2);
1891 
1892                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1893                           currentcmd->para1,
1894                           0x3ff,
1895                           rtlphy->rfreg_chnlval[rfpath]);
1896             }
1897             break;
1898         default:
1899             rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1900                 "switch case %#x not processed\n",
1901                 currentcmd->cmdid);
1902             break;
1903         }
1904 
1905         break;
1906     } while (true);
1907 
1908     (*delay) = currentcmd->msdelay;
1909     (*step)++;
1910     return false;
1911 }
1912 
1913 static bool _rtl92ee_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
1914                           u32 cmdtableidx, u32 cmdtablesz,
1915                           enum swchnlcmd_id cmdid,
1916                           u32 para1, u32 para2, u32 msdelay)
1917 {
1918     struct swchnlcmd *pcmd;
1919 
1920     if (cmdtable == NULL) {
1921         WARN_ONCE(true, "rtl8192ee: cmdtable cannot be NULL.\n");
1922         return false;
1923     }
1924 
1925     if (cmdtableidx >= cmdtablesz)
1926         return false;
1927 
1928     pcmd = cmdtable + cmdtableidx;
1929     pcmd->cmdid = cmdid;
1930     pcmd->para1 = para1;
1931     pcmd->para2 = para2;
1932     pcmd->msdelay = msdelay;
1933     return true;
1934 }
1935 
1936 static u8 _rtl92ee_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1937 {
1938     u32 reg_eac, reg_e94, reg_e9c;
1939     u8 result = 0x00;
1940     /* path-A IQK setting */
1941     /* PA/PAD controlled by 0x0 */
1942     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1943     rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);
1944     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1945 
1946     rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1947     rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1948     rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1949     rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1950 
1951     rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303);
1952     rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000);
1953 
1954     /*LO calibration setting*/
1955     rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
1956 
1957     /*One shot, path A LOK & IQK*/
1958     rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1959     rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1960 
1961     mdelay(IQK_DELAY_TIME);
1962 
1963     reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1964     reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1965     reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1966 
1967     if (!(reg_eac & BIT(28)) &&
1968         (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1969         (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1970         result |= 0x01;
1971     else
1972         return result;
1973 
1974     return result;
1975 }
1976 
1977 static u8 _rtl92ee_phy_path_b_iqk(struct ieee80211_hw *hw)
1978 {
1979     u32 reg_eac, reg_eb4, reg_ebc;
1980     u8 result = 0x00;
1981 
1982     /* PA/PAD controlled by 0x0 */
1983     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1984     rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);
1985     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1986 
1987     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1988     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1989 
1990     rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1991     rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1992     rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c);
1993     rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1994 
1995     rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2);
1996     rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000);
1997 
1998     /* LO calibration setting */
1999     rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
2000 
2001     /*One shot, path B LOK & IQK*/
2002     rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2003     rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2004 
2005     mdelay(IQK_DELAY_TIME);
2006 
2007     reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
2008     reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
2009     reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
2010 
2011     if (!(reg_eac & BIT(31)) &&
2012         (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
2013         (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
2014         result |= 0x01;
2015     else
2016         return result;
2017 
2018     return result;
2019 }
2020 
2021 static u8 _rtl92ee_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
2022 {
2023     u32 reg_eac, reg_e94, reg_e9c, reg_ea4 , u32temp;
2024     u8 result = 0x00;
2025 
2026     /*Get TXIMR Setting*/
2027     /*Modify RX IQK mode table*/
2028     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2029 
2030     rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2031     rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2032     rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2033     rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
2034 
2035     /*PA/PAD control by 0x56, and set = 0x0*/
2036     rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980);
2037     rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000);
2038 
2039     /*enter IQK mode*/
2040     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2041 
2042     /*IQK Setting*/
2043     rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
2044     rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2045 
2046     /*path a IQK setting*/
2047     rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
2048     rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2049     rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2050     rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2051 
2052     rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f);
2053     rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f);
2054 
2055     /*LO calibration Setting*/
2056     rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
2057 
2058     /*one shot,path A LOK & iqk*/
2059     rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2060     rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2061 
2062     mdelay(IQK_DELAY_TIME);
2063 
2064     /* Check failed */
2065     reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
2066     reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
2067     reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
2068 
2069     if (!(reg_eac & BIT(28)) &&
2070         (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
2071         (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) {
2072         result |= 0x01;
2073     } else {
2074         /*  PA/PAD controlled by 0x0 */
2075         rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2076         rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);
2077         return result;
2078     }
2079 
2080     u32temp = 0x80007C00 | (reg_e94 & 0x3FF0000)  |
2081           ((reg_e9c & 0x3FF0000) >> 16);
2082     rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);
2083     /*RX IQK*/
2084     /*Modify RX IQK mode table*/
2085     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2086 
2087     rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2088 
2089     rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2090     rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2091     rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
2092 
2093     /*PA/PAD control by 0x56, and set = 0x0*/
2094     rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980);
2095     rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000);
2096 
2097     /*enter IQK mode*/
2098     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2099 
2100     /*IQK Setting*/
2101     rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2102 
2103     /*path a IQK setting*/
2104     rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2105     rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
2106     rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2107     rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2108 
2109     rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f);
2110     rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f);
2111 
2112     /*LO calibration Setting*/
2113     rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891);
2114     /*one shot,path A LOK & iqk*/
2115     rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2116     rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2117 
2118     mdelay(IQK_DELAY_TIME);
2119     /*Check failed*/
2120     reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
2121     reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
2122 
2123     /*PA/PAD controlled by 0x0*/
2124     /*leave IQK mode*/
2125     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2126     rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);
2127     /*if Tx is OK, check whether Rx is OK*/
2128     if (!(reg_eac & BIT(27)) &&
2129         (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
2130         (((reg_eac & 0x03FF0000) >> 16) != 0x36))
2131         result |= 0x02;
2132 
2133     return result;
2134 }
2135 
2136 static u8 _rtl92ee_phy_path_b_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
2137 {
2138     struct rtl_priv *rtlpriv = rtl_priv(hw);
2139     u32 reg_eac, reg_eb4, reg_ebc, reg_ecc, reg_ec4, u32temp;
2140     u8 result = 0x00;
2141 
2142     /*Get TXIMR Setting*/
2143     /*Modify RX IQK mode table*/
2144     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2145 
2146     rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2147     rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2148     rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2149     rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
2150 
2151     /*PA/PAD all off*/
2152     rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980);
2153     rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000);
2154 
2155     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2156 
2157     /*IQK Setting*/
2158     rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
2159     rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2160 
2161     /*path a IQK setting*/
2162     rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2163     rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2164     rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c);
2165     rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2166 
2167     rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f);
2168     rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f);
2169 
2170     /*LO calibration Setting*/
2171     rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
2172 
2173     /*one shot,path A LOK & iqk*/
2174     rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2175     rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2176 
2177     mdelay(IQK_DELAY_TIME);
2178 
2179     /* Check failed */
2180     reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
2181     reg_eb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD);
2182     reg_ebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD);
2183 
2184     if (!(reg_eac & BIT(31)) &&
2185         (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
2186         (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) {
2187         result |= 0x01;
2188     } else {
2189         /*  PA/PAD controlled by 0x0 */
2190         rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2191         rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);
2192         return result;
2193     }
2194 
2195     u32temp = 0x80007C00 | (reg_eb4 & 0x3FF0000) |
2196           ((reg_ebc & 0x3FF0000) >> 16);
2197     rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);
2198     /*RX IQK*/
2199     /*Modify RX IQK mode table*/
2200     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2201     rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2202 
2203     rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2204     rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2205     rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
2206 
2207     /*PA/PAD all off*/
2208     rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980);
2209     rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000);
2210 
2211     /*enter IQK mode*/
2212     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2213 
2214     /*IQK Setting*/
2215     rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2216 
2217     /*path b IQK setting*/
2218     rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2219     rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2220     rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2221     rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c);
2222 
2223     rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f);
2224     rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f);
2225 
2226     /*LO calibration Setting*/
2227     rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891);
2228     /*one shot,path A LOK & iqk*/
2229     rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2230     rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2231 
2232     mdelay(IQK_DELAY_TIME);
2233     /*Check failed*/
2234     reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
2235     reg_ec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD);
2236     reg_ecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD);
2237     /*PA/PAD controlled by 0x0*/
2238     /*leave IQK mode*/
2239     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2240     rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);
2241     /*if Tx is OK, check whether Rx is OK*/
2242     if (!(reg_eac & BIT(30)) &&
2243         (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
2244         (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
2245         result |= 0x02;
2246     else
2247         rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "Path B Rx IQK fail!!\n");
2248 
2249     return result;
2250 }
2251 
2252 static void _rtl92ee_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
2253                         bool b_iqk_ok, long result[][8],
2254                         u8 final_candidate,
2255                         bool btxonly)
2256 {
2257     u32 oldval_0, x, tx0_a, reg;
2258     long y, tx0_c;
2259 
2260     if (final_candidate == 0xFF) {
2261         return;
2262     } else if (b_iqk_ok) {
2263         oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2264                       MASKDWORD) >> 22) & 0x3FF;
2265         x = result[final_candidate][0];
2266         if ((x & 0x00000200) != 0)
2267             x = x | 0xFFFFFC00;
2268         tx0_a = (x * oldval_0) >> 8;
2269         rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
2270         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
2271                   ((x * oldval_0 >> 7) & 0x1));
2272         y = result[final_candidate][1];
2273         if ((y & 0x00000200) != 0)
2274             y = y | 0xFFFFFC00;
2275         tx0_c = (y * oldval_0) >> 8;
2276         rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
2277                   ((tx0_c & 0x3C0) >> 6));
2278         rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
2279                   (tx0_c & 0x3F));
2280         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
2281                   ((y * oldval_0 >> 7) & 0x1));
2282 
2283         if (btxonly)
2284             return;
2285 
2286         reg = result[final_candidate][2];
2287         rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2288 
2289         reg = result[final_candidate][3] & 0x3F;
2290         rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2291 
2292         reg = (result[final_candidate][3] >> 6) & 0xF;
2293         rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg);
2294     }
2295 }
2296 
2297 static void _rtl92ee_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
2298                         bool b_iqk_ok, long result[][8],
2299                         u8 final_candidate,
2300                         bool btxonly)
2301 {
2302     u32 oldval_1, x, tx1_a, reg;
2303     long y, tx1_c;
2304 
2305     if (final_candidate == 0xFF) {
2306         return;
2307     } else if (b_iqk_ok) {
2308         oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2309                       MASKDWORD) >> 22) & 0x3FF;
2310         x = result[final_candidate][4];
2311         if ((x & 0x00000200) != 0)
2312             x = x | 0xFFFFFC00;
2313         tx1_a = (x * oldval_1) >> 8;
2314         rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx1_a);
2315         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
2316                   ((x * oldval_1 >> 7) & 0x1));
2317         y = result[final_candidate][5];
2318         if ((y & 0x00000200) != 0)
2319             y = y | 0xFFFFFC00;
2320         tx1_c = (y * oldval_1) >> 8;
2321         rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
2322                   ((tx1_c & 0x3C0) >> 6));
2323         rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
2324                   (tx1_c & 0x3F));
2325         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
2326                   ((y * oldval_1 >> 7) & 0x1));
2327 
2328         if (btxonly)
2329             return;
2330 
2331         reg = result[final_candidate][6];
2332         rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2333 
2334         reg = result[final_candidate][7] & 0x3F;
2335         rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2336 
2337         reg = (result[final_candidate][7] >> 6) & 0xF;
2338         rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0xF0000000, reg);
2339     }
2340 }
2341 
2342 static void _rtl92ee_phy_save_adda_registers(struct ieee80211_hw *hw,
2343                          u32 *addareg, u32 *addabackup,
2344                          u32 registernum)
2345 {
2346     u32 i;
2347 
2348     for (i = 0; i < registernum; i++)
2349         addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
2350 }
2351 
2352 static void _rtl92ee_phy_save_mac_registers(struct ieee80211_hw *hw,
2353                         u32 *macreg, u32 *macbackup)
2354 {
2355     struct rtl_priv *rtlpriv = rtl_priv(hw);
2356     u32 i;
2357 
2358     for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
2359         macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
2360 
2361     macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
2362 }
2363 
2364 static void _rtl92ee_phy_reload_adda_registers(struct ieee80211_hw *hw,
2365                            u32 *addareg, u32 *addabackup,
2366                            u32 regiesternum)
2367 {
2368     u32 i;
2369 
2370     for (i = 0; i < regiesternum; i++)
2371         rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
2372 }
2373 
2374 static void _rtl92ee_phy_reload_mac_registers(struct ieee80211_hw *hw,
2375                           u32 *macreg, u32 *macbackup)
2376 {
2377     struct rtl_priv *rtlpriv = rtl_priv(hw);
2378     u32 i;
2379 
2380     for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
2381         rtl_write_byte(rtlpriv, macreg[i], (u8)macbackup[i]);
2382     rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
2383 }
2384 
2385 static void _rtl92ee_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg,
2386                       bool is_patha_on, bool is2t)
2387 {
2388     u32 i;
2389 
2390     for (i = 0; i < IQK_ADDA_REG_NUM; i++)
2391         rtl_set_bbreg(hw, addareg[i], MASKDWORD, 0x0fc01616);
2392 }
2393 
2394 static void _rtl92ee_phy_mac_setting_calibration(struct ieee80211_hw *hw,
2395                          u32 *macreg, u32 *macbackup)
2396 {
2397     rtl_set_bbreg(hw, 0x520, 0x00ff0000, 0xff);
2398 }
2399 
2400 static void _rtl92ee_phy_path_a_standby(struct ieee80211_hw *hw)
2401 {
2402     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
2403     rtl_set_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK, 0x10000);
2404     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
2405 }
2406 
2407 static bool _rtl92ee_phy_simularity_compare(struct ieee80211_hw *hw,
2408                         long result[][8], u8 c1, u8 c2)
2409 {
2410     u32 i, j, diff, simularity_bitmap, bound;
2411 
2412     u8 final_candidate[2] = { 0xFF, 0xFF };
2413     bool bresult = true/*, is2t = true*/;
2414     s32 tmp1, tmp2;
2415 
2416     bound = 8;
2417 
2418     simularity_bitmap = 0;
2419 
2420     for (i = 0; i < bound; i++) {
2421         if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
2422             if ((result[c1][i] & 0x00000200) != 0)
2423                 tmp1 = result[c1][i] | 0xFFFFFC00;
2424             else
2425                 tmp1 = result[c1][i];
2426 
2427             if ((result[c2][i] & 0x00000200) != 0)
2428                 tmp2 = result[c2][i] | 0xFFFFFC00;
2429             else
2430                 tmp2 = result[c2][i];
2431         } else {
2432             tmp1 = result[c1][i];
2433             tmp2 = result[c2][i];
2434         }
2435 
2436         diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2437 
2438         if (diff > MAX_TOLERANCE) {
2439             if ((i == 2 || i == 6) && !simularity_bitmap) {
2440                 if (result[c1][i] + result[c1][i + 1] == 0)
2441                     final_candidate[(i / 4)] = c2;
2442                 else if (result[c2][i] + result[c2][i + 1] == 0)
2443                     final_candidate[(i / 4)] = c1;
2444                 else
2445                     simularity_bitmap |= (1 << i);
2446             } else {
2447                 simularity_bitmap |= (1 << i);
2448             }
2449         }
2450     }
2451 
2452     if (simularity_bitmap == 0) {
2453         for (i = 0; i < (bound / 4); i++) {
2454             if (final_candidate[i] != 0xFF) {
2455                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2456                     result[3][j] =
2457                         result[final_candidate[i]][j];
2458                 bresult = false;
2459             }
2460         }
2461         return bresult;
2462     }
2463     if (!(simularity_bitmap & 0x03)) {/*path A TX OK*/
2464         for (i = 0; i < 2; i++)
2465             result[3][i] = result[c1][i];
2466     }
2467     if (!(simularity_bitmap & 0x0c)) {/*path A RX OK*/
2468         for (i = 2; i < 4; i++)
2469             result[3][i] = result[c1][i];
2470     }
2471     if (!(simularity_bitmap & 0x30)) {/*path B TX OK*/
2472         for (i = 4; i < 6; i++)
2473             result[3][i] = result[c1][i];
2474     }
2475     if (!(simularity_bitmap & 0xc0)) {/*path B RX OK*/
2476         for (i = 6; i < 8; i++)
2477             result[3][i] = result[c1][i];
2478     }
2479     return false;
2480 }
2481 
2482 static void _rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw,
2483                       long result[][8], u8 t, bool is2t)
2484 {
2485     struct rtl_priv *rtlpriv = rtl_priv(hw);
2486     struct rtl_phy *rtlphy = &rtlpriv->phy;
2487     u32 i;
2488     u8 patha_ok, pathb_ok;
2489     u8 tmp_0xc50 = (u8)rtl_get_bbreg(hw, 0xc50, MASKBYTE0);
2490     u8 tmp_0xc58 = (u8)rtl_get_bbreg(hw, 0xc58, MASKBYTE0);
2491     u32 adda_reg[IQK_ADDA_REG_NUM] = {
2492         0x85c, 0xe6c, 0xe70, 0xe74,
2493         0xe78, 0xe7c, 0xe80, 0xe84,
2494         0xe88, 0xe8c, 0xed0, 0xed4,
2495         0xed8, 0xedc, 0xee0, 0xeec
2496     };
2497     u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2498         0x522, 0x550, 0x551, 0x040
2499     };
2500     u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2501         ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR,
2502         RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c,
2503         0x870, 0x860,
2504         0x864, 0x800
2505     };
2506     const u32 retrycount = 2;
2507 
2508     if (t == 0) {
2509         _rtl92ee_phy_save_adda_registers(hw, adda_reg,
2510                          rtlphy->adda_backup,
2511                          IQK_ADDA_REG_NUM);
2512         _rtl92ee_phy_save_mac_registers(hw, iqk_mac_reg,
2513                         rtlphy->iqk_mac_backup);
2514         _rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg,
2515                          rtlphy->iqk_bb_backup,
2516                          IQK_BB_REG_NUM);
2517     }
2518 
2519     _rtl92ee_phy_path_adda_on(hw, adda_reg, true, is2t);
2520 
2521     /*BB setting*/
2522     rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2523     rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
2524     rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
2525     rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200);
2526 
2527     rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(10), 0x01);
2528     rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(26), 0x01);
2529     rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 0x01);
2530     rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 0x01);
2531 
2532     _rtl92ee_phy_mac_setting_calibration(hw, iqk_mac_reg,
2533                          rtlphy->iqk_mac_backup);
2534     /* Page B init*/
2535     /* IQ calibration setting*/
2536     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2537     rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
2538     rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2539 
2540     for (i = 0 ; i < retrycount ; i++) {
2541         patha_ok = _rtl92ee_phy_path_a_iqk(hw, is2t);
2542 
2543         if (patha_ok == 0x01) {
2544             rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
2545                 "Path A Tx IQK Success!!\n");
2546             result[t][0] = (rtl_get_bbreg(hw,
2547                               RTX_POWER_BEFORE_IQK_A,
2548                               MASKDWORD) & 0x3FF0000)
2549                               >> 16;
2550             result[t][1] = (rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A,
2551                               MASKDWORD) & 0x3FF0000)
2552                               >> 16;
2553             break;
2554         }
2555         rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
2556             "Path A Tx IQK Fail!!, ret = 0x%x\n",
2557             patha_ok);
2558     }
2559 
2560     for (i = 0 ; i < retrycount ; i++) {
2561         patha_ok = _rtl92ee_phy_path_a_rx_iqk(hw, is2t);
2562 
2563         if (patha_ok == 0x03) {
2564             rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
2565                 "Path A Rx IQK Success!!\n");
2566             result[t][2] = (rtl_get_bbreg(hw,
2567                               RRX_POWER_BEFORE_IQK_A_2,
2568                               MASKDWORD) & 0x3FF0000)
2569                               >> 16;
2570             result[t][3] = (rtl_get_bbreg(hw,
2571                               RRX_POWER_AFTER_IQK_A_2,
2572                               MASKDWORD) & 0x3FF0000)
2573                               >> 16;
2574             break;
2575         }
2576         rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
2577             "Path A Rx IQK Fail!!, ret = 0x%x\n",
2578             patha_ok);
2579     }
2580 
2581     if (0x00 == patha_ok)
2582         rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
2583             "Path A IQK failed!!, ret = 0\n");
2584     if (is2t) {
2585         _rtl92ee_phy_path_a_standby(hw);
2586         /* Turn Path B ADDA on */
2587         _rtl92ee_phy_path_adda_on(hw, adda_reg, false, is2t);
2588 
2589         /* IQ calibration setting */
2590         rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2591         rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
2592         rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2593 
2594         for (i = 0 ; i < retrycount ; i++) {
2595             pathb_ok = _rtl92ee_phy_path_b_iqk(hw);
2596             if (pathb_ok == 0x01) {
2597                 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
2598                     "Path B Tx IQK Success!!\n");
2599                 result[t][4] = (rtl_get_bbreg(hw,
2600                             RTX_POWER_BEFORE_IQK_B,
2601                             MASKDWORD) & 0x3FF0000)
2602                             >> 16;
2603                 result[t][5] = (rtl_get_bbreg(hw,
2604                             RTX_POWER_AFTER_IQK_B,
2605                             MASKDWORD) & 0x3FF0000)
2606                             >> 16;
2607                 break;
2608             }
2609             rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
2610                 "Path B Tx IQK Fail!!, ret = 0x%x\n",
2611                 pathb_ok);
2612         }
2613 
2614         for (i = 0 ; i < retrycount ; i++) {
2615             pathb_ok = _rtl92ee_phy_path_b_rx_iqk(hw, is2t);
2616             if (pathb_ok == 0x03) {
2617                 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
2618                     "Path B Rx IQK Success!!\n");
2619                 result[t][6] = (rtl_get_bbreg(hw,
2620                                RRX_POWER_BEFORE_IQK_B_2,
2621                                MASKDWORD) & 0x3FF0000)
2622                                >> 16;
2623                 result[t][7] = (rtl_get_bbreg(hw,
2624                                RRX_POWER_AFTER_IQK_B_2,
2625                                MASKDWORD) & 0x3FF0000)
2626                                >> 16;
2627                 break;
2628             }
2629             rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
2630                 "Path B Rx IQK Fail!!, ret = 0x%x\n",
2631                 pathb_ok);
2632         }
2633 
2634         if (0x00 == pathb_ok)
2635             rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
2636                 "Path B IQK failed!!, ret = 0\n");
2637     }
2638     /* Back to BB mode, load original value */
2639     rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
2640         "IQK:Back to BB mode, load original value!\n");
2641     rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);
2642 
2643     if (t != 0) {
2644         /* Reload ADDA power saving parameters */
2645         _rtl92ee_phy_reload_adda_registers(hw, adda_reg,
2646                            rtlphy->adda_backup,
2647                            IQK_ADDA_REG_NUM);
2648 
2649         /* Reload MAC parameters */
2650         _rtl92ee_phy_reload_mac_registers(hw, iqk_mac_reg,
2651                           rtlphy->iqk_mac_backup);
2652 
2653         _rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg,
2654                            rtlphy->iqk_bb_backup,
2655                            IQK_BB_REG_NUM);
2656 
2657         /* Restore RX initial gain */
2658         rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50);
2659         rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_0xc50);
2660         if (is2t) {
2661             rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50);
2662             rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_0xc58);
2663         }
2664 
2665         /* load 0xe30 IQC default value */
2666         rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00);
2667         rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00);
2668     }
2669 }
2670 
2671 static void _rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2672 {
2673     u8 tmpreg;
2674     u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
2675     struct rtl_priv *rtlpriv = rtl_priv(hw);
2676 
2677     tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2678 
2679     if ((tmpreg & 0x70) != 0)
2680         rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2681     else
2682         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2683 
2684     if ((tmpreg & 0x70) != 0) {
2685         rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
2686 
2687         if (is2t)
2688             rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
2689                           MASK12BITS);
2690 
2691         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
2692                   (rf_a_mode & 0x8FFFF) | 0x10000);
2693 
2694         if (is2t)
2695             rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
2696                       (rf_b_mode & 0x8FFFF) | 0x10000);
2697     }
2698     lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
2699 
2700     rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
2701 
2702     mdelay(100);
2703 
2704     if ((tmpreg & 0x70) != 0) {
2705         rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2706         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
2707 
2708         if (is2t)
2709             rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
2710                       rf_b_mode);
2711     } else {
2712         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2713     }
2714 }
2715 
2716 static void _rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw,
2717                        bool bmain, bool is2t)
2718 {
2719     struct rtl_priv *rtlpriv = rtl_priv(hw);
2720     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2721     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2722 
2723     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
2724 
2725     if (is_hal_stop(rtlhal)) {
2726         u8 u1btmp;
2727 
2728         u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0);
2729         rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7));
2730         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
2731     }
2732     if (is2t) {
2733         if (bmain)
2734             rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2735                       BIT(5) | BIT(6), 0x1);
2736         else
2737             rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2738                       BIT(5) | BIT(6), 0x2);
2739     } else {
2740         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0);
2741         rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201);
2742 
2743         /* We use the RF definition of MAIN and AUX,
2744          * left antenna and right antenna repectively.
2745          * Default output at AUX.
2746          */
2747         if (bmain) {
2748             rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
2749                       BIT(14) | BIT(13) | BIT(12), 0);
2750             rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2751                       BIT(5) | BIT(4) | BIT(3), 0);
2752             if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
2753                 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0);
2754         } else {
2755             rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
2756                       BIT(14) | BIT(13) | BIT(12), 1);
2757             rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2758                       BIT(5) | BIT(4) | BIT(3), 1);
2759             if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
2760                 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1);
2761         }
2762     }
2763 }
2764 
2765 #undef IQK_ADDA_REG_NUM
2766 #undef IQK_DELAY_TIME
2767 
2768 static u8 rtl92ee_get_rightchnlplace_for_iqk(u8 chnl)
2769 {
2770     u8 channel_all[59] = {
2771         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
2772         36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
2773         60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
2774         114, 116, 118, 120, 122, 124, 126, 128, 130,
2775         132, 134, 136, 138, 140, 149, 151, 153, 155,
2776         157, 159, 161, 163, 165
2777     };
2778     u8 place = chnl;
2779 
2780     if (chnl > 14) {
2781         for (place = 14; place < sizeof(channel_all); place++) {
2782             if (channel_all[place] == chnl)
2783                 return place - 13;
2784         }
2785     }
2786 
2787     return 0;
2788 }
2789 
2790 void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
2791 {
2792     struct rtl_priv *rtlpriv = rtl_priv(hw);
2793     struct rtl_phy *rtlphy = &rtlpriv->phy;
2794     long result[4][8];
2795     u8 i, final_candidate;
2796     bool b_patha_ok, b_pathb_ok;
2797     long reg_e94, reg_e9c, reg_ea4;
2798     long reg_eb4, reg_ebc, reg_ec4;
2799     bool is12simular, is13simular, is23simular;
2800     u8 idx;
2801     u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2802         ROFDM0_XARXIQIMBALANCE,
2803         ROFDM0_XBRXIQIMBALANCE,
2804         ROFDM0_ECCATHRESHOLD,
2805         ROFDM0_AGCRSSITABLE,
2806         ROFDM0_XATXIQIMBALANCE,
2807         ROFDM0_XBTXIQIMBALANCE,
2808         ROFDM0_XCTXAFE,
2809         ROFDM0_XDTXAFE,
2810         ROFDM0_RXIQEXTANTA
2811     };
2812 
2813     if (b_recovery) {
2814         _rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg,
2815                            rtlphy->iqk_bb_backup, 9);
2816         return;
2817     }
2818 
2819     for (i = 0; i < 8; i++) {
2820         result[0][i] = 0;
2821         result[1][i] = 0;
2822         result[2][i] = 0;
2823 
2824         if ((i == 0) || (i == 2) || (i == 4)  || (i == 6))
2825             result[3][i] = 0x100;
2826         else
2827             result[3][i] = 0;
2828     }
2829     final_candidate = 0xff;
2830     b_patha_ok = false;
2831     b_pathb_ok = false;
2832     is12simular = false;
2833     is23simular = false;
2834     is13simular = false;
2835     for (i = 0; i < 3; i++) {
2836         _rtl92ee_phy_iq_calibrate(hw, result, i, true);
2837         if (i == 1) {
2838             is12simular = _rtl92ee_phy_simularity_compare(hw,
2839                                       result,
2840                                       0, 1);
2841             if (is12simular) {
2842                 final_candidate = 0;
2843                 break;
2844             }
2845         }
2846 
2847         if (i == 2) {
2848             is13simular = _rtl92ee_phy_simularity_compare(hw,
2849                                       result,
2850                                       0, 2);
2851             if (is13simular) {
2852                 final_candidate = 0;
2853                 break;
2854             }
2855             is23simular = _rtl92ee_phy_simularity_compare(hw,
2856                                       result,
2857                                       1, 2);
2858             if (is23simular)
2859                 final_candidate = 1;
2860             else
2861                 final_candidate = 3;
2862         }
2863     }
2864 
2865     reg_e94 = result[3][0];
2866     reg_e9c = result[3][1];
2867     reg_ea4 = result[3][2];
2868     reg_eb4 = result[3][4];
2869     reg_ebc = result[3][5];
2870     reg_ec4 = result[3][6];
2871 
2872     if (final_candidate != 0xff) {
2873         reg_e94 = result[final_candidate][0];
2874         rtlphy->reg_e94 = reg_e94;
2875         reg_e9c = result[final_candidate][1];
2876         rtlphy->reg_e9c = reg_e9c;
2877         reg_ea4 = result[final_candidate][2];
2878         reg_eb4 = result[final_candidate][4];
2879         rtlphy->reg_eb4 = reg_eb4;
2880         reg_ebc = result[final_candidate][5];
2881         rtlphy->reg_ebc = reg_ebc;
2882         reg_ec4 = result[final_candidate][6];
2883         b_patha_ok = true;
2884         b_pathb_ok = true;
2885     } else {
2886         rtlphy->reg_e94 = 0x100;
2887         rtlphy->reg_eb4 = 0x100;
2888         rtlphy->reg_e9c = 0x0;
2889         rtlphy->reg_ebc = 0x0;
2890     }
2891 
2892     if (reg_e94 != 0)
2893         _rtl92ee_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
2894                             final_candidate,
2895                             (reg_ea4 == 0));
2896 
2897     _rtl92ee_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok, result,
2898                         final_candidate,
2899                         (reg_ec4 == 0));
2900 
2901     idx = rtl92ee_get_rightchnlplace_for_iqk(rtlphy->current_channel);
2902 
2903     /* To Fix BSOD when final_candidate is 0xff */
2904     if (final_candidate < 4) {
2905         for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2906             rtlphy->iqk_matrix[idx].value[0][i] =
2907                 result[final_candidate][i];
2908 
2909         rtlphy->iqk_matrix[idx].iqk_done = true;
2910     }
2911     _rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg,
2912                      rtlphy->iqk_bb_backup, 9);
2913 }
2914 
2915 void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw)
2916 {
2917     struct rtl_priv *rtlpriv = rtl_priv(hw);
2918     struct rtl_phy *rtlphy = &rtlpriv->phy;
2919     struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
2920     u32 timeout = 2000, timecount = 0;
2921 
2922     while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2923         udelay(50);
2924         timecount += 50;
2925     }
2926 
2927     rtlphy->lck_inprogress = true;
2928     RTPRINT(rtlpriv, FINIT, INIT_IQK,
2929         "LCK:Start!!! currentband %x delay %d ms\n",
2930          rtlhal->current_bandtype, timecount);
2931 
2932     _rtl92ee_phy_lc_calibrate(hw, false);
2933 
2934     rtlphy->lck_inprogress = false;
2935 }
2936 
2937 void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
2938 {
2939 }
2940 
2941 void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
2942 {
2943     _rtl92ee_phy_set_rfpath_switch(hw, bmain, false);
2944 }
2945 
2946 bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2947 {
2948     struct rtl_priv *rtlpriv = rtl_priv(hw);
2949     struct rtl_phy *rtlphy = &rtlpriv->phy;
2950     bool postprocessing = false;
2951 
2952     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2953         "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2954         iotype, rtlphy->set_io_inprogress);
2955     do {
2956         switch (iotype) {
2957         case IO_CMD_RESUME_DM_BY_SCAN:
2958             rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2959                 "[IO CMD] Resume DM after scan.\n");
2960             postprocessing = true;
2961             break;
2962         case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
2963             rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2964                 "[IO CMD] Pause DM before scan.\n");
2965             postprocessing = true;
2966             break;
2967         default:
2968             rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
2969                 "switch case %#x not processed\n", iotype);
2970             break;
2971         }
2972     } while (false);
2973     if (postprocessing && !rtlphy->set_io_inprogress) {
2974         rtlphy->set_io_inprogress = true;
2975         rtlphy->current_io_type = iotype;
2976     } else {
2977         return false;
2978     }
2979     rtl92ee_phy_set_io(hw);
2980     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
2981     return true;
2982 }
2983 
2984 static void rtl92ee_phy_set_io(struct ieee80211_hw *hw)
2985 {
2986     struct rtl_priv *rtlpriv = rtl_priv(hw);
2987     struct rtl_phy *rtlphy = &rtlpriv->phy;
2988     struct dig_t *dm_dig = &rtlpriv->dm_digtable;
2989 
2990     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2991         "--->Cmd(%#x), set_io_inprogress(%d)\n",
2992         rtlphy->current_io_type, rtlphy->set_io_inprogress);
2993     switch (rtlphy->current_io_type) {
2994     case IO_CMD_RESUME_DM_BY_SCAN:
2995         rtl92ee_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1);
2996         rtl92ee_dm_write_cck_cca_thres(hw, rtlphy->initgain_backup.cca);
2997         rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "no set txpower\n");
2998         rtl92ee_phy_set_txpower_level(hw, rtlphy->current_channel);
2999         break;
3000     case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
3001         /* 8192eebt */
3002         rtlphy->initgain_backup.xaagccore1 = dm_dig->cur_igvalue;
3003         rtl92ee_dm_write_dig(hw, 0x17);
3004         rtlphy->initgain_backup.cca = dm_dig->cur_cck_cca_thres;
3005         rtl92ee_dm_write_cck_cca_thres(hw, 0x40);
3006         break;
3007     default:
3008         rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
3009             "switch case %#x not processed\n",
3010             rtlphy->current_io_type);
3011         break;
3012     }
3013     rtlphy->set_io_inprogress = false;
3014     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
3015         "(%#x)\n", rtlphy->current_io_type);
3016 }
3017 
3018 static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw)
3019 {
3020     struct rtl_priv *rtlpriv = rtl_priv(hw);
3021 
3022     rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
3023     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3024     /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/
3025     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3026     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3027     rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3028 }
3029 
3030 static void _rtl92ee_phy_set_rf_sleep(struct ieee80211_hw *hw)
3031 {
3032     struct rtl_priv *rtlpriv = rtl_priv(hw);
3033 
3034     rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3035     rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3036 
3037     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3038     rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3039 }
3040 
3041 static bool _rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
3042                         enum rf_pwrstate rfpwr_state)
3043 {
3044     struct rtl_priv *rtlpriv = rtl_priv(hw);
3045     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3046     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3047     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3048     bool bresult = true;
3049     u8 i, queue_id;
3050     struct rtl8192_tx_ring *ring = NULL;
3051 
3052     switch (rfpwr_state) {
3053     case ERFON:
3054         if ((ppsc->rfpwr_state == ERFOFF) &&
3055             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3056             bool rtstatus;
3057             u32 initializecount = 0;
3058 
3059             do {
3060                 initializecount++;
3061                 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3062                     "IPS Set eRf nic enable\n");
3063                 rtstatus = rtl_ps_enable_nic(hw);
3064             } while (!rtstatus && (initializecount < 10));
3065             RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3066         } else {
3067             rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3068                 "Set ERFON sleeping:%d ms\n",
3069                 jiffies_to_msecs(jiffies -
3070                          ppsc->last_sleep_jiffies));
3071             ppsc->last_awake_jiffies = jiffies;
3072             rtl92ee_phy_set_rf_on(hw);
3073         }
3074         if (mac->link_state == MAC80211_LINKED)
3075             rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK);
3076         else
3077             rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK);
3078         break;
3079     case ERFOFF:
3080         for (queue_id = 0, i = 0;
3081              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3082             ring = &pcipriv->dev.tx_ring[queue_id];
3083             if (queue_id == BEACON_QUEUE ||
3084                 skb_queue_len(&ring->queue) == 0) {
3085                 queue_id++;
3086                 continue;
3087             } else {
3088                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3089                     "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3090                     (i + 1), queue_id,
3091                     skb_queue_len(&ring->queue));
3092 
3093                 udelay(10);
3094                 i++;
3095             }
3096             if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3097                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3098                     "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
3099                     MAX_DOZE_WAITING_TIMES_9x,
3100                     queue_id,
3101                     skb_queue_len(&ring->queue));
3102                 break;
3103             }
3104         }
3105 
3106         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3107             rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3108                 "IPS Set eRf nic disable\n");
3109             rtl_ps_disable_nic(hw);
3110             RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3111         } else {
3112             if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
3113                 rtlpriv->cfg->ops->led_control(hw,
3114                             LED_CTL_NO_LINK);
3115             } else {
3116                 rtlpriv->cfg->ops->led_control(hw,
3117                             LED_CTL_POWER_OFF);
3118             }
3119         }
3120         break;
3121     case ERFSLEEP:
3122         if (ppsc->rfpwr_state == ERFOFF)
3123             break;
3124         for (queue_id = 0, i = 0;
3125              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3126             ring = &pcipriv->dev.tx_ring[queue_id];
3127             if (skb_queue_len(&ring->queue) == 0) {
3128                 queue_id++;
3129                 continue;
3130             } else {
3131                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3132                     "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3133                     (i + 1), queue_id,
3134                     skb_queue_len(&ring->queue));
3135                 udelay(10);
3136                 i++;
3137             }
3138             if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3139                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3140                     "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
3141                     MAX_DOZE_WAITING_TIMES_9x,
3142                     queue_id,
3143                     skb_queue_len(&ring->queue));
3144                 break;
3145             }
3146         }
3147         rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3148             "Set ERFSLEEP awaked:%d ms\n",
3149             jiffies_to_msecs(jiffies -
3150                      ppsc->last_awake_jiffies));
3151         ppsc->last_sleep_jiffies = jiffies;
3152         _rtl92ee_phy_set_rf_sleep(hw);
3153         break;
3154     default:
3155         rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
3156             "switch case %#x not processed\n", rfpwr_state);
3157         bresult = false;
3158         break;
3159     }
3160     if (bresult)
3161         ppsc->rfpwr_state = rfpwr_state;
3162     return bresult;
3163 }
3164 
3165 bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
3166                     enum rf_pwrstate rfpwr_state)
3167 {
3168     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3169 
3170     bool bresult = false;
3171 
3172     if (rfpwr_state == ppsc->rfpwr_state)
3173         return bresult;
3174     bresult = _rtl92ee_phy_set_rf_power_state(hw, rfpwr_state);
3175     return bresult;
3176 }
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