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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 2009-2014  Realtek Corporation.*/
0003 
0004 #include "../wifi.h"
0005 #include "../base.h"
0006 #include "../pci.h"
0007 #include "../core.h"
0008 #include "reg.h"
0009 #include "def.h"
0010 #include "phy.h"
0011 #include "dm.h"
0012 #include "fw.h"
0013 #include "trx.h"
0014 
0015 static void rtl92ee_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
0016 {
0017     u32 ret_value;
0018     struct rtl_priv *rtlpriv = rtl_priv(hw);
0019     struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
0020 
0021     rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
0022     rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
0023 
0024     ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
0025     falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
0026     falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
0027 
0028     ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
0029     falsealm_cnt->cnt_ofdm_cca = (ret_value & 0xffff);
0030     falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
0031 
0032     ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
0033     falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
0034     falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
0035 
0036     ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
0037     falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
0038 
0039     falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
0040                       falsealm_cnt->cnt_rate_illegal +
0041                       falsealm_cnt->cnt_crc8_fail +
0042                       falsealm_cnt->cnt_mcs_fail +
0043                       falsealm_cnt->cnt_fast_fsync_fail +
0044                       falsealm_cnt->cnt_sb_search_fail;
0045 
0046     ret_value = rtl_get_bbreg(hw, DM_REG_SC_CNT_11N, MASKDWORD);
0047     falsealm_cnt->cnt_bw_lsc = (ret_value & 0xffff);
0048     falsealm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16);
0049 
0050     rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(12), 1);
0051     rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(14), 1);
0052 
0053     ret_value = rtl_get_bbreg(hw, DM_REG_CCK_FA_LSB_11N, MASKBYTE0);
0054     falsealm_cnt->cnt_cck_fail = ret_value;
0055 
0056     ret_value = rtl_get_bbreg(hw, DM_REG_CCK_FA_MSB_11N, MASKBYTE3);
0057     falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
0058 
0059     ret_value = rtl_get_bbreg(hw, DM_REG_CCK_CCA_CNT_11N, MASKDWORD);
0060     falsealm_cnt->cnt_cck_cca = ((ret_value & 0xff) << 8) |
0061                     ((ret_value & 0xFF00) >> 8);
0062 
0063     falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail +
0064                 falsealm_cnt->cnt_sb_search_fail +
0065                 falsealm_cnt->cnt_parity_fail +
0066                 falsealm_cnt->cnt_rate_illegal +
0067                 falsealm_cnt->cnt_crc8_fail +
0068                 falsealm_cnt->cnt_mcs_fail +
0069                 falsealm_cnt->cnt_cck_fail;
0070 
0071     falsealm_cnt->cnt_cca_all = falsealm_cnt->cnt_ofdm_cca +
0072                     falsealm_cnt->cnt_cck_cca;
0073 
0074     /*reset false alarm counter registers*/
0075     rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
0076     rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
0077     rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
0078     rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
0079     /*update ofdm counter*/
0080     rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
0081     rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
0082     /*reset CCK CCA counter*/
0083     rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 0);
0084     rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 2);
0085     /*reset CCK FA counter*/
0086     rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 0);
0087     rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2);
0088 
0089     rtl_dbg(rtlpriv, COMP_DIG, DBG_TRACE,
0090         "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
0091         falsealm_cnt->cnt_parity_fail,
0092         falsealm_cnt->cnt_rate_illegal,
0093         falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
0094 
0095     rtl_dbg(rtlpriv, COMP_DIG, DBG_TRACE,
0096         "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
0097         falsealm_cnt->cnt_ofdm_fail,
0098         falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
0099 }
0100 
0101 static void rtl92ee_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
0102 {
0103     struct rtl_priv *rtlpriv = rtl_priv(hw);
0104     struct dig_t *dm_dig = &rtlpriv->dm_digtable;
0105     u8 cur_cck_cca_thresh;
0106 
0107     if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
0108         if (dm_dig->rssi_val_min > 25) {
0109             cur_cck_cca_thresh = 0xcd;
0110         } else if ((dm_dig->rssi_val_min <= 25) &&
0111                (dm_dig->rssi_val_min > 10)) {
0112             cur_cck_cca_thresh = 0x83;
0113         } else {
0114             if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
0115                 cur_cck_cca_thresh = 0x83;
0116             else
0117                 cur_cck_cca_thresh = 0x40;
0118         }
0119     } else {
0120         if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
0121             cur_cck_cca_thresh = 0x83;
0122         else
0123             cur_cck_cca_thresh = 0x40;
0124     }
0125     rtl92ee_dm_write_cck_cca_thres(hw, cur_cck_cca_thresh);
0126 }
0127 
0128 static void rtl92ee_dm_dig(struct ieee80211_hw *hw)
0129 {
0130     struct rtl_priv *rtlpriv = rtl_priv(hw);
0131     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
0132     struct dig_t *dm_dig = &rtlpriv->dm_digtable;
0133     u8 dig_min_0, dig_maxofmin;
0134     bool bfirstconnect , bfirstdisconnect;
0135     u8 dm_dig_max, dm_dig_min;
0136     u8 current_igi = dm_dig->cur_igvalue;
0137     u8 offset;
0138 
0139     /* AP,BT */
0140     if (mac->act_scanning)
0141         return;
0142 
0143     dig_min_0 = dm_dig->dig_min_0;
0144     bfirstconnect = (mac->link_state >= MAC80211_LINKED) &&
0145             !dm_dig->media_connect_0;
0146     bfirstdisconnect = (mac->link_state < MAC80211_LINKED) &&
0147                dm_dig->media_connect_0;
0148 
0149     dm_dig_max = 0x5a;
0150     dm_dig_min = DM_DIG_MIN;
0151     dig_maxofmin = DM_DIG_MAX_AP;
0152 
0153     if (mac->link_state >= MAC80211_LINKED) {
0154         if ((dm_dig->rssi_val_min + 10) > dm_dig_max)
0155             dm_dig->rx_gain_max = dm_dig_max;
0156         else if ((dm_dig->rssi_val_min + 10) < dm_dig_min)
0157             dm_dig->rx_gain_max = dm_dig_min;
0158         else
0159             dm_dig->rx_gain_max = dm_dig->rssi_val_min + 10;
0160 
0161         if (rtlpriv->dm.one_entry_only) {
0162             offset = 0;
0163             if (dm_dig->rssi_val_min - offset < dm_dig_min)
0164                 dig_min_0 = dm_dig_min;
0165             else if (dm_dig->rssi_val_min - offset >
0166                  dig_maxofmin)
0167                 dig_min_0 = dig_maxofmin;
0168             else
0169                 dig_min_0 = dm_dig->rssi_val_min - offset;
0170         } else {
0171             dig_min_0 = dm_dig_min;
0172         }
0173 
0174     } else {
0175         dm_dig->rx_gain_max = dm_dig_max;
0176         dig_min_0 = dm_dig_min;
0177         rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "no link\n");
0178     }
0179 
0180     if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
0181         if (dm_dig->large_fa_hit != 3)
0182             dm_dig->large_fa_hit++;
0183         if (dm_dig->forbidden_igi < current_igi) {
0184             dm_dig->forbidden_igi = current_igi;
0185             dm_dig->large_fa_hit = 1;
0186         }
0187 
0188         if (dm_dig->large_fa_hit >= 3) {
0189             if (dm_dig->forbidden_igi + 1 > dm_dig->rx_gain_max)
0190                 dm_dig->rx_gain_min =
0191                         dm_dig->rx_gain_max;
0192             else
0193                 dm_dig->rx_gain_min =
0194                         dm_dig->forbidden_igi + 1;
0195             dm_dig->recover_cnt = 3600;
0196         }
0197     } else {
0198         if (dm_dig->recover_cnt != 0) {
0199             dm_dig->recover_cnt--;
0200         } else {
0201             if (dm_dig->large_fa_hit < 3) {
0202                 if ((dm_dig->forbidden_igi - 1) <
0203                     dig_min_0) {
0204                     dm_dig->forbidden_igi = dig_min_0;
0205                     dm_dig->rx_gain_min =
0206                                 dig_min_0;
0207                 } else {
0208                     dm_dig->forbidden_igi--;
0209                     dm_dig->rx_gain_min =
0210                         dm_dig->forbidden_igi + 1;
0211                 }
0212             } else {
0213                 dm_dig->large_fa_hit = 0;
0214             }
0215         }
0216     }
0217 
0218     if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 5)
0219         dm_dig->rx_gain_min = dm_dig_min;
0220 
0221     if (dm_dig->rx_gain_min > dm_dig->rx_gain_max)
0222         dm_dig->rx_gain_min = dm_dig->rx_gain_max;
0223 
0224     if (mac->link_state >= MAC80211_LINKED) {
0225         if (bfirstconnect) {
0226             if (dm_dig->rssi_val_min <= dig_maxofmin)
0227                 current_igi = dm_dig->rssi_val_min;
0228             else
0229                 current_igi = dig_maxofmin;
0230 
0231             dm_dig->large_fa_hit = 0;
0232         } else {
0233             if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH2)
0234                 current_igi += 4;
0235             else if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH1)
0236                 current_igi += 2;
0237             else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
0238                 current_igi -= 2;
0239 
0240             if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 5 &&
0241                 rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
0242                 current_igi = dm_dig->rx_gain_min;
0243         }
0244     } else {
0245         if (bfirstdisconnect) {
0246             current_igi = dm_dig->rx_gain_min;
0247         } else {
0248             if (rtlpriv->falsealm_cnt.cnt_all > 10000)
0249                 current_igi += 4;
0250             else if (rtlpriv->falsealm_cnt.cnt_all > 8000)
0251                 current_igi += 2;
0252             else if (rtlpriv->falsealm_cnt.cnt_all < 500)
0253                 current_igi -= 2;
0254         }
0255     }
0256 
0257     if (current_igi > dm_dig->rx_gain_max)
0258         current_igi = dm_dig->rx_gain_max;
0259     if (current_igi < dm_dig->rx_gain_min)
0260         current_igi = dm_dig->rx_gain_min;
0261 
0262     rtl92ee_dm_write_dig(hw , current_igi);
0263     dm_dig->media_connect_0 = ((mac->link_state >= MAC80211_LINKED) ?
0264                    true : false);
0265     dm_dig->dig_min_0 = dig_min_0;
0266 }
0267 
0268 void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 cur_thres)
0269 {
0270     struct rtl_priv *rtlpriv = rtl_priv(hw);
0271     struct dig_t *dm_dig = &rtlpriv->dm_digtable;
0272 
0273     if (dm_dig->cur_cck_cca_thres != cur_thres)
0274         rtl_write_byte(rtlpriv, DM_REG_CCK_CCA_11N, cur_thres);
0275 
0276     dm_dig->pre_cck_cca_thres = dm_dig->cur_cck_cca_thres;
0277     dm_dig->cur_cck_cca_thres = cur_thres;
0278 }
0279 
0280 void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi)
0281 {
0282     struct rtl_priv *rtlpriv = rtl_priv(hw);
0283     struct dig_t *dm_dig = &rtlpriv->dm_digtable;
0284 
0285     if (dm_dig->stop_dig)
0286         return;
0287 
0288     if (dm_dig->cur_igvalue != current_igi) {
0289         rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, current_igi);
0290         if (rtlpriv->phy.rf_type != RF_1T1R)
0291             rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, current_igi);
0292     }
0293     dm_dig->pre_igvalue = dm_dig->cur_igvalue;
0294     dm_dig->cur_igvalue = current_igi;
0295 }
0296 
0297 static void rtl92ee_rssi_dump_to_register(struct ieee80211_hw *hw)
0298 {
0299     struct rtl_priv *rtlpriv = rtl_priv(hw);
0300 
0301     rtl_write_byte(rtlpriv, RA_RSSIDUMP,
0302                rtlpriv->stats.rx_rssi_percentage[0]);
0303     rtl_write_byte(rtlpriv, RB_RSSIDUMP,
0304                rtlpriv->stats.rx_rssi_percentage[1]);
0305     /*It seems the following values are not initialized.
0306       *According to Windows code,
0307       *these value will only be valid with JAGUAR chips
0308       */
0309     /* Rx EVM */
0310     rtl_write_byte(rtlpriv, RS1_RXEVMDUMP, rtlpriv->stats.rx_evm_dbm[0]);
0311     rtl_write_byte(rtlpriv, RS2_RXEVMDUMP, rtlpriv->stats.rx_evm_dbm[1]);
0312     /* Rx SNR */
0313     rtl_write_byte(rtlpriv, RA_RXSNRDUMP,
0314                (u8)(rtlpriv->stats.rx_snr_db[0]));
0315     rtl_write_byte(rtlpriv, RB_RXSNRDUMP,
0316                (u8)(rtlpriv->stats.rx_snr_db[1]));
0317     /* Rx Cfo_Short */
0318     rtl_write_word(rtlpriv, RA_CFOSHORTDUMP,
0319                rtlpriv->stats.rx_cfo_short[0]);
0320     rtl_write_word(rtlpriv, RB_CFOSHORTDUMP,
0321                rtlpriv->stats.rx_cfo_short[1]);
0322     /* Rx Cfo_Tail */
0323     rtl_write_word(rtlpriv, RA_CFOLONGDUMP, rtlpriv->stats.rx_cfo_tail[0]);
0324     rtl_write_word(rtlpriv, RB_CFOLONGDUMP, rtlpriv->stats.rx_cfo_tail[1]);
0325 }
0326 
0327 static void rtl92ee_dm_find_minimum_rssi(struct ieee80211_hw *hw)
0328 {
0329     struct rtl_priv *rtlpriv = rtl_priv(hw);
0330     struct dig_t *rtl_dm_dig = &rtlpriv->dm_digtable;
0331     struct rtl_mac *mac = rtl_mac(rtlpriv);
0332 
0333     /* Determine the minimum RSSI  */
0334     if ((mac->link_state < MAC80211_LINKED) &&
0335         (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
0336         rtl_dm_dig->min_undec_pwdb_for_dm = 0;
0337         rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
0338             "Not connected to any\n");
0339     }
0340     if (mac->link_state >= MAC80211_LINKED) {
0341         if (mac->opmode == NL80211_IFTYPE_AP ||
0342             mac->opmode == NL80211_IFTYPE_ADHOC) {
0343             rtl_dm_dig->min_undec_pwdb_for_dm =
0344                 rtlpriv->dm.entry_min_undec_sm_pwdb;
0345             rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
0346                 "AP Client PWDB = 0x%lx\n",
0347                 rtlpriv->dm.entry_min_undec_sm_pwdb);
0348         } else {
0349             rtl_dm_dig->min_undec_pwdb_for_dm =
0350                 rtlpriv->dm.undec_sm_pwdb;
0351             rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
0352                 "STA Default Port PWDB = 0x%x\n",
0353                 rtl_dm_dig->min_undec_pwdb_for_dm);
0354         }
0355     } else {
0356         rtl_dm_dig->min_undec_pwdb_for_dm =
0357             rtlpriv->dm.entry_min_undec_sm_pwdb;
0358         rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
0359             "AP Ext Port or disconnect PWDB = 0x%x\n",
0360             rtl_dm_dig->min_undec_pwdb_for_dm);
0361     }
0362     rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
0363         "MinUndecoratedPWDBForDM =%d\n",
0364         rtl_dm_dig->min_undec_pwdb_for_dm);
0365 }
0366 
0367 static void rtl92ee_dm_check_rssi_monitor(struct ieee80211_hw *hw)
0368 {
0369     struct rtl_priv *rtlpriv = rtl_priv(hw);
0370     struct dig_t *dm_dig = &rtlpriv->dm_digtable;
0371     struct rtl_mac *mac = rtl_mac(rtlpriv);
0372     struct rtl_dm *dm = rtl_dm(rtlpriv);
0373     struct rtl_sta_info *drv_priv;
0374     u8 h2c[4] = { 0 };
0375     long max = 0, min = 0xff;
0376     u8 i = 0;
0377 
0378     if (mac->opmode == NL80211_IFTYPE_AP ||
0379         mac->opmode == NL80211_IFTYPE_ADHOC ||
0380         mac->opmode == NL80211_IFTYPE_MESH_POINT) {
0381         /* AP & ADHOC & MESH */
0382         spin_lock_bh(&rtlpriv->locks.entry_list_lock);
0383         list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
0384             struct rssi_sta *stat = &drv_priv->rssi_stat;
0385 
0386             if (stat->undec_sm_pwdb < min)
0387                 min = stat->undec_sm_pwdb;
0388             if (stat->undec_sm_pwdb > max)
0389                 max = stat->undec_sm_pwdb;
0390 
0391             h2c[3] = 0;
0392             h2c[2] = (u8)(dm->undec_sm_pwdb & 0xFF);
0393             h2c[1] = 0x20;
0394             h2c[0] = ++i;
0395             rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSSI_REPORT, 4, h2c);
0396         }
0397         spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
0398 
0399         /* If associated entry is found */
0400         if (max != 0) {
0401             dm->entry_max_undec_sm_pwdb = max;
0402             RTPRINT(rtlpriv, FDM, DM_PWDB,
0403                 "EntryMaxPWDB = 0x%lx(%ld)\n", max, max);
0404         } else {
0405             dm->entry_max_undec_sm_pwdb = 0;
0406         }
0407         /* If associated entry is found */
0408         if (min != 0xff) {
0409             dm->entry_min_undec_sm_pwdb = min;
0410             RTPRINT(rtlpriv, FDM, DM_PWDB,
0411                 "EntryMinPWDB = 0x%lx(%ld)\n", min, min);
0412         } else {
0413             dm->entry_min_undec_sm_pwdb = 0;
0414         }
0415     }
0416 
0417     /* Indicate Rx signal strength to FW. */
0418     if (dm->useramask) {
0419         h2c[3] = 0;
0420         h2c[2] = (u8)(dm->undec_sm_pwdb & 0xFF);
0421         h2c[1] = 0x20;
0422         h2c[0] = 0;
0423         rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSSI_REPORT, 4, h2c);
0424     } else {
0425         rtl_write_byte(rtlpriv, 0x4fe, dm->undec_sm_pwdb);
0426     }
0427     rtl92ee_rssi_dump_to_register(hw);
0428     rtl92ee_dm_find_minimum_rssi(hw);
0429     dm_dig->rssi_val_min = rtlpriv->dm_digtable.min_undec_pwdb_for_dm;
0430 }
0431 
0432 static void rtl92ee_dm_init_primary_cca_check(struct ieee80211_hw *hw)
0433 {
0434     struct rtl_priv *rtlpriv = rtl_priv(hw);
0435     struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
0436     struct dynamic_primary_cca *primarycca = &rtlpriv->primarycca;
0437 
0438     rtlhal->rts_en = 0;
0439     primarycca->dup_rts_flag = 0;
0440     primarycca->intf_flag = 0;
0441     primarycca->intf_type = 0;
0442     primarycca->monitor_flag = 0;
0443     primarycca->ch_offset = 0;
0444     primarycca->mf_state = 0;
0445 }
0446 
0447 static bool rtl92ee_dm_is_edca_turbo_disable(struct ieee80211_hw *hw)
0448 {
0449     struct rtl_priv *rtlpriv = rtl_priv(hw);
0450 
0451     if (rtlpriv->mac80211.mode == WIRELESS_MODE_B)
0452         return true;
0453 
0454     return false;
0455 }
0456 
0457 void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw)
0458 {
0459     struct rtl_priv *rtlpriv = rtl_priv(hw);
0460 
0461     rtlpriv->dm.current_turbo_edca = false;
0462     rtlpriv->dm.is_cur_rdlstate = false;
0463     rtlpriv->dm.is_any_nonbepkts = false;
0464 }
0465 
0466 static void rtl92ee_dm_check_edca_turbo(struct ieee80211_hw *hw)
0467 {
0468     struct rtl_priv *rtlpriv = rtl_priv(hw);
0469 
0470     static u64 last_txok_cnt;
0471     static u64 last_rxok_cnt;
0472     u64 cur_txok_cnt = 0;
0473     u64 cur_rxok_cnt = 0;
0474     u32 edca_be_ul = 0x5ea42b;
0475     u32 edca_be_dl = 0x5ea42b; /*not sure*/
0476     u32 edca_be = 0x5ea42b;
0477     bool is_cur_rdlstate;
0478     bool b_edca_turbo_on = false;
0479 
0480     if (rtlpriv->dm.dbginfo.num_non_be_pkt > 0x100)
0481         rtlpriv->dm.is_any_nonbepkts = true;
0482     rtlpriv->dm.dbginfo.num_non_be_pkt = 0;
0483 
0484     cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
0485     cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
0486 
0487     /*b_bias_on_rx = false;*/
0488     b_edca_turbo_on = ((!rtlpriv->dm.is_any_nonbepkts) &&
0489                (!rtlpriv->dm.disable_framebursting)) ?
0490               true : false;
0491 
0492     if (rtl92ee_dm_is_edca_turbo_disable(hw))
0493         goto check_exit;
0494 
0495     if (b_edca_turbo_on) {
0496         is_cur_rdlstate = (cur_rxok_cnt > cur_txok_cnt * 4) ?
0497                     true : false;
0498 
0499         edca_be = is_cur_rdlstate ? edca_be_dl : edca_be_ul;
0500         rtl_write_dword(rtlpriv , REG_EDCA_BE_PARAM , edca_be);
0501         rtlpriv->dm.is_cur_rdlstate = is_cur_rdlstate;
0502         rtlpriv->dm.current_turbo_edca = true;
0503     } else {
0504         if (rtlpriv->dm.current_turbo_edca) {
0505             u8 tmp = AC0_BE;
0506 
0507             rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
0508                               (u8 *)(&tmp));
0509         }
0510         rtlpriv->dm.current_turbo_edca = false;
0511     }
0512 
0513 check_exit:
0514     rtlpriv->dm.is_any_nonbepkts = false;
0515     last_txok_cnt = rtlpriv->stats.txbytesunicast;
0516     last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
0517 }
0518 
0519 static void rtl92ee_dm_dynamic_edcca(struct ieee80211_hw *hw)
0520 {
0521     struct rtl_priv *rtlpriv = rtl_priv(hw);
0522     u8 reg_c50 , reg_c58;
0523     bool fw_current_in_ps_mode = false;
0524 
0525     rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
0526                       (u8 *)(&fw_current_in_ps_mode));
0527     if (fw_current_in_ps_mode)
0528         return;
0529 
0530     reg_c50 = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
0531     reg_c58 = rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
0532 
0533     if (reg_c50 > 0x28 && reg_c58 > 0x28) {
0534         if (!rtlpriv->rtlhal.pre_edcca_enable) {
0535             rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD, 0x03);
0536             rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD + 2, 0x00);
0537             rtlpriv->rtlhal.pre_edcca_enable = true;
0538         }
0539     } else if (reg_c50 < 0x25 && reg_c58 < 0x25) {
0540         if (rtlpriv->rtlhal.pre_edcca_enable) {
0541             rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD, 0x7f);
0542             rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD + 2, 0x7f);
0543             rtlpriv->rtlhal.pre_edcca_enable = false;
0544         }
0545     }
0546 }
0547 
0548 static void rtl92ee_dm_adaptivity(struct ieee80211_hw *hw)
0549 {
0550     rtl92ee_dm_dynamic_edcca(hw);
0551 }
0552 
0553 static void rtl92ee_dm_write_dynamic_cca(struct ieee80211_hw *hw,
0554                      u8 cur_mf_state)
0555 {
0556     struct dynamic_primary_cca *primarycca = &rtl_priv(hw)->primarycca;
0557 
0558     if (primarycca->mf_state != cur_mf_state)
0559         rtl_set_bbreg(hw, DM_REG_L1SBD_PD_CH_11N, BIT(8) | BIT(7),
0560                   cur_mf_state);
0561 
0562     primarycca->mf_state = cur_mf_state;
0563 }
0564 
0565 static void rtl92ee_dm_dynamic_primary_cca_ckeck(struct ieee80211_hw *hw)
0566 {
0567     struct rtl_priv *rtlpriv = rtl_priv(hw);
0568     struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
0569     struct dynamic_primary_cca *primarycca = &rtlpriv->primarycca;
0570     bool is40mhz = false;
0571     u64 ofdm_cca, ofdm_fa, bw_usc_cnt, bw_lsc_cnt;
0572     u8 sec_ch_offset;
0573     u8 cur_mf_state;
0574     static u8 count_down = MONITOR_TIME;
0575 
0576     ofdm_cca = falsealm_cnt->cnt_ofdm_cca;
0577     ofdm_fa = falsealm_cnt->cnt_ofdm_fail;
0578     bw_usc_cnt = falsealm_cnt->cnt_bw_usc;
0579     bw_lsc_cnt = falsealm_cnt->cnt_bw_lsc;
0580     is40mhz = rtlpriv->mac80211.bw_40;
0581     sec_ch_offset = rtlpriv->mac80211.cur_40_prime_sc;
0582     /* NIC: 2: sec is below,  1: sec is above */
0583 
0584     if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) {
0585         cur_mf_state = MF_USC_LSC;
0586         rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
0587         return;
0588     }
0589 
0590     if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
0591         return;
0592 
0593     if (is40mhz)
0594         return;
0595 
0596     if (primarycca->pricca_flag == 0) {
0597         /* Primary channel is above
0598          * NOTE: duplicate CTS can remove this condition
0599          */
0600         if (sec_ch_offset == 2) {
0601             if ((ofdm_cca > OFDMCCA_TH) &&
0602                 (bw_lsc_cnt > (bw_usc_cnt + BW_IND_BIAS)) &&
0603                 (ofdm_fa > (ofdm_cca >> 1))) {
0604                 primarycca->intf_type = 1;
0605                 primarycca->intf_flag = 1;
0606                 cur_mf_state = MF_USC;
0607                 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
0608                 primarycca->pricca_flag = 1;
0609             } else if ((ofdm_cca > OFDMCCA_TH) &&
0610                    (bw_lsc_cnt > (bw_usc_cnt + BW_IND_BIAS)) &&
0611                    (ofdm_fa < (ofdm_cca >> 1))) {
0612                 primarycca->intf_type = 2;
0613                 primarycca->intf_flag = 1;
0614                 cur_mf_state = MF_USC;
0615                 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
0616                 primarycca->pricca_flag = 1;
0617                 primarycca->dup_rts_flag = 1;
0618                 rtlpriv->rtlhal.rts_en = 1;
0619             } else {
0620                 primarycca->intf_type = 0;
0621                 primarycca->intf_flag = 0;
0622                 cur_mf_state = MF_USC_LSC;
0623                 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
0624                 rtlpriv->rtlhal.rts_en = 0;
0625                 primarycca->dup_rts_flag = 0;
0626             }
0627         } else if (sec_ch_offset == 1) {
0628             if ((ofdm_cca > OFDMCCA_TH) &&
0629                 (bw_usc_cnt > (bw_lsc_cnt + BW_IND_BIAS)) &&
0630                 (ofdm_fa > (ofdm_cca >> 1))) {
0631                 primarycca->intf_type = 1;
0632                 primarycca->intf_flag = 1;
0633                 cur_mf_state = MF_LSC;
0634                 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
0635                 primarycca->pricca_flag = 1;
0636             } else if ((ofdm_cca > OFDMCCA_TH) &&
0637                    (bw_usc_cnt > (bw_lsc_cnt + BW_IND_BIAS)) &&
0638                    (ofdm_fa < (ofdm_cca >> 1))) {
0639                 primarycca->intf_type = 2;
0640                 primarycca->intf_flag = 1;
0641                 cur_mf_state = MF_LSC;
0642                 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
0643                 primarycca->pricca_flag = 1;
0644                 primarycca->dup_rts_flag = 1;
0645                 rtlpriv->rtlhal.rts_en = 1;
0646             } else {
0647                 primarycca->intf_type = 0;
0648                 primarycca->intf_flag = 0;
0649                 cur_mf_state = MF_USC_LSC;
0650                 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
0651                 rtlpriv->rtlhal.rts_en = 0;
0652                 primarycca->dup_rts_flag = 0;
0653             }
0654         }
0655     } else {/* PrimaryCCA->PriCCA_flag==1 */
0656         count_down--;
0657         if (count_down == 0) {
0658             count_down = MONITOR_TIME;
0659             primarycca->pricca_flag = 0;
0660             cur_mf_state = MF_USC_LSC;
0661             /* default */
0662             rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
0663             rtlpriv->rtlhal.rts_en = 0;
0664             primarycca->dup_rts_flag = 0;
0665             primarycca->intf_type = 0;
0666             primarycca->intf_flag = 0;
0667         }
0668     }
0669 }
0670 
0671 static void rtl92ee_dm_dynamic_atc_switch(struct ieee80211_hw *hw)
0672 {
0673     struct rtl_priv *rtlpriv = rtl_priv(hw);
0674     struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
0675     u8 crystal_cap;
0676     u32 packet_count;
0677     int cfo_khz_a , cfo_khz_b , cfo_ave = 0, adjust_xtal = 0;
0678     int cfo_ave_diff;
0679 
0680     if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
0681         if (rtldm->atc_status == ATC_STATUS_OFF) {
0682             rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
0683                       ATC_STATUS_ON);
0684             rtldm->atc_status = ATC_STATUS_ON;
0685         }
0686         /* Disable CFO tracking for BT */
0687         if (rtlpriv->cfg->ops->get_btc_status()) {
0688             if (!rtlpriv->btcoexist.btc_ops->
0689                 btc_is_bt_disabled(rtlpriv)) {
0690                 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
0691                     "odm_DynamicATCSwitch(): Disable CFO tracking for BT!!\n");
0692                 return;
0693             }
0694         }
0695         /* Reset Crystal Cap */
0696         if (rtldm->crystal_cap != rtlpriv->efuse.crystalcap) {
0697             rtldm->crystal_cap = rtlpriv->efuse.crystalcap;
0698             crystal_cap = rtldm->crystal_cap & 0x3f;
0699             rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
0700                       (crystal_cap | (crystal_cap << 6)));
0701         }
0702     } else {
0703         cfo_khz_a = (int)(rtldm->cfo_tail[0] * 3125) / 1280;
0704         cfo_khz_b = (int)(rtldm->cfo_tail[1] * 3125) / 1280;
0705         packet_count = rtldm->packet_count;
0706 
0707         if (packet_count == rtldm->packet_count_pre)
0708             return;
0709 
0710         rtldm->packet_count_pre = packet_count;
0711 
0712         if (rtlpriv->phy.rf_type == RF_1T1R)
0713             cfo_ave = cfo_khz_a;
0714         else
0715             cfo_ave = (int)(cfo_khz_a + cfo_khz_b) >> 1;
0716 
0717         cfo_ave_diff = (rtldm->cfo_ave_pre >= cfo_ave) ?
0718                    (rtldm->cfo_ave_pre - cfo_ave) :
0719                    (cfo_ave - rtldm->cfo_ave_pre);
0720 
0721         if (cfo_ave_diff > 20 && !rtldm->large_cfo_hit) {
0722             rtldm->large_cfo_hit = true;
0723             return;
0724         }
0725         rtldm->large_cfo_hit = false;
0726 
0727         rtldm->cfo_ave_pre = cfo_ave;
0728 
0729         if (cfo_ave >= -rtldm->cfo_threshold &&
0730             cfo_ave <= rtldm->cfo_threshold && rtldm->is_freeze == 0) {
0731             if (rtldm->cfo_threshold == CFO_THRESHOLD_XTAL) {
0732                 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL + 10;
0733                 rtldm->is_freeze = 1;
0734             } else {
0735                 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL;
0736             }
0737         }
0738 
0739         if (cfo_ave > rtldm->cfo_threshold && rtldm->crystal_cap < 0x3f)
0740             adjust_xtal = ((cfo_ave - CFO_THRESHOLD_XTAL) >> 2) + 1;
0741         else if ((cfo_ave < -rtlpriv->dm.cfo_threshold) &&
0742              rtlpriv->dm.crystal_cap > 0)
0743             adjust_xtal = ((cfo_ave + CFO_THRESHOLD_XTAL) >> 2) - 1;
0744 
0745         if (adjust_xtal != 0) {
0746             rtldm->is_freeze = 0;
0747             rtldm->crystal_cap += adjust_xtal;
0748 
0749             if (rtldm->crystal_cap > 0x3f)
0750                 rtldm->crystal_cap = 0x3f;
0751             else if (rtldm->crystal_cap < 0)
0752                 rtldm->crystal_cap = 0;
0753 
0754             crystal_cap = rtldm->crystal_cap & 0x3f;
0755             rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
0756                       (crystal_cap | (crystal_cap << 6)));
0757         }
0758 
0759         if (cfo_ave < CFO_THRESHOLD_ATC &&
0760             cfo_ave > -CFO_THRESHOLD_ATC) {
0761             if (rtldm->atc_status == ATC_STATUS_ON) {
0762                 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
0763                           ATC_STATUS_OFF);
0764                 rtldm->atc_status = ATC_STATUS_OFF;
0765             }
0766         } else {
0767             if (rtldm->atc_status == ATC_STATUS_OFF) {
0768                 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
0769                           ATC_STATUS_ON);
0770                 rtldm->atc_status = ATC_STATUS_ON;
0771             }
0772         }
0773     }
0774 }
0775 
0776 static void rtl92ee_dm_init_txpower_tracking(struct ieee80211_hw *hw)
0777 {
0778     struct rtl_priv *rtlpriv = rtl_priv(hw);
0779     struct rtl_dm *dm = rtl_dm(rtlpriv);
0780     u8 path;
0781 
0782     dm->txpower_tracking = true;
0783     dm->default_ofdm_index = 30;
0784     dm->default_cck_index = 20;
0785 
0786     dm->swing_idx_cck_base = dm->default_cck_index;
0787     dm->cck_index = dm->default_cck_index;
0788 
0789     for (path = RF90_PATH_A; path < MAX_RF_PATH; path++) {
0790         dm->swing_idx_ofdm_base[path] = dm->default_ofdm_index;
0791         dm->ofdm_index[path] = dm->default_ofdm_index;
0792         dm->delta_power_index[path] = 0;
0793         dm->delta_power_index_last[path] = 0;
0794         dm->power_index_offset[path] = 0;
0795     }
0796 }
0797 
0798 void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
0799 {
0800     struct rtl_priv *rtlpriv = rtl_priv(hw);
0801     struct rate_adaptive *p_ra = &rtlpriv->ra;
0802 
0803     p_ra->ratr_state = DM_RATR_STA_INIT;
0804     p_ra->pre_ratr_state = DM_RATR_STA_INIT;
0805 
0806     if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
0807         rtlpriv->dm.useramask = true;
0808     else
0809         rtlpriv->dm.useramask = false;
0810 
0811     p_ra->ldpc_thres = 35;
0812     p_ra->use_ldpc = false;
0813     p_ra->high_rssi_thresh_for_ra = 50;
0814     p_ra->low_rssi_thresh_for_ra40m = 20;
0815 }
0816 
0817 static bool _rtl92ee_dm_ra_state_check(struct ieee80211_hw *hw,
0818                        s32 rssi, u8 *ratr_state)
0819 {
0820     struct rtl_priv *rtlpriv = rtl_priv(hw);
0821     struct rate_adaptive *p_ra = &rtlpriv->ra;
0822     const u8 go_up_gap = 5;
0823     u32 high_rssithresh_for_ra = p_ra->high_rssi_thresh_for_ra;
0824     u32 low_rssithresh_for_ra = p_ra->low_rssi_thresh_for_ra40m;
0825     u8 state;
0826 
0827     /* Threshold Adjustment:
0828      * when RSSI state trends to go up one or two levels,
0829      * make sure RSSI is high enough.
0830      * Here GoUpGap is added to solve
0831      * the boundary's level alternation issue.
0832      */
0833     switch (*ratr_state) {
0834     case DM_RATR_STA_INIT:
0835     case DM_RATR_STA_HIGH:
0836         break;
0837     case DM_RATR_STA_MIDDLE:
0838         high_rssithresh_for_ra += go_up_gap;
0839         break;
0840     case DM_RATR_STA_LOW:
0841         high_rssithresh_for_ra += go_up_gap;
0842         low_rssithresh_for_ra += go_up_gap;
0843         break;
0844     default:
0845         rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
0846             "wrong rssi level setting %d !\n", *ratr_state);
0847         break;
0848     }
0849 
0850     /* Decide RATRState by RSSI. */
0851     if (rssi > high_rssithresh_for_ra)
0852         state = DM_RATR_STA_HIGH;
0853     else if (rssi > low_rssithresh_for_ra)
0854         state = DM_RATR_STA_MIDDLE;
0855     else
0856         state = DM_RATR_STA_LOW;
0857 
0858     if (*ratr_state != state) {
0859         *ratr_state = state;
0860         return true;
0861     }
0862 
0863     return false;
0864 }
0865 
0866 static void rtl92ee_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
0867 {
0868     struct rtl_priv *rtlpriv = rtl_priv(hw);
0869     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0870     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
0871     struct rate_adaptive *p_ra = &rtlpriv->ra;
0872     struct ieee80211_sta *sta = NULL;
0873 
0874     if (is_hal_stop(rtlhal)) {
0875         rtl_dbg(rtlpriv, COMP_RATE, DBG_LOUD,
0876             "driver is going to unload\n");
0877         return;
0878     }
0879 
0880     if (!rtlpriv->dm.useramask) {
0881         rtl_dbg(rtlpriv, COMP_RATE, DBG_LOUD,
0882             "driver does not control rate adaptive mask\n");
0883         return;
0884     }
0885 
0886     if (mac->link_state == MAC80211_LINKED &&
0887         mac->opmode == NL80211_IFTYPE_STATION) {
0888         if (rtlpriv->dm.undec_sm_pwdb < p_ra->ldpc_thres) {
0889             p_ra->use_ldpc = true;
0890             p_ra->lower_rts_rate = true;
0891         } else if (rtlpriv->dm.undec_sm_pwdb >
0892                (p_ra->ldpc_thres - 5)) {
0893             p_ra->use_ldpc = false;
0894             p_ra->lower_rts_rate = false;
0895         }
0896         if (_rtl92ee_dm_ra_state_check(hw, rtlpriv->dm.undec_sm_pwdb,
0897                            &p_ra->ratr_state)) {
0898             rcu_read_lock();
0899             sta = rtl_find_sta(hw, mac->bssid);
0900             if (sta)
0901                 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
0902                                   p_ra->ratr_state,
0903                                   true);
0904             rcu_read_unlock();
0905 
0906             p_ra->pre_ratr_state = p_ra->ratr_state;
0907         }
0908     }
0909 }
0910 
0911 static void rtl92ee_dm_init_dynamic_atc_switch(struct ieee80211_hw *hw)
0912 {
0913     struct rtl_priv *rtlpriv = rtl_priv(hw);
0914 
0915     rtlpriv->dm.crystal_cap = rtlpriv->efuse.crystalcap;
0916 
0917     rtlpriv->dm.atc_status = rtl_get_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11));
0918     rtlpriv->dm.cfo_threshold = CFO_THRESHOLD_XTAL;
0919 }
0920 
0921 void rtl92ee_dm_init(struct ieee80211_hw *hw)
0922 {
0923     struct rtl_priv *rtlpriv = rtl_priv(hw);
0924     u32 cur_igvalue = rtl_get_bbreg(hw, DM_REG_IGI_A_11N, DM_BIT_IGI_11N);
0925 
0926     rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
0927 
0928     rtl_dm_diginit(hw, cur_igvalue);
0929     rtl92ee_dm_init_rate_adaptive_mask(hw);
0930     rtl92ee_dm_init_primary_cca_check(hw);
0931     rtl92ee_dm_init_edca_turbo(hw);
0932     rtl92ee_dm_init_txpower_tracking(hw);
0933     rtl92ee_dm_init_dynamic_atc_switch(hw);
0934 }
0935 
0936 static void rtl92ee_dm_common_info_self_update(struct ieee80211_hw *hw)
0937 {
0938     struct rtl_priv *rtlpriv = rtl_priv(hw);
0939     struct rtl_sta_info *drv_priv;
0940     u8 cnt = 0;
0941 
0942     rtlpriv->dm.one_entry_only = false;
0943 
0944     if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_STATION &&
0945         rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
0946         rtlpriv->dm.one_entry_only = true;
0947         return;
0948     }
0949 
0950     if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
0951         rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC ||
0952         rtlpriv->mac80211.opmode == NL80211_IFTYPE_MESH_POINT) {
0953         spin_lock_bh(&rtlpriv->locks.entry_list_lock);
0954         list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
0955             cnt++;
0956         }
0957         spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
0958 
0959         if (cnt == 1)
0960             rtlpriv->dm.one_entry_only = true;
0961     }
0962 }
0963 
0964 void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,
0965                     u8 rate, bool collision_state)
0966 {
0967     struct rtl_priv *rtlpriv = rtl_priv(hw);
0968 
0969     if (rate >= DESC92C_RATEMCS8  && rate <= DESC92C_RATEMCS12) {
0970         if (collision_state == 1) {
0971             if (rate == DESC92C_RATEMCS12) {
0972                 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
0973                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
0974                         0x07060501);
0975             } else if (rate == DESC92C_RATEMCS11) {
0976                 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
0977                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
0978                         0x07070605);
0979             } else if (rate == DESC92C_RATEMCS10) {
0980                 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
0981                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
0982                         0x08080706);
0983             } else if (rate == DESC92C_RATEMCS9) {
0984                 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
0985                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
0986                         0x08080707);
0987             } else {
0988                 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
0989                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
0990                         0x09090808);
0991             }
0992         } else {   /* collision_state == 0 */
0993             if (rate == DESC92C_RATEMCS12) {
0994                 rtl_write_dword(rtlpriv, REG_DARFRC,
0995                         0x05010000);
0996                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
0997                         0x09080706);
0998             } else if (rate == DESC92C_RATEMCS11) {
0999                 rtl_write_dword(rtlpriv, REG_DARFRC,
1000                         0x06050000);
1001                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1002                         0x09080807);
1003             } else if (rate == DESC92C_RATEMCS10) {
1004                 rtl_write_dword(rtlpriv, REG_DARFRC,
1005                         0x07060000);
1006                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1007                         0x0a090908);
1008             } else if (rate == DESC92C_RATEMCS9) {
1009                 rtl_write_dword(rtlpriv, REG_DARFRC,
1010                         0x07070000);
1011                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1012                         0x0a090808);
1013             } else {
1014                 rtl_write_dword(rtlpriv, REG_DARFRC,
1015                         0x08080000);
1016                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1017                         0x0b0a0909);
1018             }
1019         }
1020     } else {  /* MCS13~MCS15,  1SS, G-mode */
1021         if (collision_state == 1) {
1022             if (rate == DESC92C_RATEMCS15) {
1023                 rtl_write_dword(rtlpriv, REG_DARFRC,
1024                         0x00000000);
1025                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1026                         0x05040302);
1027             } else if (rate == DESC92C_RATEMCS14) {
1028                 rtl_write_dword(rtlpriv, REG_DARFRC,
1029                         0x00000000);
1030                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1031                         0x06050302);
1032             } else if (rate == DESC92C_RATEMCS13) {
1033                 rtl_write_dword(rtlpriv, REG_DARFRC,
1034                         0x00000000);
1035                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1036                         0x07060502);
1037             } else {
1038                 rtl_write_dword(rtlpriv, REG_DARFRC,
1039                         0x00000000);
1040                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1041                         0x06050402);
1042             }
1043         } else{   /* collision_state == 0 */
1044             if (rate == DESC92C_RATEMCS15) {
1045                 rtl_write_dword(rtlpriv, REG_DARFRC,
1046                         0x03020000);
1047                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1048                         0x07060504);
1049             } else if (rate == DESC92C_RATEMCS14) {
1050                 rtl_write_dword(rtlpriv, REG_DARFRC,
1051                         0x03020000);
1052                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1053                         0x08070605);
1054             } else if (rate == DESC92C_RATEMCS13) {
1055                 rtl_write_dword(rtlpriv, REG_DARFRC,
1056                         0x05020000);
1057                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1058                         0x09080706);
1059             } else {
1060                 rtl_write_dword(rtlpriv, REG_DARFRC,
1061                         0x04020000);
1062                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1063                         0x08070605);
1064             }
1065         }
1066     }
1067 }
1068 
1069 void rtl92ee_dm_watchdog(struct ieee80211_hw *hw)
1070 {
1071     struct rtl_priv *rtlpriv = rtl_priv(hw);
1072     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1073     bool fw_current_inpsmode = false;
1074     bool fw_ps_awake = true;
1075 
1076     rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1077                       (u8 *)(&fw_current_inpsmode));
1078     rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1079                       (u8 *)(&fw_ps_awake));
1080     if (ppsc->p2p_ps_info.p2p_ps_mode)
1081         fw_ps_awake = false;
1082 
1083     spin_lock(&rtlpriv->locks.rf_ps_lock);
1084     if ((ppsc->rfpwr_state == ERFON) &&
1085         ((!fw_current_inpsmode) && fw_ps_awake) &&
1086         (!ppsc->rfchange_inprogress)) {
1087         rtl92ee_dm_common_info_self_update(hw);
1088         rtl92ee_dm_false_alarm_counter_statistics(hw);
1089         rtl92ee_dm_check_rssi_monitor(hw);
1090         rtl92ee_dm_dig(hw);
1091         rtl92ee_dm_adaptivity(hw);
1092         rtl92ee_dm_cck_packet_detection_thresh(hw);
1093         rtl92ee_dm_refresh_rate_adaptive_mask(hw);
1094         rtl92ee_dm_check_edca_turbo(hw);
1095         rtl92ee_dm_dynamic_atc_switch(hw);
1096         rtl92ee_dm_dynamic_primary_cca_ckeck(hw);
1097     }
1098     spin_unlock(&rtlpriv->locks.rf_ps_lock);
1099 }
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