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0002
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0004 #ifndef __RTL92E_DEF_H__
0005 #define __RTL92E_DEF_H__
0006
0007 #define RX_DESC_NUM_92E 512
0008
0009 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
0010 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
0011 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
0012
0013 #define RX_MPDU_QUEUE 0
0014
0015 #define IS_HT_RATE(_rate) \
0016 (_rate >= DESC92C_RATEMCS0)
0017 #define IS_CCK_RATE(_rate) \
0018 (_rate >= DESC92C_RATE1M && _rate <= DESC92C_RATE11M)
0019 #define IS_OFDM_RATE(_rate) \
0020 (_rate >= DESC92C_RATE6M && _rate <= DESC92C_RATE54M)
0021
0022 enum version_8192e {
0023 VERSION_TEST_CHIP_2T2R_8192E = 0x0024,
0024 VERSION_NORMAL_CHIP_2T2R_8192E = 0x102C,
0025 VERSION_UNKNOWN = 0xFF,
0026 };
0027
0028 enum rtl_desc_qsel {
0029 QSLT_BK = 0x2,
0030 QSLT_BE = 0x0,
0031 QSLT_VI = 0x5,
0032 QSLT_VO = 0x7,
0033 QSLT_BEACON = 0x10,
0034 QSLT_HIGH = 0x11,
0035 QSLT_MGNT = 0x12,
0036 QSLT_CMD = 0x13,
0037 };
0038
0039 enum rtl_desc92c_rate {
0040 DESC92C_RATE1M = 0x00,
0041 DESC92C_RATE2M = 0x01,
0042 DESC92C_RATE5_5M = 0x02,
0043 DESC92C_RATE11M = 0x03,
0044
0045 DESC92C_RATE6M = 0x04,
0046 DESC92C_RATE9M = 0x05,
0047 DESC92C_RATE12M = 0x06,
0048 DESC92C_RATE18M = 0x07,
0049 DESC92C_RATE24M = 0x08,
0050 DESC92C_RATE36M = 0x09,
0051 DESC92C_RATE48M = 0x0a,
0052 DESC92C_RATE54M = 0x0b,
0053
0054 DESC92C_RATEMCS0 = 0x0c,
0055 DESC92C_RATEMCS1 = 0x0d,
0056 DESC92C_RATEMCS2 = 0x0e,
0057 DESC92C_RATEMCS3 = 0x0f,
0058 DESC92C_RATEMCS4 = 0x10,
0059 DESC92C_RATEMCS5 = 0x11,
0060 DESC92C_RATEMCS6 = 0x12,
0061 DESC92C_RATEMCS7 = 0x13,
0062 DESC92C_RATEMCS8 = 0x14,
0063 DESC92C_RATEMCS9 = 0x15,
0064 DESC92C_RATEMCS10 = 0x16,
0065 DESC92C_RATEMCS11 = 0x17,
0066 DESC92C_RATEMCS12 = 0x18,
0067 DESC92C_RATEMCS13 = 0x19,
0068 DESC92C_RATEMCS14 = 0x1a,
0069 DESC92C_RATEMCS15 = 0x1b,
0070 };
0071 #endif