rtlwifi/rtl8192de/sw.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003
0004 #include "../wifi.h"
0005 #include "../core.h"
0006 #include "../pci.h"
0007 #include "../base.h"
0008 #include "reg.h"
0009 #include "def.h"
0010 #include "phy.h"
0011 #include "dm.h"
0012 #include "hw.h"
0013 #include "sw.h"
0014 #include "trx.h"
0015 #include "led.h"
0016
0017 #include <linux/module.h>
0018
0019 static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw)
0020 {
0021     struct rtl_priv *rtlpriv = rtl_priv(hw);
0022     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0023
0024     /*close ASPM for AMD defaultly */
0025     rtlpci->const_amdpci_aspm = 0;
0026
0027     /*
0028      * ASPM PS mode.
0029      * 0 - Disable ASPM,
0030      * 1 - Enable ASPM without Clock Req,
0031      * 2 - Enable ASPM with Clock Req,
0032      * 3 - Alwyas Enable ASPM with Clock Req,
0033      * 4 - Always Enable ASPM without Clock Req.
0034      * set defult to RTL8192CE:3 RTL8192E:2
0035      * */
0036     rtlpci->const_pci_aspm = 3;
0037
0038     /*Setting for PCI-E device */
0039     rtlpci->const_devicepci_aspm_setting = 0x03;
0040
0041     /*Setting for PCI-E bridge */
0042     rtlpci->const_hostpci_aspm_setting = 0x02;
0043
0044     /*
0045      * In Hw/Sw Radio Off situation.
0046      * 0 - Default,
0047      * 1 - From ASPM setting without low Mac Pwr,
0048      * 2 - From ASPM setting with low Mac Pwr,
0049      * 3 - Bus D3
0050      * set default to RTL8192CE:0 RTL8192SE:2
0051      */
0052     rtlpci->const_hwsw_rfoff_d3 = 0;
0053
0054     /*
0055      * This setting works for those device with
0056      * backdoor ASPM setting such as EPHY setting.
0057      * 0 - Not support ASPM,
0058      * 1 - Support ASPM,
0059      * 2 - According to chipset.
0060      */
0061     rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
0062 }
0063
0064 static int rtl92d_init_sw_vars(struct ieee80211_hw *hw)
0065 {
0066     int err;
0067     u8 tid;
0068     struct rtl_priv *rtlpriv = rtl_priv(hw);
0069     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0070     char *fw_name = "rtlwifi/rtl8192defw.bin";
0071
0072     rtlpriv->dm.dm_initialgain_enable = true;
0073     rtlpriv->dm.dm_flag = 0;
0074     rtlpriv->dm.disable_framebursting = false;
0075     rtlpriv->dm.thermalvalue = 0;
0076     rtlpriv->dm.useramask = true;
0077
0078     /* dual mac */
0079     if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
0080         rtlpriv->phy.current_channel = 36;
0081     else
0082         rtlpriv->phy.current_channel = 1;
0083
0084     if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
0085         rtlpriv->rtlhal.disable_amsdu_8k = true;
0086         /* No long RX - reduce fragmentation */
0087         rtlpci->rxbuffersize = 4096;
0088     }
0089
0090     rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
0091
0092     rtlpci->receive_config = (
0093             RCR_APPFCS
0094             | RCR_AMF
0095             | RCR_ADF
0096             | RCR_APP_MIC
0097             | RCR_APP_ICV
0098             | RCR_AICV
0099             | RCR_ACRC32
0100             | RCR_AB
0101             | RCR_AM
0102             | RCR_APM
0103             | RCR_APP_PHYST_RXFF
0104             | RCR_HTC_LOC_CTRL
0105     );
0106
0107     rtlpci->irq_mask[0] = (u32) (
0108             IMR_ROK
0109             | IMR_VODOK
0110             | IMR_VIDOK
0111             | IMR_BEDOK
0112             | IMR_BKDOK
0113             | IMR_MGNTDOK
0114             | IMR_HIGHDOK
0115             | IMR_BDOK
0116             | IMR_RDU
0117             | IMR_RXFOVW
0118     );
0119
0120     rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD);
0121
0122     /* for LPS & IPS */
0123     rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
0124     rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
0125     rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
0126     if (!rtlpriv->psc.inactiveps)
0127         pr_info("Power Save off (module option)\n");
0128     if (!rtlpriv->psc.fwctrl_lps)
0129         pr_info("FW Power Save off (module option)\n");
0130     rtlpriv->psc.reg_fwctrl_lps = 3;
0131     rtlpriv->psc.reg_max_lps_awakeintvl = 5;
0132     /* for ASPM, you can close aspm through
0133      * set const_support_pciaspm = 0 */
0134     rtl92d_init_aspm_vars(hw);
0135
0136     if (rtlpriv->psc.reg_fwctrl_lps == 1)
0137         rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
0138     else if (rtlpriv->psc.reg_fwctrl_lps == 2)
0139         rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
0140     else if (rtlpriv->psc.reg_fwctrl_lps == 3)
0141         rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
0142
0143     /* for early mode */
0144     rtlpriv->rtlhal.earlymode_enable = false;
0145     for (tid = 0; tid < 8; tid++)
0146         skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
0147
0148     /* for firmware buf */
0149     rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
0150     if (!rtlpriv->rtlhal.pfirmware) {
0151         pr_err("Can't alloc buffer for fw\n");
0152         return 1;
0153     }
0154
0155     rtlpriv->max_fw_size = 0x8000;
0156     pr_info("Driver for Realtek RTL8192DE WLAN interface\n");
0157     pr_info("Loading firmware file %s\n", fw_name);
0158
0159     /* request fw */
0160     err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
0161                       rtlpriv->io.dev, GFP_KERNEL, hw,
0162                       rtl_fw_cb);
0163     if (err) {
0164         pr_err("Failed to request firmware!\n");
0165         vfree(rtlpriv->rtlhal.pfirmware);
0166         rtlpriv->rtlhal.pfirmware = NULL;
0167         return 1;
0168     }
0169
0170     return 0;
0171 }
0172
0173 static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw)
0174 {
0175     struct rtl_priv *rtlpriv = rtl_priv(hw);
0176     u8 tid;
0177
0178     if (rtlpriv->rtlhal.pfirmware) {
0179         vfree(rtlpriv->rtlhal.pfirmware);
0180         rtlpriv->rtlhal.pfirmware = NULL;
0181     }
0182     for (tid = 0; tid < 8; tid++)
0183         skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]);
0184 }
0185
0186 static struct rtl_hal_ops rtl8192de_hal_ops = {
0187     .init_sw_vars = rtl92d_init_sw_vars,
0188     .deinit_sw_vars = rtl92d_deinit_sw_vars,
0189     .read_eeprom_info = rtl92de_read_eeprom_info,
0190     .interrupt_recognized = rtl92de_interrupt_recognized,
0191     .hw_init = rtl92de_hw_init,
0192     .hw_disable = rtl92de_card_disable,
0193     .hw_suspend = rtl92de_suspend,
0194     .hw_resume = rtl92de_resume,
0195     .enable_interrupt = rtl92de_enable_interrupt,
0196     .disable_interrupt = rtl92de_disable_interrupt,
0197     .set_network_type = rtl92de_set_network_type,
0198     .set_chk_bssid = rtl92de_set_check_bssid,
0199     .set_qos = rtl92de_set_qos,
0200     .set_bcn_reg = rtl92de_set_beacon_related_registers,
0201     .set_bcn_intv = rtl92de_set_beacon_interval,
0202     .update_interrupt_mask = rtl92de_update_interrupt_mask,
0203     .get_hw_reg = rtl92de_get_hw_reg,
0204     .set_hw_reg = rtl92de_set_hw_reg,
0205     .update_rate_tbl = rtl92de_update_hal_rate_tbl,
0206     .fill_tx_desc = rtl92de_tx_fill_desc,
0207     .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc,
0208     .query_rx_desc = rtl92de_rx_query_desc,
0209     .set_channel_access = rtl92de_update_channel_access_setting,
0210     .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking,
0211     .set_bw_mode = rtl92d_phy_set_bw_mode,
0212     .switch_channel = rtl92d_phy_sw_chnl,
0213     .dm_watchdog = rtl92d_dm_watchdog,
0214     .scan_operation_backup = rtl_phy_scan_operation_backup,
0215     .set_rf_power_state = rtl92d_phy_set_rf_power_state,
0216     .led_control = rtl92de_led_control,
0217     .set_desc = rtl92de_set_desc,
0218     .get_desc = rtl92de_get_desc,
0219     .is_tx_desc_closed = rtl92de_is_tx_desc_closed,
0220     .tx_polling = rtl92de_tx_polling,
0221     .enable_hw_sec = rtl92de_enable_hw_security_config,
0222     .set_key = rtl92de_set_key,
0223     .init_sw_leds = rtl92de_init_sw_leds,
0224     .get_bbreg = rtl92d_phy_query_bb_reg,
0225     .set_bbreg = rtl92d_phy_set_bb_reg,
0226     .get_rfreg = rtl92d_phy_query_rf_reg,
0227     .set_rfreg = rtl92d_phy_set_rf_reg,
0228     .linked_set_reg = rtl92d_linked_set_reg,
0229     .get_btc_status = rtl_btc_status_false,
0230 };
0231
0232 static struct rtl_mod_params rtl92de_mod_params = {
0233     .sw_crypto = false,
0234     .inactiveps = true,
0235     .swctrl_lps = true,
0236     .fwctrl_lps = false,
0237     .aspm_support = 1,
0238     .debug_level = 0,
0239     .debug_mask = 0,
0240 };
0241
0242 static const struct rtl_hal_cfg rtl92de_hal_cfg = {
0243     .bar_id = 2,
0244     .write_readback = true,
0245     .name = "rtl8192de",
0246     .ops = &rtl8192de_hal_ops,
0247     .mod_params = &rtl92de_mod_params,
0248
0249     .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
0250     .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
0251     .maps[SYS_CLK] = REG_SYS_CLKR,
0252     .maps[MAC_RCR_AM] = RCR_AM,
0253     .maps[MAC_RCR_AB] = RCR_AB,
0254     .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
0255     .maps[MAC_RCR_ACF] = RCR_ACF,
0256     .maps[MAC_RCR_AAP] = RCR_AAP,
0257
0258     .maps[EFUSE_TEST] = REG_EFUSE_TEST,
0259     .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
0260     .maps[EFUSE_CLK] = 0,   /* just for 92se */
0261     .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
0262     .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
0263     .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
0264     .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
0265     .maps[EFUSE_ANA8M] = 0, /* just for 92se */
0266     .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
0267     .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
0268     .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
0269
0270     .maps[RWCAM] = REG_CAMCMD,
0271     .maps[WCAMI] = REG_CAMWRITE,
0272     .maps[RCAMO] = REG_CAMREAD,
0273     .maps[CAMDBG] = REG_CAMDBG,
0274     .maps[SECR] = REG_SECCFG,
0275     .maps[SEC_CAM_NONE] = CAM_NONE,
0276     .maps[SEC_CAM_WEP40] = CAM_WEP40,
0277     .maps[SEC_CAM_TKIP] = CAM_TKIP,
0278     .maps[SEC_CAM_AES] = CAM_AES,
0279     .maps[SEC_CAM_WEP104] = CAM_WEP104,
0280
0281     .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
0282     .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
0283     .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
0284     .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
0285     .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
0286     .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
0287     .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
0288     .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
0289     .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
0290     .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
0291     .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
0292     .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
0293     .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
0294     .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
0295     .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
0296     .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
0297
0298     .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
0299     .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
0300     .maps[RTL_IMR_BCNINT] = IMR_BCNINT,
0301     .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
0302     .maps[RTL_IMR_RDU] = IMR_RDU,
0303     .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
0304     .maps[RTL_IMR_BDOK] = IMR_BDOK,
0305     .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
0306     .maps[RTL_IMR_TBDER] = IMR_TBDER,
0307     .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
0308     .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
0309     .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
0310     .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
0311     .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
0312     .maps[RTL_IMR_VODOK] = IMR_VODOK,
0313     .maps[RTL_IMR_ROK] = IMR_ROK,
0314     .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
0315
0316     .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
0317     .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
0318     .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
0319     .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
0320     .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
0321     .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
0322     .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
0323     .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
0324     .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
0325     .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
0326     .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
0327     .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
0328
0329     .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
0330     .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
0331 };
0332
0333 static const struct pci_device_id rtl92de_pci_ids[] = {
0334     {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)},
0335     {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)},
0336     {},
0337 };
0338
0339 MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids);
0340
0341 MODULE_AUTHOR("lizhaoming   <chaoming_li@realsil.com.cn>");
0342 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
0343 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
0344 MODULE_LICENSE("GPL");
0345 MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless");
0346 MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin");
0347
0348 module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444);
0349 module_param_named(debug_level, rtl92de_mod_params.debug_level, int, 0644);
0350 module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444);
0351 module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444);
0352 module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444);
0353 module_param_named(aspm, rtl92de_mod_params.aspm_support, int, 0444);
0354 module_param_named(debug_mask, rtl92de_mod_params.debug_mask, ullong, 0644);
0355 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
0356 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
0357 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
0358 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");
0359 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
0360 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
0361 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
0362
0363 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
0364
0365 static struct pci_driver rtl92de_driver = {
0366     .name = KBUILD_MODNAME,
0367     .id_table = rtl92de_pci_ids,
0368     .probe = rtl_pci_probe,
0369     .remove = rtl_pci_disconnect,
0370     .driver.pm = &rtlwifi_pm_ops,
0371 };
0372
0373 /* add global spin lock to solve the problem that
0374  * Dul mac register operation on the same time */
0375 DEFINE_SPINLOCK(globalmutex_power);
0376 DEFINE_SPINLOCK(globalmutex_for_fwdownload);
0377 DEFINE_SPINLOCK(globalmutex_for_power_and_efuse);
0378
0379 static int __init rtl92de_module_init(void)
0380 {
0381     int ret = 0;
0382
0383     ret = pci_register_driver(&rtl92de_driver);
0384     if (ret)
0385         WARN_ONCE(true, "rtl8192de: No device found\n");
0386     return ret;
0387 }
0388
0389 static void __exit rtl92de_module_exit(void)
0390 {
0391     pci_unregister_driver(&rtl92de_driver);
0392 }
0393
0394 module_init(rtl92de_module_init);
0395 module_exit(rtl92de_module_exit);