rtlwifi/rtl8192de/rf.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003
0004 #include "../wifi.h"
0005 #include "reg.h"
0006 #include "def.h"
0007 #include "phy.h"
0008 #include "rf.h"
0009 #include "dm.h"
0010 #include "hw.h"
0011
0012 void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
0013 {
0014     struct rtl_priv *rtlpriv = rtl_priv(hw);
0015     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0016     u8 rfpath;
0017
0018     switch (bandwidth) {
0019     case HT_CHANNEL_WIDTH_20:
0020         for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
0021             rtlphy->rfreg_chnlval[rfpath] = ((rtlphy->rfreg_chnlval
0022                     [rfpath] & 0xfffff3ff) | 0x0400);
0023             rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) |
0024                       BIT(11), 0x01);
0025
0026             rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
0027                 "20M RF 0x18 = 0x%x\n",
0028                 rtlphy->rfreg_chnlval[rfpath]);
0029         }
0030
0031         break;
0032     case HT_CHANNEL_WIDTH_20_40:
0033         for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
0034             rtlphy->rfreg_chnlval[rfpath] =
0035                 ((rtlphy->rfreg_chnlval[rfpath] & 0xfffff3ff));
0036             rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT(11),
0037                       0x00);
0038             rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
0039                 "40M RF 0x18 = 0x%x\n",
0040                 rtlphy->rfreg_chnlval[rfpath]);
0041         }
0042         break;
0043     default:
0044         pr_err("unknown bandwidth: %#X\n", bandwidth);
0045         break;
0046     }
0047 }
0048
0049 void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
0050                        u8 *ppowerlevel)
0051 {
0052     struct rtl_priv *rtlpriv = rtl_priv(hw);
0053     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0054     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
0055     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0056     u32 tx_agc[2] = {0, 0}, tmpval;
0057     bool turbo_scanoff = false;
0058     u8 idx1, idx2;
0059     u8 *ptr;
0060
0061     if (rtlefuse->eeprom_regulatory != 0)
0062         turbo_scanoff = true;
0063     if (mac->act_scanning) {
0064         tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
0065         tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
0066         if (turbo_scanoff) {
0067             for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
0068                 tx_agc[idx1] = ppowerlevel[idx1] |
0069                     (ppowerlevel[idx1] << 8) |
0070                     (ppowerlevel[idx1] << 16) |
0071                     (ppowerlevel[idx1] << 24);
0072             }
0073         }
0074     } else {
0075         for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
0076             tx_agc[idx1] = ppowerlevel[idx1] |
0077                 (ppowerlevel[idx1] << 8) |
0078                 (ppowerlevel[idx1] << 16) |
0079                 (ppowerlevel[idx1] << 24);
0080         }
0081         if (rtlefuse->eeprom_regulatory == 0) {
0082             tmpval = (rtlphy->mcs_offset[0][6]) +
0083                 (rtlphy->mcs_offset[0][7] << 8);
0084             tx_agc[RF90_PATH_A] += tmpval;
0085             tmpval = (rtlphy->mcs_offset[0][14]) +
0086                 (rtlphy->mcs_offset[0][15] << 24);
0087             tx_agc[RF90_PATH_B] += tmpval;
0088         }
0089     }
0090
0091     for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
0092         ptr = (u8 *) (&(tx_agc[idx1]));
0093         for (idx2 = 0; idx2 < 4; idx2++) {
0094             if (*ptr > RF6052_MAX_TX_PWR)
0095                 *ptr = RF6052_MAX_TX_PWR;
0096             ptr++;
0097         }
0098     }
0099
0100     tmpval = tx_agc[RF90_PATH_A] & 0xff;
0101     rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
0102     RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0103         "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n",
0104         tmpval, RTXAGC_A_CCK1_MCS32);
0105     tmpval = tx_agc[RF90_PATH_A] >> 8;
0106     rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
0107     RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0108         "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n",
0109         tmpval, RTXAGC_B_CCK11_A_CCK2_11);
0110     tmpval = tx_agc[RF90_PATH_B] >> 24;
0111     rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
0112     RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0113         "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n",
0114         tmpval, RTXAGC_B_CCK11_A_CCK2_11);
0115     tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
0116     rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
0117     RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0118         "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",
0119         tmpval, RTXAGC_B_CCK1_55_MCS32);
0120 }
0121
0122 static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw,
0123                        u8 *ppowerlevel, u8 channel,
0124                        u32 *ofdmbase, u32 *mcsbase)
0125 {
0126     struct rtl_priv *rtlpriv = rtl_priv(hw);
0127     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0128     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0129     u32 powerbase0, powerbase1;
0130     u8 legacy_pwrdiff, ht20_pwrdiff;
0131     u8 i, powerlevel[2];
0132
0133     for (i = 0; i < 2; i++) {
0134         powerlevel[i] = ppowerlevel[i];
0135         legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
0136         powerbase0 = powerlevel[i] + legacy_pwrdiff;
0137         powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
0138             (powerbase0 << 8) | powerbase0;
0139         *(ofdmbase + i) = powerbase0;
0140         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0141             " [OFDM power base index rf(%c) = 0x%x]\n",
0142             i == 0 ? 'A' : 'B', *(ofdmbase + i));
0143     }
0144
0145     for (i = 0; i < 2; i++) {
0146         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
0147             ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1];
0148             powerlevel[i] += ht20_pwrdiff;
0149         }
0150         powerbase1 = powerlevel[i];
0151         powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) |
0152                  (powerbase1 << 8) | powerbase1;
0153         *(mcsbase + i) = powerbase1;
0154         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0155             " [MCS power base index rf(%c) = 0x%x]\n",
0156             i == 0 ? 'A' : 'B', *(mcsbase + i));
0157     }
0158 }
0159
0160 static u8 _rtl92d_phy_get_chnlgroup_bypg(u8 chnlindex)
0161 {
0162     u8 group;
0163     u8 channel_info[59] = {
0164         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
0165         36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
0166         60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
0167         114, 116, 118, 120, 122, 124, 126, 128, 130, 132,
0168         134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
0169         161, 163, 165
0170     };
0171
0172     if (channel_info[chnlindex] <= 3)   /* Chanel 1-3 */
0173         group = 0;
0174     else if (channel_info[chnlindex] <= 9)  /* Channel 4-9 */
0175         group = 1;
0176     else if (channel_info[chnlindex] <= 14) /* Channel 10-14 */
0177         group = 2;
0178     else if (channel_info[chnlindex] <= 64)
0179         group = 6;
0180     else if (channel_info[chnlindex] <= 140)
0181         group = 7;
0182     else
0183         group = 8;
0184     return group;
0185 }
0186
0187 static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
0188                                u8 channel, u8 index,
0189                                u32 *powerbase0,
0190                                u32 *powerbase1,
0191                                u32 *p_outwriteval)
0192 {
0193     struct rtl_priv *rtlpriv = rtl_priv(hw);
0194     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0195     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0196     u8 i, chnlgroup = 0, pwr_diff_limit[4];
0197     u32 writeval = 0, customer_limit, rf;
0198
0199     for (rf = 0; rf < 2; rf++) {
0200         switch (rtlefuse->eeprom_regulatory) {
0201         case 0:
0202             chnlgroup = 0;
0203             writeval = rtlphy->mcs_offset
0204                     [chnlgroup][index +
0205                     (rf ? 8 : 0)] + ((index < 2) ?
0206                     powerbase0[rf] :
0207                     powerbase1[rf]);
0208             RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0209                 "RTK better performance, writeval(%c) = 0x%x\n",
0210                 rf == 0 ? 'A' : 'B', writeval);
0211             break;
0212         case 1:
0213             if (rtlphy->pwrgroup_cnt == 1)
0214                 chnlgroup = 0;
0215             if (rtlphy->pwrgroup_cnt >= MAX_PG_GROUP) {
0216                 chnlgroup = _rtl92d_phy_get_chnlgroup_bypg(
0217                                 channel - 1);
0218                 if (rtlphy->current_chan_bw ==
0219                     HT_CHANNEL_WIDTH_20)
0220                     chnlgroup++;
0221                 else
0222                     chnlgroup += 4;
0223                 writeval = rtlphy->mcs_offset
0224                         [chnlgroup][index +
0225                         (rf ? 8 : 0)] + ((index < 2) ?
0226                         powerbase0[rf] :
0227                         powerbase1[rf]);
0228                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0229                     "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
0230                     rf == 0 ? 'A' : 'B', writeval);
0231             }
0232             break;
0233         case 2:
0234             writeval = ((index < 2) ? powerbase0[rf] :
0235                    powerbase1[rf]);
0236             RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0237                 "Better regulatory, writeval(%c) = 0x%x\n",
0238                 rf == 0 ? 'A' : 'B', writeval);
0239             break;
0240         case 3:
0241             chnlgroup = 0;
0242             if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
0243                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0244                     "customer's limit, 40MHz rf(%c) = 0x%x\n",
0245                     rf == 0 ? 'A' : 'B',
0246                     rtlefuse->pwrgroup_ht40[rf]
0247                     [channel - 1]);
0248             } else {
0249                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0250                     "customer's limit, 20MHz rf(%c) = 0x%x\n",
0251                     rf == 0 ? 'A' : 'B',
0252                     rtlefuse->pwrgroup_ht20[rf]
0253                     [channel - 1]);
0254             }
0255             for (i = 0; i < 4; i++) {
0256                 pwr_diff_limit[i] = (u8)((rtlphy->mcs_offset
0257                     [chnlgroup][index + (rf ? 8 : 0)] &
0258                     (0x7f << (i * 8))) >> (i * 8));
0259                 if (rtlphy->current_chan_bw ==
0260                     HT_CHANNEL_WIDTH_20_40) {
0261                     if (pwr_diff_limit[i] >
0262                         rtlefuse->pwrgroup_ht40[rf]
0263                        [channel - 1])
0264                         pwr_diff_limit[i] =
0265                             rtlefuse->pwrgroup_ht40
0266                             [rf][channel - 1];
0267                 } else {
0268                     if (pwr_diff_limit[i] >
0269                         rtlefuse->pwrgroup_ht20[rf][
0270                         channel - 1])
0271                         pwr_diff_limit[i] =
0272                            rtlefuse->pwrgroup_ht20[rf]
0273                            [channel - 1];
0274                 }
0275             }
0276             customer_limit = (pwr_diff_limit[3] << 24) |
0277                      (pwr_diff_limit[2] << 16) |
0278                      (pwr_diff_limit[1] << 8) |
0279                      (pwr_diff_limit[0]);
0280             RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0281                 "Customer's limit rf(%c) = 0x%x\n",
0282                 rf == 0 ? 'A' : 'B', customer_limit);
0283             writeval = customer_limit + ((index < 2) ?
0284                    powerbase0[rf] : powerbase1[rf]);
0285             RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0286                 "Customer, writeval rf(%c)= 0x%x\n",
0287                 rf == 0 ? 'A' : 'B', writeval);
0288             break;
0289         default:
0290             chnlgroup = 0;
0291             writeval = rtlphy->mcs_offset[chnlgroup][index +
0292                    (rf ? 8 : 0)] + ((index < 2) ?
0293                    powerbase0[rf] : powerbase1[rf]);
0294             RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0295                 "RTK better performance, writeval rf(%c) = 0x%x\n",
0296                 rf == 0 ? 'A' : 'B', writeval);
0297             break;
0298         }
0299         *(p_outwriteval + rf) = writeval;
0300     }
0301 }
0302
0303 static void _rtl92d_write_ofdm_power_reg(struct ieee80211_hw *hw,
0304                      u8 index, u32 *pvalue)
0305 {
0306     struct rtl_priv *rtlpriv = rtl_priv(hw);
0307     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0308     static u16 regoffset_a[6] = {
0309         RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
0310         RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
0311         RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
0312     };
0313     static u16 regoffset_b[6] = {
0314         RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
0315         RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
0316         RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
0317     };
0318     u8 i, rf, pwr_val[4];
0319     u32 writeval;
0320     u16 regoffset;
0321
0322     for (rf = 0; rf < 2; rf++) {
0323         writeval = pvalue[rf];
0324         for (i = 0; i < 4; i++) {
0325             pwr_val[i] = (u8) ((writeval & (0x7f <<
0326                      (i * 8))) >> (i * 8));
0327             if (pwr_val[i] > RF6052_MAX_TX_PWR)
0328                 pwr_val[i] = RF6052_MAX_TX_PWR;
0329         }
0330         writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
0331                (pwr_val[1] << 8) | pwr_val[0];
0332         if (rf == 0)
0333             regoffset = regoffset_a[index];
0334         else
0335             regoffset = regoffset_b[index];
0336         rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
0337         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0338             "Set 0x%x = %08x\n", regoffset, writeval);
0339         if (((get_rf_type(rtlphy) == RF_2T2R) &&
0340             (regoffset == RTXAGC_A_MCS15_MCS12 ||
0341             regoffset == RTXAGC_B_MCS15_MCS12)) ||
0342             ((get_rf_type(rtlphy) != RF_2T2R) &&
0343             (regoffset == RTXAGC_A_MCS07_MCS04 ||
0344             regoffset == RTXAGC_B_MCS07_MCS04))) {
0345             writeval = pwr_val[3];
0346             if (regoffset == RTXAGC_A_MCS15_MCS12 ||
0347                 regoffset == RTXAGC_A_MCS07_MCS04)
0348                 regoffset = 0xc90;
0349             if (regoffset == RTXAGC_B_MCS15_MCS12 ||
0350                 regoffset == RTXAGC_B_MCS07_MCS04)
0351                 regoffset = 0xc98;
0352             for (i = 0; i < 3; i++) {
0353                 if (i != 2)
0354                     writeval = (writeval > 8) ?
0355                            (writeval - 8) : 0;
0356                 else
0357                     writeval = (writeval > 6) ?
0358                            (writeval - 6) : 0;
0359                 rtl_write_byte(rtlpriv, (u32) (regoffset + i),
0360                            (u8) writeval);
0361             }
0362         }
0363     }
0364 }
0365
0366 void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
0367                     u8 *ppowerlevel, u8 channel)
0368 {
0369     u32 writeval[2], powerbase0[2], powerbase1[2];
0370     u8 index;
0371
0372     _rtl92d_phy_get_power_base(hw, ppowerlevel, channel,
0373             &powerbase0[0], &powerbase1[0]);
0374     for (index = 0; index < 6; index++) {
0375         _rtl92d_get_txpower_writeval_by_regulatory(hw,
0376                 channel, index, &powerbase0[0],
0377                 &powerbase1[0], &writeval[0]);
0378         _rtl92d_write_ofdm_power_reg(hw, index, &writeval[0]);
0379     }
0380 }
0381
0382 bool rtl92d_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0)
0383 {
0384     struct rtl_priv *rtlpriv = rtl_priv(hw);
0385     struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
0386     u8 u1btmp;
0387     u8 direct = bmac0 ? BIT(3) | BIT(2) : BIT(3);
0388     u8 mac_reg = bmac0 ? REG_MAC1 : REG_MAC0;
0389     u8 mac_on_bit = bmac0 ? MAC1_ON : MAC0_ON;
0390     bool bresult = true; /* true: need to enable BB/RF power */
0391
0392     rtlhal->during_mac0init_radiob = false;
0393     rtlhal->during_mac1init_radioa = false;
0394     rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "===>\n");
0395     /* MAC0 Need PHY1 load radio_b.txt . Driver use DBI to write. */
0396     u1btmp = rtl_read_byte(rtlpriv, mac_reg);
0397     if (!(u1btmp & mac_on_bit)) {
0398         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable BB & RF\n");
0399         /* Enable BB and RF power */
0400         rtl92de_write_dword_dbi(hw, REG_SYS_ISO_CTRL,
0401             rtl92de_read_dword_dbi(hw, REG_SYS_ISO_CTRL, direct) |
0402                 BIT(29) | BIT(16) | BIT(17), direct);
0403     } else {
0404         /* We think if MAC1 is ON,then radio_a.txt
0405          * and radio_b.txt has been load. */
0406         bresult = false;
0407     }
0408     rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<===\n");
0409     return bresult;
0410
0411 }
0412
0413 void rtl92d_phy_powerdown_anotherphy(struct ieee80211_hw *hw, bool bmac0)
0414 {
0415     struct rtl_priv *rtlpriv = rtl_priv(hw);
0416     struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
0417     u8 u1btmp;
0418     u8 direct = bmac0 ? BIT(3) | BIT(2) : BIT(3);
0419     u8 mac_reg = bmac0 ? REG_MAC1 : REG_MAC0;
0420     u8 mac_on_bit = bmac0 ? MAC1_ON : MAC0_ON;
0421
0422     rtlhal->during_mac0init_radiob = false;
0423     rtlhal->during_mac1init_radioa = false;
0424     rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
0425     /* check MAC0 enable or not again now, if
0426      * enabled, not power down radio A. */
0427     u1btmp = rtl_read_byte(rtlpriv, mac_reg);
0428     if (!(u1btmp & mac_on_bit)) {
0429         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "power down\n");
0430         /* power down RF radio A according to YuNan's advice. */
0431         rtl92de_write_dword_dbi(hw, RFPGA0_XA_LSSIPARAMETER,
0432                     0x00000000, direct);
0433     }
0434     rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
0435 }
0436
0437 bool rtl92d_phy_rf6052_config(struct ieee80211_hw *hw)
0438 {
0439     struct rtl_priv *rtlpriv = rtl_priv(hw);
0440     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0441     bool rtstatus = true;
0442     struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
0443     u32 u4_regvalue = 0;
0444     u8 rfpath;
0445     struct bb_reg_def *pphyreg;
0446     bool mac1_initradioa_first = false, mac0_initradiob_first = false;
0447     bool need_pwrdown_radioa = false, need_pwrdown_radiob = false;
0448     bool true_bpath = false;
0449
0450     if (rtlphy->rf_type == RF_1T1R)
0451         rtlphy->num_total_rfpath = 1;
0452     else
0453         rtlphy->num_total_rfpath = 2;
0454
0455     /* Single phy mode: use radio_a radio_b config path_A path_B */
0456     /* seperately by MAC0, and MAC1 needn't configure RF; */
0457     /* Dual PHY mode:MAC0 use radio_a config 1st phy path_A, */
0458     /* MAC1 use radio_b config 2nd PHY path_A. */
0459     /* DMDP,MAC0 on G band,MAC1 on A band. */
0460     if (rtlhal->macphymode == DUALMAC_DUALPHY) {
0461         if (rtlhal->current_bandtype == BAND_ON_2_4G &&
0462             rtlhal->interfaceindex == 0) {
0463             /* MAC0 needs PHY1 load radio_b.txt.
0464              * Driver use DBI to write. */
0465             if (rtl92d_phy_enable_anotherphy(hw, true)) {
0466                 rtlphy->num_total_rfpath = 2;
0467                 mac0_initradiob_first = true;
0468             } else {
0469                 /* We think if MAC1 is ON,then radio_a.txt and
0470                  * radio_b.txt has been load. */
0471                 return rtstatus;
0472             }
0473         } else if (rtlhal->current_bandtype == BAND_ON_5G &&
0474                rtlhal->interfaceindex == 1) {
0475             /* MAC1 needs PHY0 load radio_a.txt.
0476              * Driver use DBI to write. */
0477             if (rtl92d_phy_enable_anotherphy(hw, false)) {
0478                 rtlphy->num_total_rfpath = 2;
0479                 mac1_initradioa_first = true;
0480             } else {
0481                 /* We think if MAC0 is ON,then radio_a.txt and
0482                  * radio_b.txt has been load. */
0483                 return rtstatus;
0484             }
0485         } else if (rtlhal->interfaceindex == 1) {
0486             /* MAC0 enabled, only init radia B.   */
0487             true_bpath = true;
0488         }
0489     }
0490
0491     for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
0492         /* Mac1 use PHY0 write */
0493         if (mac1_initradioa_first) {
0494             if (rfpath == RF90_PATH_A) {
0495                 rtlhal->during_mac1init_radioa = true;
0496                 need_pwrdown_radioa = true;
0497             } else if (rfpath == RF90_PATH_B) {
0498                 rtlhal->during_mac1init_radioa = false;
0499                 mac1_initradioa_first = false;
0500                 rfpath = RF90_PATH_A;
0501                 true_bpath = true;
0502                 rtlphy->num_total_rfpath = 1;
0503             }
0504         } else if (mac0_initradiob_first) {
0505             /* Mac0 use PHY1 write */
0506             if (rfpath == RF90_PATH_A)
0507                 rtlhal->during_mac0init_radiob = false;
0508             if (rfpath == RF90_PATH_B) {
0509                 rtlhal->during_mac0init_radiob = true;
0510                 mac0_initradiob_first = false;
0511                 need_pwrdown_radiob = true;
0512                 rfpath = RF90_PATH_A;
0513                 true_bpath = true;
0514                 rtlphy->num_total_rfpath = 1;
0515             }
0516         }
0517         pphyreg = &rtlphy->phyreg_def[rfpath];
0518         switch (rfpath) {
0519         case RF90_PATH_A:
0520         case RF90_PATH_C:
0521             u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
0522                             BRFSI_RFENV);
0523             break;
0524         case RF90_PATH_B:
0525         case RF90_PATH_D:
0526             u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
0527                 BRFSI_RFENV << 16);
0528             break;
0529         }
0530         rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
0531         udelay(1);
0532         rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
0533         udelay(1);
0534         /* Set bit number of Address and Data for RF register */
0535         /* Set 1 to 4 bits for 8255 */
0536         rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
0537                   B3WIREADDRESSLENGTH, 0x0);
0538         udelay(1);
0539         /* Set 0 to 12  bits for 8255 */
0540         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
0541         udelay(1);
0542         switch (rfpath) {
0543         case RF90_PATH_A:
0544             if (true_bpath)
0545                 rtstatus = rtl92d_phy_config_rf_with_headerfile(
0546                         hw, radiob_txt,
0547                         (enum radio_path)rfpath);
0548             else
0549                 rtstatus = rtl92d_phy_config_rf_with_headerfile(
0550                          hw, radioa_txt,
0551                          (enum radio_path)rfpath);
0552             break;
0553         case RF90_PATH_B:
0554             rtstatus =
0555                 rtl92d_phy_config_rf_with_headerfile(hw, radiob_txt,
0556                         (enum radio_path) rfpath);
0557             break;
0558         case RF90_PATH_C:
0559             break;
0560         case RF90_PATH_D:
0561             break;
0562         }
0563         switch (rfpath) {
0564         case RF90_PATH_A:
0565         case RF90_PATH_C:
0566             rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV,
0567                       u4_regvalue);
0568             break;
0569         case RF90_PATH_B:
0570         case RF90_PATH_D:
0571             rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
0572                       u4_regvalue);
0573             break;
0574         }
0575         if (!rtstatus) {
0576             rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0577                 "Radio[%d] Fail!!\n", rfpath);
0578             goto phy_rf_cfg_fail;
0579         }
0580
0581     }
0582
0583     /* check MAC0 enable or not again, if enabled,
0584      * not power down radio A. */
0585     /* check MAC1 enable or not again, if enabled,
0586      * not power down radio B. */
0587     if (need_pwrdown_radioa)
0588         rtl92d_phy_powerdown_anotherphy(hw, false);
0589     else if (need_pwrdown_radiob)
0590         rtl92d_phy_powerdown_anotherphy(hw, true);
0591     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "<---\n");
0592     return rtstatus;
0593
0594 phy_rf_cfg_fail:
0595     return rtstatus;
0596 }