rtlwifi/rtl8192de/phy.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003
0004 #ifndef __RTL92D_PHY_H__
0005 #define __RTL92D_PHY_H__
0006
0007 #define MAX_PRECMD_CNT              16
0008 #define MAX_RFDEPENDCMD_CNT         16
0009 #define MAX_POSTCMD_CNT             16
0010
0011 #define MAX_DOZE_WAITING_TIMES_9x       64
0012
0013 #define RT_CANNOT_IO(hw)            false
0014 #define HIGHPOWER_RADIOA_ARRAYLEN       22
0015
0016 #define MAX_TOLERANCE               5
0017
0018 #define APK_BB_REG_NUM              5
0019 #define APK_AFE_REG_NUM             16
0020 #define APK_CURVE_REG_NUM           4
0021 #define PATH_NUM                2
0022
0023 #define LOOP_LIMIT              5
0024 #define MAX_STALL_TIME              50
0025 #define ANTENNA_DIVERSITY_VALUE         0x80
0026 #define MAX_TXPWR_IDX_NMODE_92S         63
0027 #define RESET_CNT_LIMIT             3
0028
0029 #define IQK_ADDA_REG_NUM            16
0030 #define IQK_BB_REG_NUM              10
0031 #define IQK_BB_REG_NUM_test         6
0032 #define IQK_MAC_REG_NUM             4
0033 #define RX_INDEX_MAPPING_NUM            15
0034
0035 #define IQK_DELAY_TIME              1
0036
0037 #define CT_OFFSET_MAC_ADDR          0X16
0038
0039 #define CT_OFFSET_CCK_TX_PWR_IDX        0x5A
0040 #define CT_OFFSET_HT401S_TX_PWR_IDX     0x60
0041 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF    0x66
0042 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF      0x69
0043 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF      0x6C
0044
0045 #define CT_OFFSET_HT40_MAX_PWR_OFFSET       0x6F
0046 #define CT_OFFSET_HT20_MAX_PWR_OFFSET       0x72
0047
0048 #define CT_OFFSET_CHANNEL_PLAH          0x75
0049 #define CT_OFFSET_THERMAL_METER         0x78
0050 #define CT_OFFSET_RF_OPTION         0x79
0051 #define CT_OFFSET_VERSION           0x7E
0052 #define CT_OFFSET_CUSTOMER_ID           0x7F
0053
0054 enum swchnlcmd_id {
0055     CMDID_END,
0056     CMDID_SET_TXPOWEROWER_LEVEL,
0057     CMDID_BBREGWRITE10,
0058     CMDID_WRITEPORT_ULONG,
0059     CMDID_WRITEPORT_USHORT,
0060     CMDID_WRITEPORT_UCHAR,
0061     CMDID_RF_WRITEREG,
0062 };
0063
0064 struct swchnlcmd {
0065     enum swchnlcmd_id cmdid;
0066     u32 para1;
0067     u32 para2;
0068     u32 msdelay;
0069 };
0070
0071 enum baseband_config_type {
0072     BASEBAND_CONFIG_PHY_REG = 0,
0073     BASEBAND_CONFIG_AGC_TAB = 1,
0074 };
0075
0076 enum rf_content {
0077     radioa_txt = 0,
0078     radiob_txt = 1,
0079     radioc_txt = 2,
0080     radiod_txt = 3
0081 };
0082
0083 static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
0084                              unsigned long *flag)
0085 {
0086     struct rtl_priv *rtlpriv = rtl_priv(hw);
0087
0088     if (rtlpriv->rtlhal.interfaceindex == 1)
0089         spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag);
0090 }
0091
0092 static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
0093                              unsigned long *flag)
0094 {
0095     struct rtl_priv *rtlpriv = rtl_priv(hw);
0096
0097     if (rtlpriv->rtlhal.interfaceindex == 1)
0098         spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock,
0099             *flag);
0100 }
0101
0102 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw,
0103                 u32 regaddr, u32 bitmask);
0104 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
0105                u32 regaddr, u32 bitmask, u32 data);
0106 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
0107                 enum radio_path rfpath, u32 regaddr,
0108                 u32 bitmask);
0109 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw,
0110                enum radio_path rfpath, u32 regaddr,
0111                u32 bitmask, u32 data);
0112 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw);
0113 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw);
0114 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw);
0115 bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
0116                       enum radio_path rfpath);
0117 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
0118 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
0119 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
0120                 enum nl80211_channel_type ch_type);
0121 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw);
0122 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
0123                       enum rf_content content,
0124                       enum radio_path rfpath);
0125 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
0126 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
0127                    enum rf_pwrstate rfpwr_state);
0128
0129 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw);
0130 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw);
0131 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl);
0132 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw);
0133 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw);
0134 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw);
0135 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw);
0136 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw);
0137 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta);
0138 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
0139 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw);
0140 void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
0141                        unsigned long *flag);
0142 void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
0143                        unsigned long *flag);
0144 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl);
0145 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel);
0146
0147 #endif