rtlwifi/rtl8192de/phy.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003
0004 #include "../wifi.h"
0005 #include "../pci.h"
0006 #include "../ps.h"
0007 #include "../core.h"
0008 #include "reg.h"
0009 #include "def.h"
0010 #include "phy.h"
0011 #include "rf.h"
0012 #include "dm.h"
0013 #include "table.h"
0014 #include "sw.h"
0015 #include "hw.h"
0016
0017 #define MAX_RF_IMR_INDEX            12
0018 #define MAX_RF_IMR_INDEX_NORMAL         13
0019 #define RF_REG_NUM_FOR_C_CUT_5G         6
0020 #define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA  7
0021 #define RF_REG_NUM_FOR_C_CUT_2G         5
0022 #define RF_CHNL_NUM_5G              19
0023 #define RF_CHNL_NUM_5G_40M          17
0024 #define TARGET_CHNL_NUM_5G          221
0025 #define TARGET_CHNL_NUM_2G          14
0026 #define CV_CURVE_CNT                64
0027
0028 static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
0029     0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
0030 };
0031
0032 static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
0033     RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
0034 };
0035
0036 static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
0037     RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
0038 };
0039
0040 static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
0041     0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
0042 };
0043
0044 static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
0045     BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
0046     BIT(10) | BIT(9),
0047     BIT(18) | BIT(17) | BIT(16) | BIT(1),
0048     BIT(2) | BIT(1),
0049     BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
0050 };
0051
0052 static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
0053     36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
0054     112, 116, 120, 124, 128, 132, 136, 140
0055 };
0056
0057 static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
0058     38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
0059     118, 122, 126, 130, 134, 138
0060 };
0061 static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
0062     {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
0063     {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
0064     {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
0065     {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
0066     {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
0067 };
0068
0069 static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
0070     {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
0071     {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
0072     {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
0073 };
0074
0075 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
0076
0077 static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
0078     {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
0079     {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
0080     {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
0081 };
0082
0083 /* [mode][patha+b][reg] */
0084 static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
0085     {
0086         /* channel 1-14. */
0087         {
0088             0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
0089             0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
0090         },
0091         /* path 36-64 */
0092         {
0093             0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
0094             0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
0095             0x32c9a
0096         },
0097         /* 100 -165 */
0098         {
0099             0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
0100             0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
0101         }
0102     }
0103 };
0104
0105 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
0106
0107 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
0108
0109 static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
0110     25141, 25116, 25091, 25066, 25041,
0111     25016, 24991, 24966, 24941, 24917,
0112     24892, 24867, 24843, 24818, 24794,
0113     24770, 24765, 24721, 24697, 24672,
0114     24648, 24624, 24600, 24576, 24552,
0115     24528, 24504, 24480, 24457, 24433,
0116     24409, 24385, 24362, 24338, 24315,
0117     24291, 24268, 24245, 24221, 24198,
0118     24175, 24151, 24128, 24105, 24082,
0119     24059, 24036, 24013, 23990, 23967,
0120     23945, 23922, 23899, 23876, 23854,
0121     23831, 23809, 23786, 23764, 23741,
0122     23719, 23697, 23674, 23652, 23630,
0123     23608, 23586, 23564, 23541, 23519,
0124     23498, 23476, 23454, 23432, 23410,
0125     23388, 23367, 23345, 23323, 23302,
0126     23280, 23259, 23237, 23216, 23194,
0127     23173, 23152, 23130, 23109, 23088,
0128     23067, 23046, 23025, 23003, 22982,
0129     22962, 22941, 22920, 22899, 22878,
0130     22857, 22837, 22816, 22795, 22775,
0131     22754, 22733, 22713, 22692, 22672,
0132     22652, 22631, 22611, 22591, 22570,
0133     22550, 22530, 22510, 22490, 22469,
0134     22449, 22429, 22409, 22390, 22370,
0135     22350, 22336, 22310, 22290, 22271,
0136     22251, 22231, 22212, 22192, 22173,
0137     22153, 22134, 22114, 22095, 22075,
0138     22056, 22037, 22017, 21998, 21979,
0139     21960, 21941, 21921, 21902, 21883,
0140     21864, 21845, 21826, 21807, 21789,
0141     21770, 21751, 21732, 21713, 21695,
0142     21676, 21657, 21639, 21620, 21602,
0143     21583, 21565, 21546, 21528, 21509,
0144     21491, 21473, 21454, 21436, 21418,
0145     21400, 21381, 21363, 21345, 21327,
0146     21309, 21291, 21273, 21255, 21237,
0147     21219, 21201, 21183, 21166, 21148,
0148     21130, 21112, 21095, 21077, 21059,
0149     21042, 21024, 21007, 20989, 20972,
0150     25679, 25653, 25627, 25601, 25575,
0151     25549, 25523, 25497, 25471, 25446,
0152     25420, 25394, 25369, 25343, 25318,
0153     25292, 25267, 25242, 25216, 25191,
0154     25166
0155 };
0156
0157 /* channel 1~14 */
0158 static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
0159     26084, 26030, 25976, 25923, 25869, 25816, 25764,
0160     25711, 25658, 25606, 25554, 25502, 25451, 25328
0161 };
0162
0163 static const u8 channel_all[59] = {
0164     1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
0165     36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
0166     60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
0167     114, 116, 118, 120, 122, 124, 126, 128, 130,
0168     132, 134, 136, 138, 140, 149, 151, 153, 155,
0169     157, 159, 161, 163, 165
0170 };
0171
0172 static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
0173 {
0174     u32 i = ffs(bitmask);
0175
0176     return i ? i - 1 : 32;
0177 }
0178
0179 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
0180 {
0181     struct rtl_priv *rtlpriv = rtl_priv(hw);
0182     struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
0183     u32 returnvalue, originalvalue, bitshift;
0184
0185     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
0186         regaddr, bitmask);
0187     if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
0188         u8 dbi_direct = 0;
0189
0190         /* mac1 use phy0 read radio_b. */
0191         /* mac0 use phy1 read radio_b. */
0192         if (rtlhal->during_mac1init_radioa)
0193             dbi_direct = BIT(3);
0194         else if (rtlhal->during_mac0init_radiob)
0195             dbi_direct = BIT(3) | BIT(2);
0196         originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
0197             dbi_direct);
0198     } else {
0199         originalvalue = rtl_read_dword(rtlpriv, regaddr);
0200     }
0201     bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
0202     returnvalue = (originalvalue & bitmask) >> bitshift;
0203     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0204         "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
0205         bitmask, regaddr, originalvalue);
0206     return returnvalue;
0207 }
0208
0209 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
0210                u32 regaddr, u32 bitmask, u32 data)
0211 {
0212     struct rtl_priv *rtlpriv = rtl_priv(hw);
0213     struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
0214     u8 dbi_direct = 0;
0215     u32 originalvalue, bitshift;
0216
0217     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0218         "regaddr(%#x), bitmask(%#x), data(%#x)\n",
0219         regaddr, bitmask, data);
0220     if (rtlhal->during_mac1init_radioa)
0221         dbi_direct = BIT(3);
0222     else if (rtlhal->during_mac0init_radiob)
0223         /* mac0 use phy1 write radio_b. */
0224         dbi_direct = BIT(3) | BIT(2);
0225     if (bitmask != MASKDWORD) {
0226         if (rtlhal->during_mac1init_radioa ||
0227             rtlhal->during_mac0init_radiob)
0228             originalvalue = rtl92de_read_dword_dbi(hw,
0229                     (u16) regaddr,
0230                     dbi_direct);
0231         else
0232             originalvalue = rtl_read_dword(rtlpriv, regaddr);
0233         bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
0234         data = ((originalvalue & (~bitmask)) | (data << bitshift));
0235     }
0236     if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
0237         rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
0238     else
0239         rtl_write_dword(rtlpriv, regaddr, data);
0240     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0241         "regaddr(%#x), bitmask(%#x), data(%#x)\n",
0242         regaddr, bitmask, data);
0243 }
0244
0245 static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
0246                       enum radio_path rfpath, u32 offset)
0247 {
0248
0249     struct rtl_priv *rtlpriv = rtl_priv(hw);
0250     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0251     struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
0252     u32 newoffset;
0253     u32 tmplong, tmplong2;
0254     u8 rfpi_enable = 0;
0255     u32 retvalue;
0256
0257     newoffset = offset;
0258     tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
0259     if (rfpath == RF90_PATH_A)
0260         tmplong2 = tmplong;
0261     else
0262         tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
0263     tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
0264         (newoffset << 23) | BLSSIREADEDGE;
0265     rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
0266         tmplong & (~BLSSIREADEDGE));
0267     udelay(10);
0268     rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
0269     udelay(50);
0270     udelay(50);
0271     rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
0272         tmplong | BLSSIREADEDGE);
0273     udelay(10);
0274     if (rfpath == RF90_PATH_A)
0275         rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
0276                   BIT(8));
0277     else if (rfpath == RF90_PATH_B)
0278         rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
0279                   BIT(8));
0280     if (rfpi_enable)
0281         retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
0282             BLSSIREADBACKDATA);
0283     else
0284         retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
0285             BLSSIREADBACKDATA);
0286     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",
0287         rfpath, pphyreg->rf_rb, retvalue);
0288     return retvalue;
0289 }
0290
0291 static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
0292                     enum radio_path rfpath,
0293                     u32 offset, u32 data)
0294 {
0295     u32 data_and_addr;
0296     u32 newoffset;
0297     struct rtl_priv *rtlpriv = rtl_priv(hw);
0298     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0299     struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
0300
0301     newoffset = offset;
0302     /* T65 RF */
0303     data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
0304     rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
0305     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
0306         rfpath, pphyreg->rf3wire_offset, data_and_addr);
0307 }
0308
0309 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
0310                 enum radio_path rfpath, u32 regaddr, u32 bitmask)
0311 {
0312     struct rtl_priv *rtlpriv = rtl_priv(hw);
0313     u32 original_value, readback_value, bitshift;
0314
0315     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0316         "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
0317         regaddr, rfpath, bitmask);
0318     spin_lock(&rtlpriv->locks.rf_lock);
0319     original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
0320     bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
0321     readback_value = (original_value & bitmask) >> bitshift;
0322     spin_unlock(&rtlpriv->locks.rf_lock);
0323     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0324         "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
0325         regaddr, rfpath, bitmask, original_value);
0326     return readback_value;
0327 }
0328
0329 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
0330     u32 regaddr, u32 bitmask, u32 data)
0331 {
0332     struct rtl_priv *rtlpriv = rtl_priv(hw);
0333     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0334     u32 original_value, bitshift;
0335
0336     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0337         "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
0338         regaddr, bitmask, data, rfpath);
0339     if (bitmask == 0)
0340         return;
0341     spin_lock(&rtlpriv->locks.rf_lock);
0342     if (rtlphy->rf_mode != RF_OP_BY_FW) {
0343         if (bitmask != RFREG_OFFSET_MASK) {
0344             original_value = _rtl92d_phy_rf_serial_read(hw,
0345                 rfpath, regaddr);
0346             bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
0347             data = ((original_value & (~bitmask)) |
0348                 (data << bitshift));
0349         }
0350         _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
0351     }
0352     spin_unlock(&rtlpriv->locks.rf_lock);
0353     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0354         "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
0355         regaddr, bitmask, data, rfpath);
0356 }
0357
0358 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
0359 {
0360     struct rtl_priv *rtlpriv = rtl_priv(hw);
0361     u32 i;
0362     u32 arraylength;
0363     u32 *ptrarray;
0364
0365     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
0366     arraylength = MAC_2T_ARRAYLENGTH;
0367     ptrarray = rtl8192de_mac_2tarray;
0368     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n");
0369     for (i = 0; i < arraylength; i = i + 2)
0370         rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
0371     if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
0372         /* improve 2-stream TX EVM */
0373         /* rtl_write_byte(rtlpriv, 0x14,0x71); */
0374         /* AMPDU aggregation number 9 */
0375         /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
0376         rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
0377     } else {
0378         /* 92D need to test to decide the num. */
0379         rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
0380     }
0381     return true;
0382 }
0383
0384 static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
0385 {
0386     struct rtl_priv *rtlpriv = rtl_priv(hw);
0387     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0388
0389     /* RF Interface Sowrtware Control */
0390     /* 16 LSBs if read 32-bit from 0x870 */
0391     rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
0392     /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
0393     rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
0394     /* 16 LSBs if read 32-bit from 0x874 */
0395     rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
0396     /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
0397
0398     rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
0399     /* RF Interface Readback Value */
0400     /* 16 LSBs if read 32-bit from 0x8E0 */
0401     rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
0402     /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
0403     rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
0404     /* 16 LSBs if read 32-bit from 0x8E4 */
0405     rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
0406     /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
0407     rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
0408
0409     /* RF Interface Output (and Enable) */
0410     /* 16 LSBs if read 32-bit from 0x860 */
0411     rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
0412     /* 16 LSBs if read 32-bit from 0x864 */
0413     rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
0414
0415     /* RF Interface (Output and)  Enable */
0416     /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
0417     rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
0418     /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
0419     rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
0420
0421     /* Addr of LSSI. Wirte RF register by driver */
0422     /* LSSI Parameter */
0423     rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
0424                  RFPGA0_XA_LSSIPARAMETER;
0425     rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
0426                  RFPGA0_XB_LSSIPARAMETER;
0427
0428     /* RF parameter */
0429     /* BB Band Select */
0430     rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
0431     rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
0432     rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
0433     rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
0434
0435     /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
0436     /* Tx gain stage */
0437     rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0438     /* Tx gain stage */
0439     rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0440     /* Tx gain stage */
0441     rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0442     /* Tx gain stage */
0443     rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0444
0445     /* Tranceiver A~D HSSI Parameter-1 */
0446     /* wire control parameter1 */
0447     rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
0448     /* wire control parameter1 */
0449     rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
0450
0451     /* Tranceiver A~D HSSI Parameter-2 */
0452     /* wire control parameter2 */
0453     rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
0454     /* wire control parameter2 */
0455     rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
0456
0457     /* RF switch Control */
0458     /* TR/Ant switch control */
0459     rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
0460     rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
0461     rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
0462     rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
0463
0464     /* AGC control 1 */
0465     rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
0466     rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
0467     rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
0468     rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
0469
0470     /* AGC control 2  */
0471     rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
0472     rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
0473     rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
0474     rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
0475
0476     /* RX AFE control 1 */
0477     rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
0478     rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
0479     rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
0480     rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
0481
0482     /*RX AFE control 1 */
0483     rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
0484     rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
0485     rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
0486     rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
0487
0488     /* Tx AFE control 1 */
0489     rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
0490     rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
0491     rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
0492     rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
0493
0494     /* Tx AFE control 2 */
0495     rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
0496     rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
0497     rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
0498     rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
0499
0500     /* Tranceiver LSSI Readback SI mode */
0501     rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
0502     rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
0503     rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
0504     rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
0505
0506     /* Tranceiver LSSI Readback PI mode */
0507     rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
0508     rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
0509 }
0510
0511 static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
0512     u8 configtype)
0513 {
0514     int i;
0515     u32 *phy_regarray_table;
0516     u32 *agctab_array_table = NULL;
0517     u32 *agctab_5garray_table;
0518     u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
0519     struct rtl_priv *rtlpriv = rtl_priv(hw);
0520     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0521
0522     /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */
0523     if (rtlhal->interfaceindex == 0) {
0524         agctab_arraylen = AGCTAB_ARRAYLENGTH;
0525         agctab_array_table = rtl8192de_agctab_array;
0526         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0527             " ===> phy:MAC0, Rtl819XAGCTAB_Array\n");
0528     } else {
0529         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
0530             agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
0531             agctab_array_table = rtl8192de_agctab_2garray;
0532             rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0533                 " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n");
0534         } else {
0535             agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
0536             agctab_5garray_table = rtl8192de_agctab_5garray;
0537             rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0538                 " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n");
0539
0540         }
0541     }
0542     phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
0543     phy_regarray_table = rtl8192de_phy_reg_2tarray;
0544     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0545         " ===> phy:Rtl819XPHY_REG_Array_PG\n");
0546     if (configtype == BASEBAND_CONFIG_PHY_REG) {
0547         for (i = 0; i < phy_reg_arraylen; i = i + 2) {
0548             rtl_addr_delay(phy_regarray_table[i]);
0549             rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
0550                       phy_regarray_table[i + 1]);
0551             udelay(1);
0552             rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0553                 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
0554                 phy_regarray_table[i],
0555                 phy_regarray_table[i + 1]);
0556         }
0557     } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
0558         if (rtlhal->interfaceindex == 0) {
0559             for (i = 0; i < agctab_arraylen; i = i + 2) {
0560                 rtl_set_bbreg(hw, agctab_array_table[i],
0561                     MASKDWORD,
0562                     agctab_array_table[i + 1]);
0563                 /* Add 1us delay between BB/RF register
0564                  * setting. */
0565                 udelay(1);
0566                 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0567                     "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
0568                     agctab_array_table[i],
0569                     agctab_array_table[i + 1]);
0570             }
0571             rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0572                 "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n");
0573         } else {
0574             if (rtlhal->current_bandtype == BAND_ON_2_4G) {
0575                 for (i = 0; i < agctab_arraylen; i = i + 2) {
0576                     rtl_set_bbreg(hw, agctab_array_table[i],
0577                         MASKDWORD,
0578                         agctab_array_table[i + 1]);
0579                     /* Add 1us delay between BB/RF register
0580                      * setting. */
0581                     udelay(1);
0582                     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0583                         "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
0584                         agctab_array_table[i],
0585                         agctab_array_table[i + 1]);
0586                 }
0587                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0588                     "Load Rtl819XAGCTAB_2GArray\n");
0589             } else {
0590                 for (i = 0; i < agctab_5garraylen; i = i + 2) {
0591                     rtl_set_bbreg(hw,
0592                         agctab_5garray_table[i],
0593                         MASKDWORD,
0594                         agctab_5garray_table[i + 1]);
0595                     /* Add 1us delay between BB/RF registeri
0596                      * setting. */
0597                     udelay(1);
0598                     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0599                         "The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
0600                         agctab_5garray_table[i],
0601                         agctab_5garray_table[i + 1]);
0602                 }
0603                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0604                     "Load Rtl819XAGCTAB_5GArray\n");
0605             }
0606         }
0607     }
0608     return true;
0609 }
0610
0611 static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
0612                            u32 regaddr, u32 bitmask,
0613                            u32 data)
0614 {
0615     struct rtl_priv *rtlpriv = rtl_priv(hw);
0616     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0617     int index;
0618
0619     if (regaddr == RTXAGC_A_RATE18_06)
0620         index = 0;
0621     else if (regaddr == RTXAGC_A_RATE54_24)
0622         index = 1;
0623     else if (regaddr == RTXAGC_A_CCK1_MCS32)
0624         index = 6;
0625     else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
0626         index = 7;
0627     else if (regaddr == RTXAGC_A_MCS03_MCS00)
0628         index = 2;
0629     else if (regaddr == RTXAGC_A_MCS07_MCS04)
0630         index = 3;
0631     else if (regaddr == RTXAGC_A_MCS11_MCS08)
0632         index = 4;
0633     else if (regaddr == RTXAGC_A_MCS15_MCS12)
0634         index = 5;
0635     else if (regaddr == RTXAGC_B_RATE18_06)
0636         index = 8;
0637     else if (regaddr == RTXAGC_B_RATE54_24)
0638         index = 9;
0639     else if (regaddr == RTXAGC_B_CCK1_55_MCS32)
0640         index = 14;
0641     else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
0642         index = 15;
0643     else if (regaddr == RTXAGC_B_MCS03_MCS00)
0644         index = 10;
0645     else if (regaddr == RTXAGC_B_MCS07_MCS04)
0646         index = 11;
0647     else if (regaddr == RTXAGC_B_MCS11_MCS08)
0648         index = 12;
0649     else if (regaddr == RTXAGC_B_MCS15_MCS12)
0650         index = 13;
0651     else
0652         return;
0653
0654     rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
0655     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0656         "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
0657         rtlphy->pwrgroup_cnt, index,
0658         rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);
0659     if (index == 13)
0660         rtlphy->pwrgroup_cnt++;
0661 }
0662
0663 static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
0664     u8 configtype)
0665 {
0666     struct rtl_priv *rtlpriv = rtl_priv(hw);
0667     int i;
0668     u32 *phy_regarray_table_pg;
0669     u16 phy_regarray_pg_len;
0670
0671     phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
0672     phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
0673     if (configtype == BASEBAND_CONFIG_PHY_REG) {
0674         for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
0675             rtl_addr_delay(phy_regarray_table_pg[i]);
0676             _rtl92d_store_pwrindex_diffrate_offset(hw,
0677                 phy_regarray_table_pg[i],
0678                 phy_regarray_table_pg[i + 1],
0679                 phy_regarray_table_pg[i + 2]);
0680         }
0681     } else {
0682         rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,
0683             "configtype != BaseBand_Config_PHY_REG\n");
0684     }
0685     return true;
0686 }
0687
0688 static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
0689 {
0690     struct rtl_priv *rtlpriv = rtl_priv(hw);
0691     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0692     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0693     bool rtstatus;
0694
0695     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
0696     rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
0697         BASEBAND_CONFIG_PHY_REG);
0698     if (!rtstatus) {
0699         pr_err("Write BB Reg Fail!!\n");
0700         return false;
0701     }
0702
0703     /* if (rtlphy->rf_type == RF_1T2R) {
0704      *      _rtl92c_phy_bb_config_1t(hw);
0705      *     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
0706      *} */
0707
0708     if (rtlefuse->autoload_failflag == false) {
0709         rtlphy->pwrgroup_cnt = 0;
0710         rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
0711             BASEBAND_CONFIG_PHY_REG);
0712     }
0713     if (!rtstatus) {
0714         pr_err("BB_PG Reg Fail!!\n");
0715         return false;
0716     }
0717     rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
0718         BASEBAND_CONFIG_AGC_TAB);
0719     if (!rtstatus) {
0720         pr_err("AGC Table Fail\n");
0721         return false;
0722     }
0723     rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
0724         RFPGA0_XA_HSSIPARAMETER2, 0x200));
0725
0726     return true;
0727 }
0728
0729 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
0730 {
0731     struct rtl_priv *rtlpriv = rtl_priv(hw);
0732     u16 regval;
0733     u32 regvaldw;
0734     u8 value;
0735
0736     _rtl92d_phy_init_bb_rf_register_definition(hw);
0737     regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
0738     rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
0739                regval | BIT(13) | BIT(0) | BIT(1));
0740     rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
0741     rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
0742     /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
0743     value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
0744     rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
0745         RF_SDMRSTB);
0746     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
0747         FEN_DIO_PCIE | FEN_BB_GLB_RSTN | FEN_BBRSTB);
0748     rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
0749     if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
0750         regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
0751         rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
0752     }
0753
0754     return _rtl92d_phy_bb_config(hw);
0755 }
0756
0757 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
0758 {
0759     return rtl92d_phy_rf6052_config(hw);
0760 }
0761
0762 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
0763                       enum rf_content content,
0764                       enum radio_path rfpath)
0765 {
0766     int i;
0767     u32 *radioa_array_table;
0768     u32 *radiob_array_table;
0769     u16 radioa_arraylen, radiob_arraylen;
0770     struct rtl_priv *rtlpriv = rtl_priv(hw);
0771
0772     radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
0773     radioa_array_table = rtl8192de_radioa_2tarray;
0774     radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
0775     radiob_array_table = rtl8192de_radiob_2tarray;
0776     if (rtlpriv->efuse.internal_pa_5g[0]) {
0777         radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
0778         radioa_array_table = rtl8192de_radioa_2t_int_paarray;
0779     }
0780     if (rtlpriv->efuse.internal_pa_5g[1]) {
0781         radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
0782         radiob_array_table = rtl8192de_radiob_2t_int_paarray;
0783     }
0784     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0785         "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n");
0786     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0787         "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n");
0788     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
0789
0790     /* this only happens when DMDP, mac0 start on 2.4G,
0791      * mac1 start on 5G, mac 0 has to set phy0&phy1
0792      * pathA or mac1 has to set phy0&phy1 pathA */
0793     if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
0794         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0795             " ===> althougth Path A, we load radiob.txt\n");
0796         radioa_arraylen = radiob_arraylen;
0797         radioa_array_table = radiob_array_table;
0798     }
0799     switch (rfpath) {
0800     case RF90_PATH_A:
0801         for (i = 0; i < radioa_arraylen; i = i + 2) {
0802             rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
0803                     RFREG_OFFSET_MASK,
0804                     radioa_array_table[i + 1]);
0805         }
0806         break;
0807     case RF90_PATH_B:
0808         for (i = 0; i < radiob_arraylen; i = i + 2) {
0809             rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
0810                     RFREG_OFFSET_MASK,
0811                     radiob_array_table[i + 1]);
0812         }
0813         break;
0814     case RF90_PATH_C:
0815     case RF90_PATH_D:
0816         pr_err("switch case %#x not processed\n", rfpath);
0817         break;
0818     }
0819     return true;
0820 }
0821
0822 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
0823 {
0824     struct rtl_priv *rtlpriv = rtl_priv(hw);
0825     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0826
0827     rtlphy->default_initialgain[0] =
0828         (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
0829     rtlphy->default_initialgain[1] =
0830         (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
0831     rtlphy->default_initialgain[2] =
0832         (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
0833     rtlphy->default_initialgain[3] =
0834         (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
0835     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0836         "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
0837         rtlphy->default_initialgain[0],
0838         rtlphy->default_initialgain[1],
0839         rtlphy->default_initialgain[2],
0840         rtlphy->default_initialgain[3]);
0841     rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
0842                           MASKBYTE0);
0843     rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
0844                           MASKDWORD);
0845     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0846         "Default framesync (0x%x) = 0x%x\n",
0847         ROFDM0_RXDETECTOR3, rtlphy->framesync);
0848 }
0849
0850 static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
0851     u8 *cckpowerlevel, u8 *ofdmpowerlevel)
0852 {
0853     struct rtl_priv *rtlpriv = rtl_priv(hw);
0854     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0855     struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
0856     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0857     u8 index = (channel - 1);
0858
0859     /* 1. CCK */
0860     if (rtlhal->current_bandtype == BAND_ON_2_4G) {
0861         /* RF-A */
0862         cckpowerlevel[RF90_PATH_A] =
0863                  rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
0864         /* RF-B */
0865         cckpowerlevel[RF90_PATH_B] =
0866                  rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
0867     } else {
0868         cckpowerlevel[RF90_PATH_A] = 0;
0869         cckpowerlevel[RF90_PATH_B] = 0;
0870     }
0871     /* 2. OFDM for 1S or 2S */
0872     if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
0873         /*  Read HT 40 OFDM TX power */
0874         ofdmpowerlevel[RF90_PATH_A] =
0875             rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
0876         ofdmpowerlevel[RF90_PATH_B] =
0877             rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
0878     } else if (rtlphy->rf_type == RF_2T2R) {
0879         /* Read HT 40 OFDM TX power */
0880         ofdmpowerlevel[RF90_PATH_A] =
0881             rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
0882         ofdmpowerlevel[RF90_PATH_B] =
0883             rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
0884     }
0885 }
0886
0887 static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
0888     u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
0889 {
0890     struct rtl_priv *rtlpriv = rtl_priv(hw);
0891     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0892
0893     rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
0894     rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
0895 }
0896
0897 static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
0898 {
0899     u8 place = chnl;
0900
0901     if (chnl > 14) {
0902         for (place = 14; place < ARRAY_SIZE(channel5g); place++) {
0903             if (channel5g[place] == chnl) {
0904                 place++;
0905                 break;
0906             }
0907         }
0908     }
0909     return place;
0910 }
0911
0912 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
0913 {
0914     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0915     struct rtl_priv *rtlpriv = rtl_priv(hw);
0916     u8 cckpowerlevel[2], ofdmpowerlevel[2];
0917
0918     if (!rtlefuse->txpwr_fromeprom)
0919         return;
0920     channel = _rtl92c_phy_get_rightchnlplace(channel);
0921     _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
0922         &ofdmpowerlevel[0]);
0923     if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
0924         _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
0925                 &ofdmpowerlevel[0]);
0926     if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
0927         rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
0928     rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
0929 }
0930
0931 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
0932                 enum nl80211_channel_type ch_type)
0933 {
0934     struct rtl_priv *rtlpriv = rtl_priv(hw);
0935     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0936     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0937     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
0938     unsigned long flag = 0;
0939     u8 reg_prsr_rsc;
0940     u8 reg_bw_opmode;
0941
0942     if (rtlphy->set_bwmode_inprogress)
0943         return;
0944     if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
0945         rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
0946             "FALSE driver sleep or unload\n");
0947         return;
0948     }
0949     rtlphy->set_bwmode_inprogress = true;
0950     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
0951         rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
0952         "20MHz" : "40MHz");
0953     reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
0954     reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
0955     switch (rtlphy->current_chan_bw) {
0956     case HT_CHANNEL_WIDTH_20:
0957         reg_bw_opmode |= BW_OPMODE_20MHZ;
0958         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
0959         break;
0960     case HT_CHANNEL_WIDTH_20_40:
0961         reg_bw_opmode &= ~BW_OPMODE_20MHZ;
0962         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
0963
0964         reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
0965             (mac->cur_40_prime_sc << 5);
0966         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
0967         break;
0968     default:
0969         pr_err("unknown bandwidth: %#X\n",
0970                rtlphy->current_chan_bw);
0971         break;
0972     }
0973     switch (rtlphy->current_chan_bw) {
0974     case HT_CHANNEL_WIDTH_20:
0975         rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
0976         rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
0977         /* SET BIT10 BIT11  for receive cck */
0978         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
0979                   BIT(11), 3);
0980         break;
0981     case HT_CHANNEL_WIDTH_20_40:
0982         rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
0983         rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
0984         /* Set Control channel to upper or lower.
0985          * These settings are required only for 40MHz */
0986         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
0987             rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
0988             rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
0989                 (mac->cur_40_prime_sc >> 1));
0990             rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
0991         }
0992         rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
0993         /* SET BIT10 BIT11  for receive cck */
0994         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
0995                   BIT(11), 0);
0996         rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
0997             (mac->cur_40_prime_sc ==
0998             HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
0999         break;
1000     default:
1001         pr_err("unknown bandwidth: %#X\n",
1002                rtlphy->current_chan_bw);
1003         break;
1004
1005     }
1006     rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1007     rtlphy->set_bwmode_inprogress = false;
1008     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
1009 }
1010
1011 static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1012 {
1013     rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1014     rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1015     rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
1016     rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1017 }
1018
1019 static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1020 {
1021     struct rtl_priv *rtlpriv = rtl_priv(hw);
1022     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1023     u8 value8;
1024
1025     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
1026     rtlhal->bandset = band;
1027     rtlhal->current_bandtype = band;
1028     if (IS_92D_SINGLEPHY(rtlhal->version))
1029         rtlhal->bandset = BAND_ON_BOTH;
1030     /* stop RX/Tx */
1031     _rtl92d_phy_stop_trx_before_changeband(hw);
1032     /* reconfig BB/RF according to wireless mode */
1033     if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1034         /* BB & RF Config */
1035         rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n");
1036         if (rtlhal->interfaceindex == 1)
1037             _rtl92d_phy_config_bb_with_headerfile(hw,
1038                 BASEBAND_CONFIG_AGC_TAB);
1039     } else {
1040         /* 5G band */
1041         rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n");
1042         if (rtlhal->interfaceindex == 1)
1043             _rtl92d_phy_config_bb_with_headerfile(hw,
1044                 BASEBAND_CONFIG_AGC_TAB);
1045     }
1046     rtl92d_update_bbrf_configuration(hw);
1047     if (rtlhal->current_bandtype == BAND_ON_2_4G)
1048         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1049     rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1050
1051     /* 20M BW. */
1052     /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */
1053     rtlhal->reloadtxpowerindex = true;
1054     /* notice fw know band status  0x81[1]/0x53[1] = 0: 5G, 1: 2G */
1055     if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1056         value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1057             0 ? REG_MAC0 : REG_MAC1));
1058         value8 |= BIT(1);
1059         rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1060             0 ? REG_MAC0 : REG_MAC1), value8);
1061     } else {
1062         value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1063             0 ? REG_MAC0 : REG_MAC1));
1064         value8 &= (~BIT(1));
1065         rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1066             0 ? REG_MAC0 : REG_MAC1), value8);
1067     }
1068     mdelay(1);
1069     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n");
1070 }
1071
1072 static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1073     u8 channel, u8 rfpath)
1074 {
1075     struct rtl_priv *rtlpriv = rtl_priv(hw);
1076     u32 imr_num = MAX_RF_IMR_INDEX;
1077     u32 rfmask = RFREG_OFFSET_MASK;
1078     u8 group, i;
1079     unsigned long flag = 0;
1080
1081     rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath);
1082     if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1083         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1084         rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1085         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1086         /* fc area 0xd2c */
1087         if (channel > 99)
1088             rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1089                       BIT(14), 2);
1090         else
1091             rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1092                       BIT(14), 1);
1093         /* leave 0 for channel1-14. */
1094         group = channel <= 64 ? 1 : 2;
1095         imr_num = MAX_RF_IMR_INDEX_NORMAL;
1096         for (i = 0; i < imr_num; i++)
1097             rtl_set_rfreg(hw, (enum radio_path)rfpath,
1098                       rf_reg_for_5g_swchnl_normal[i], rfmask,
1099                       rf_imr_param_normal[0][group][i]);
1100         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1101         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1102     } else {
1103         /* G band. */
1104         rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
1105             "Load RF IMR parameters for G band. IMR already setting %d\n",
1106             rtlpriv->rtlhal.load_imrandiqk_setting_for2g);
1107         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1108         if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1109             rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
1110                 "Load RF IMR parameters for G band. %d\n",
1111                 rfpath);
1112             rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1113             rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1114             rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1115                       0x00f00000, 0xf);
1116             imr_num = MAX_RF_IMR_INDEX_NORMAL;
1117             for (i = 0; i < imr_num; i++) {
1118                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1119                           rf_reg_for_5g_swchnl_normal[i],
1120                           RFREG_OFFSET_MASK,
1121                           rf_imr_param_normal[0][0][i]);
1122             }
1123             rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1124                       0x00f00000, 0);
1125             rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1126             rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1127         }
1128     }
1129     rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1130 }
1131
1132 static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1133     u8 rfpath, u32 *pu4_regval)
1134 {
1135     struct rtl_priv *rtlpriv = rtl_priv(hw);
1136     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1137     struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1138
1139     rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
1140     /*----Store original RFENV control type----*/
1141     switch (rfpath) {
1142     case RF90_PATH_A:
1143     case RF90_PATH_C:
1144         *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1145         break;
1146     case RF90_PATH_B:
1147     case RF90_PATH_D:
1148         *pu4_regval =
1149             rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1150         break;
1151     }
1152     /*----Set RF_ENV enable----*/
1153     rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1154     udelay(1);
1155     /*----Set RF_ENV output high----*/
1156     rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1157     udelay(1);
1158     /* Set bit number of Address and Data for RF register */
1159     /* Set 1 to 4 bits for 8255 */
1160     rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1161     udelay(1);
1162     /*Set 0 to 12 bits for 8255 */
1163     rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1164     udelay(1);
1165     rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
1166 }
1167
1168 static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1169                        u32 *pu4_regval)
1170 {
1171     struct rtl_priv *rtlpriv = rtl_priv(hw);
1172     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1173     struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1174
1175     rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n");
1176     /*----Restore RFENV control type----*/
1177     switch (rfpath) {
1178     case RF90_PATH_A:
1179     case RF90_PATH_C:
1180         rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1181         break;
1182     case RF90_PATH_B:
1183     case RF90_PATH_D:
1184         rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1185                   *pu4_regval);
1186         break;
1187     }
1188     rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n");
1189 }
1190
1191 static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1192 {
1193     struct rtl_priv *rtlpriv = rtl_priv(hw);
1194     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1195     struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1196     u8 path = rtlhal->current_bandtype ==
1197         BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1198     u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1199     bool need_pwr_down = false, internal_pa = false;
1200     u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1201
1202     rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n");
1203     /* config path A for 5G */
1204     if (rtlhal->current_bandtype == BAND_ON_5G) {
1205         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1206         u4tmp = curveindex_5g[channel - 1];
1207         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1208             "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
1209         for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1210             if (channel == rf_chnl_5g[i] && channel <= 140)
1211                 index = 0;
1212         }
1213         for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1214             if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1215                 index = 1;
1216         }
1217         if (channel == 149 || channel == 155 || channel == 161)
1218             index = 2;
1219         else if (channel == 151 || channel == 153 || channel == 163
1220              || channel == 165)
1221             index = 3;
1222         else if (channel == 157 || channel == 159)
1223             index = 4;
1224
1225         if (rtlhal->macphymode == DUALMAC_DUALPHY
1226             && rtlhal->interfaceindex == 1) {
1227             need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1228             rtlhal->during_mac1init_radioa = true;
1229             /* asume no this case */
1230             if (need_pwr_down)
1231                 _rtl92d_phy_enable_rf_env(hw, path,
1232                               &u4regvalue);
1233         }
1234         for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1235             if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1236                 rtl_set_rfreg(hw, (enum radio_path)path,
1237                           rf_reg_for_c_cut_5g[i],
1238                           RFREG_OFFSET_MASK, 0xE439D);
1239             } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1240                 u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1241                      0x7FF) | (u4tmp << 11);
1242                 if (channel == 36)
1243                     u4tmp2 &= ~(BIT(7) | BIT(6));
1244                 rtl_set_rfreg(hw, (enum radio_path)path,
1245                           rf_reg_for_c_cut_5g[i],
1246                           RFREG_OFFSET_MASK, u4tmp2);
1247             } else {
1248                 rtl_set_rfreg(hw, (enum radio_path)path,
1249                           rf_reg_for_c_cut_5g[i],
1250                           RFREG_OFFSET_MASK,
1251                           rf_reg_pram_c_5g[index][i]);
1252             }
1253             rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
1254                 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n",
1255                 rf_reg_for_c_cut_5g[i],
1256                 rf_reg_pram_c_5g[index][i],
1257                 path, index,
1258                 rtl_get_rfreg(hw, (enum radio_path)path,
1259                           rf_reg_for_c_cut_5g[i],
1260                           RFREG_OFFSET_MASK));
1261         }
1262         if (need_pwr_down)
1263             _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1264         if (rtlhal->during_mac1init_radioa)
1265             rtl92d_phy_powerdown_anotherphy(hw, false);
1266         if (channel < 149)
1267             value = 0x07;
1268         else if (channel >= 149)
1269             value = 0x02;
1270         if (channel >= 36 && channel <= 64)
1271             index = 0;
1272         else if (channel >= 100 && channel <= 140)
1273             index = 1;
1274         else
1275             index = 2;
1276         for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1277             rfpath++) {
1278             if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1279                 rtlhal->interfaceindex == 1)    /* MAC 1 5G */
1280                 internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1281             else
1282                 internal_pa =
1283                      rtlpriv->efuse.internal_pa_5g[rfpath];
1284             if (internal_pa) {
1285                 for (i = 0;
1286                      i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1287                      i++) {
1288                     rtl_set_rfreg(hw, rfpath,
1289                         rf_for_c_cut_5g_internal_pa[i],
1290                         RFREG_OFFSET_MASK,
1291                         rf_pram_c_5g_int_pa[index][i]);
1292                     rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
1293                         "offset 0x%x value 0x%x path %d index %d\n",
1294                         rf_for_c_cut_5g_internal_pa[i],
1295                         rf_pram_c_5g_int_pa[index][i],
1296                         rfpath, index);
1297                 }
1298             } else {
1299                 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1300                           mask, value);
1301             }
1302         }
1303     } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1304         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1305         u4tmp = curveindex_2g[channel - 1];
1306         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1307             "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
1308         if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1309             || channel == 10 || channel == 11 || channel == 12)
1310             index = 0;
1311         else if (channel == 3 || channel == 13 || channel == 14)
1312             index = 1;
1313         else if (channel >= 5 && channel <= 8)
1314             index = 2;
1315         if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1316             path = RF90_PATH_A;
1317             if (rtlhal->interfaceindex == 0) {
1318                 need_pwr_down =
1319                      rtl92d_phy_enable_anotherphy(hw, true);
1320                 rtlhal->during_mac0init_radiob = true;
1321
1322                 if (need_pwr_down)
1323                     _rtl92d_phy_enable_rf_env(hw, path,
1324                                   &u4regvalue);
1325             }
1326         }
1327         for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1328             if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1329                 rtl_set_rfreg(hw, (enum radio_path)path,
1330                     rf_reg_for_c_cut_2g[i],
1331                     RFREG_OFFSET_MASK,
1332                     (rf_reg_param_for_c_cut_2g[index][i] |
1333                     BIT(17)));
1334             else
1335                 rtl_set_rfreg(hw, (enum radio_path)path,
1336                           rf_reg_for_c_cut_2g[i],
1337                           RFREG_OFFSET_MASK,
1338                           rf_reg_param_for_c_cut_2g
1339                           [index][i]);
1340             rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
1341                 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n",
1342                 rf_reg_for_c_cut_2g[i],
1343                 rf_reg_param_for_c_cut_2g[index][i],
1344                 rf_reg_mask_for_c_cut_2g[i], path, index,
1345                 rtl_get_rfreg(hw, (enum radio_path)path,
1346                           rf_reg_for_c_cut_2g[i],
1347                           RFREG_OFFSET_MASK));
1348         }
1349         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1350             "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1351             rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1352
1353         rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1354                   RFREG_OFFSET_MASK,
1355                   rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1356         if (need_pwr_down)
1357             _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1358         if (rtlhal->during_mac0init_radiob)
1359             rtl92d_phy_powerdown_anotherphy(hw, true);
1360     }
1361     rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1362 }
1363
1364 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1365 {
1366     u8 place;
1367
1368     if (chnl > 14) {
1369         for (place = 14; place < ARRAY_SIZE(channel_all); place++) {
1370             if (channel_all[place] == chnl)
1371                 return place - 13;
1372         }
1373     }
1374
1375     return 0;
1376 }
1377
1378 #define MAX_TOLERANCE       5
1379 #define IQK_DELAY_TIME      1   /* ms */
1380 #define MAX_TOLERANCE_92D   3
1381
1382 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1383 static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1384 {
1385     struct rtl_priv *rtlpriv = rtl_priv(hw);
1386     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1387     u32 regeac, rege94, rege9c, regea4;
1388     u8 result = 0;
1389
1390     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK!\n");
1391     /* path-A IQK setting */
1392     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1393     if (rtlhal->interfaceindex == 0) {
1394         rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1395         rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1396     } else {
1397         rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22);
1398         rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22);
1399     }
1400     rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1401     rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206);
1402     /* path-B IQK setting */
1403     if (configpathb) {
1404         rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1405         rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1406         rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1407         rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206);
1408     }
1409     /* LO calibration setting */
1410     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1411     rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1412     /* One shot, path A LOK & IQK */
1413     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "One shot, path A LOK & IQK!\n");
1414     rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1415     rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1416     /* delay x ms */
1417     RTPRINT(rtlpriv, FINIT, INIT_IQK,
1418         "Delay %d ms for One shot, path A LOK & IQK\n",
1419         IQK_DELAY_TIME);
1420     mdelay(IQK_DELAY_TIME);
1421     /* Check failed */
1422     regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1423     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1424     rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1425     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe94 = 0x%x\n", rege94);
1426     rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1427     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe9c = 0x%x\n", rege9c);
1428     regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1429     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xea4 = 0x%x\n", regea4);
1430     if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1431         (((rege9c & 0x03FF0000) >> 16) != 0x42))
1432         result |= 0x01;
1433     else            /* if Tx not OK, ignore Rx */
1434         return result;
1435     /* if Tx is OK, check whether Rx is OK */
1436     if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1437         (((regeac & 0x03FF0000) >> 16) != 0x36))
1438         result |= 0x02;
1439     else
1440         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A Rx IQK fail!!\n");
1441     return result;
1442 }
1443
1444 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1445 static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1446                       bool configpathb)
1447 {
1448     struct rtl_priv *rtlpriv = rtl_priv(hw);
1449     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1450     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1451     u32 regeac, rege94, rege9c, regea4;
1452     u8 result = 0;
1453     u8 i;
1454     u8 retrycount = 2;
1455     u32 TXOKBIT = BIT(28), RXOKBIT = BIT(27);
1456
1457     if (rtlhal->interfaceindex == 1) {  /* PHY1 */
1458         TXOKBIT = BIT(31);
1459         RXOKBIT = BIT(30);
1460     }
1461     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK!\n");
1462     /* path-A IQK setting */
1463     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1464     rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1465     rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1466     rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307);
1467     rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960);
1468     /* path-B IQK setting */
1469     if (configpathb) {
1470         rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1471         rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1472         rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000);
1473         rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000);
1474     }
1475     /* LO calibration setting */
1476     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1477     rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1478     /* path-A PA on */
1479     rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
1480     rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30);
1481     for (i = 0; i < retrycount; i++) {
1482         /* One shot, path A LOK & IQK */
1483         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1484             "One shot, path A LOK & IQK!\n");
1485         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1486         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1487         /* delay x ms */
1488         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1489             "Delay %d ms for One shot, path A LOK & IQK.\n",
1490             IQK_DELAY_TIME);
1491         mdelay(IQK_DELAY_TIME * 10);
1492         /* Check failed */
1493         regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1494         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1495         rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1496         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe94 = 0x%x\n", rege94);
1497         rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1498         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe9c = 0x%x\n", rege9c);
1499         regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1500         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xea4 = 0x%x\n", regea4);
1501         if (!(regeac & TXOKBIT) &&
1502              (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1503             result |= 0x01;
1504         } else { /* if Tx not OK, ignore Rx */
1505             RTPRINT(rtlpriv, FINIT, INIT_IQK,
1506                 "Path A Tx IQK fail!!\n");
1507             continue;
1508         }
1509
1510         /* if Tx is OK, check whether Rx is OK */
1511         if (!(regeac & RXOKBIT) &&
1512             (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1513             result |= 0x02;
1514             break;
1515         } else {
1516             RTPRINT(rtlpriv, FINIT, INIT_IQK,
1517                 "Path A Rx IQK fail!!\n");
1518         }
1519     }
1520     /* path A PA off */
1521     rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1522               rtlphy->iqk_bb_backup[0]);
1523     rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD,
1524               rtlphy->iqk_bb_backup[1]);
1525     return result;
1526 }
1527
1528 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1529 static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1530 {
1531     struct rtl_priv *rtlpriv = rtl_priv(hw);
1532     u32 regeac, regeb4, regebc, regec4, regecc;
1533     u8 result = 0;
1534
1535     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B IQK!\n");
1536     /* One shot, path B LOK & IQK */
1537     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "One shot, path A LOK & IQK!\n");
1538     rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1539     rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1540     /* delay x ms  */
1541     RTPRINT(rtlpriv, FINIT, INIT_IQK,
1542         "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
1543     mdelay(IQK_DELAY_TIME);
1544     /* Check failed */
1545     regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1546     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1547     regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1548     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeb4 = 0x%x\n", regeb4);
1549     regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1550     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xebc = 0x%x\n", regebc);
1551     regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1552     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xec4 = 0x%x\n", regec4);
1553     regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1554     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xecc = 0x%x\n", regecc);
1555     if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1556         (((regebc & 0x03FF0000) >> 16) != 0x42))
1557         result |= 0x01;
1558     else
1559         return result;
1560     if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1561         (((regecc & 0x03FF0000) >> 16) != 0x36))
1562         result |= 0x02;
1563     else
1564         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B Rx IQK fail!!\n");
1565     return result;
1566 }
1567
1568 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1569 static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1570 {
1571     struct rtl_priv *rtlpriv = rtl_priv(hw);
1572     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1573     u32 regeac, regeb4, regebc, regec4, regecc;
1574     u8 result = 0;
1575     u8 i;
1576     u8 retrycount = 2;
1577
1578     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B IQK!\n");
1579     /* path-A IQK setting */
1580     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1581     rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1582     rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1583     rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000);
1584     rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000);
1585
1586     /* path-B IQK setting */
1587     rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1588     rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1589     rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307);
1590     rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960);
1591
1592     /* LO calibration setting */
1593     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1594     rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1595
1596     /* path-B PA on */
1597     rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
1598     rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30);
1599
1600     for (i = 0; i < retrycount; i++) {
1601         /* One shot, path B LOK & IQK */
1602         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1603             "One shot, path A LOK & IQK!\n");
1604         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000);
1605         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1606
1607         /* delay x ms */
1608         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1609             "Delay %d ms for One shot, path B LOK & IQK.\n", 10);
1610         mdelay(IQK_DELAY_TIME * 10);
1611
1612         /* Check failed */
1613         regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1614         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1615         regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1616         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeb4 = 0x%x\n", regeb4);
1617         regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1618         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xebc = 0x%x\n", regebc);
1619         regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1620         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xec4 = 0x%x\n", regec4);
1621         regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1622         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xecc = 0x%x\n", regecc);
1623         if (!(regeac & BIT(31)) &&
1624             (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1625             result |= 0x01;
1626         else
1627             continue;
1628         if (!(regeac & BIT(30)) &&
1629             (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1630             result |= 0x02;
1631             break;
1632         } else {
1633             RTPRINT(rtlpriv, FINIT, INIT_IQK,
1634                 "Path B Rx IQK fail!!\n");
1635         }
1636     }
1637
1638     /* path B PA off */
1639     rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1640               rtlphy->iqk_bb_backup[0]);
1641     rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD,
1642               rtlphy->iqk_bb_backup[2]);
1643     return result;
1644 }
1645
1646 static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1647                         u32 *adda_reg, u32 *adda_backup,
1648                         u32 regnum)
1649 {
1650     struct rtl_priv *rtlpriv = rtl_priv(hw);
1651     u32 i;
1652
1653     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Save ADDA parameters.\n");
1654     for (i = 0; i < regnum; i++)
1655         adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD);
1656 }
1657
1658 static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1659     u32 *macreg, u32 *macbackup)
1660 {
1661     struct rtl_priv *rtlpriv = rtl_priv(hw);
1662     u32 i;
1663
1664     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Save MAC parameters.\n");
1665     for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1666         macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1667     macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1668 }
1669
1670 static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1671                           u32 *adda_reg, u32 *adda_backup,
1672                           u32 regnum)
1673 {
1674     struct rtl_priv *rtlpriv = rtl_priv(hw);
1675     u32 i;
1676
1677     RTPRINT(rtlpriv, FINIT, INIT_IQK,
1678         "Reload ADDA power saving parameters !\n");
1679     for (i = 0; i < regnum; i++)
1680         rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]);
1681 }
1682
1683 static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1684                          u32 *macreg, u32 *macbackup)
1685 {
1686     struct rtl_priv *rtlpriv = rtl_priv(hw);
1687     u32 i;
1688
1689     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Reload MAC parameters !\n");
1690     for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1691         rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1692     rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1693 }
1694
1695 static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1696         u32 *adda_reg, bool patha_on, bool is2t)
1697 {
1698     struct rtl_priv *rtlpriv = rtl_priv(hw);
1699     u32 pathon;
1700     u32 i;
1701
1702     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "ADDA ON.\n");
1703     pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1704     if (patha_on)
1705         pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1706             0x04db25a4 : 0x0b1b25a4;
1707     for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1708         rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon);
1709 }
1710
1711 static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1712                         u32 *macreg, u32 *macbackup)
1713 {
1714     struct rtl_priv *rtlpriv = rtl_priv(hw);
1715     u32 i;
1716
1717     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "MAC settings for Calibration.\n");
1718     rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1719
1720     for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1721         rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1722                    (~BIT(3))));
1723     rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1724 }
1725
1726 static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1727 {
1728     struct rtl_priv *rtlpriv = rtl_priv(hw);
1729     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A standby mode!\n");
1730
1731     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1732     rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000);
1733     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1734 }
1735
1736 static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1737 {
1738     struct rtl_priv *rtlpriv = rtl_priv(hw);
1739     u32 mode;
1740
1741     RTPRINT(rtlpriv, FINIT, INIT_IQK,
1742         "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
1743     mode = pi_mode ? 0x01000100 : 0x01000000;
1744     rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1745     rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1746 }
1747
1748 static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1749                      u8 t, bool is2t)
1750 {
1751     struct rtl_priv *rtlpriv = rtl_priv(hw);
1752     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1753     u32 i;
1754     u8 patha_ok, pathb_ok;
1755     static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1756         RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1757         0xe78, 0xe7c, 0xe80, 0xe84,
1758         0xe88, 0xe8c, 0xed0, 0xed4,
1759         0xed8, 0xedc, 0xee0, 0xeec
1760     };
1761     static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1762         0x522, 0x550, 0x551, 0x040
1763     };
1764     static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1765         RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1766         RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1767         RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1768         RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1769         ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1770     };
1771     const u32 retrycount = 2;
1772     u32 bbvalue;
1773
1774     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK for 2.4G :Start!!!\n");
1775     if (t == 0) {
1776         bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1777         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "==>0x%08x\n", bbvalue);
1778         RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1779             is2t ? "2T2R" : "1T1R");
1780
1781         /*  Save ADDA parameters, turn Path A ADDA on */
1782         _rtl92d_phy_save_adda_registers(hw, adda_reg,
1783             rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1784         _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1785             rtlphy->iqk_mac_backup);
1786         _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1787             rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
1788     }
1789     _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1790     if (t == 0)
1791         rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1792                 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1793
1794     /*  Switch BB to PI mode to do IQ Calibration. */
1795     if (!rtlphy->rfpi_enable)
1796         _rtl92d_phy_pimode_switch(hw, true);
1797
1798     rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1799     rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1800     rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1801     rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
1802     rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1803     if (is2t) {
1804         rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD,
1805                   0x00010000);
1806         rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD,
1807                   0x00010000);
1808     }
1809     /* MAC settings */
1810     _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1811                         rtlphy->iqk_mac_backup);
1812     /* Page B init */
1813     rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1814     if (is2t)
1815         rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1816     /* IQ calibration setting */
1817     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK setting!\n");
1818     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1819     rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1820     rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1821     for (i = 0; i < retrycount; i++) {
1822         patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
1823         if (patha_ok == 0x03) {
1824             RTPRINT(rtlpriv, FINIT, INIT_IQK,
1825                 "Path A IQK Success!!\n");
1826             result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1827                     0x3FF0000) >> 16;
1828             result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1829                     0x3FF0000) >> 16;
1830             result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1831                     0x3FF0000) >> 16;
1832             result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1833                     0x3FF0000) >> 16;
1834             break;
1835         } else if (i == (retrycount - 1) && patha_ok == 0x01) {
1836             /* Tx IQK OK */
1837             RTPRINT(rtlpriv, FINIT, INIT_IQK,
1838                 "Path A IQK Only  Tx Success!!\n");
1839
1840             result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1841                     0x3FF0000) >> 16;
1842             result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1843                     0x3FF0000) >> 16;
1844         }
1845     }
1846     if (0x00 == patha_ok)
1847         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK failed!!\n");
1848     if (is2t) {
1849         _rtl92d_phy_patha_standby(hw);
1850         /* Turn Path B ADDA on */
1851         _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
1852         for (i = 0; i < retrycount; i++) {
1853             pathb_ok = _rtl92d_phy_pathb_iqk(hw);
1854             if (pathb_ok == 0x03) {
1855                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1856                     "Path B IQK Success!!\n");
1857                 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1858                            MASKDWORD) & 0x3FF0000) >> 16;
1859                 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1860                            MASKDWORD) & 0x3FF0000) >> 16;
1861                 result[t][6] = (rtl_get_bbreg(hw, 0xec4,
1862                            MASKDWORD) & 0x3FF0000) >> 16;
1863                 result[t][7] = (rtl_get_bbreg(hw, 0xecc,
1864                            MASKDWORD) & 0x3FF0000) >> 16;
1865                 break;
1866             } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1867                 /* Tx IQK OK */
1868                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1869                     "Path B Only Tx IQK Success!!\n");
1870                 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1871                            MASKDWORD) & 0x3FF0000) >> 16;
1872                 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1873                            MASKDWORD) & 0x3FF0000) >> 16;
1874             }
1875         }
1876         if (0x00 == pathb_ok)
1877             RTPRINT(rtlpriv, FINIT, INIT_IQK,
1878                 "Path B IQK failed!!\n");
1879     }
1880
1881     /* Back to BB mode, load original value */
1882     RTPRINT(rtlpriv, FINIT, INIT_IQK,
1883         "IQK:Back to BB mode, load original value!\n");
1884
1885     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1886     if (t != 0) {
1887         /* Switch back BB to SI mode after finish IQ Calibration. */
1888         if (!rtlphy->rfpi_enable)
1889             _rtl92d_phy_pimode_switch(hw, false);
1890         /* Reload ADDA power saving parameters */
1891         _rtl92d_phy_reload_adda_registers(hw, adda_reg,
1892                 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1893         /* Reload MAC parameters */
1894         _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
1895                     rtlphy->iqk_mac_backup);
1896         if (is2t)
1897             _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1898                               rtlphy->iqk_bb_backup,
1899                               IQK_BB_REG_NUM);
1900         else
1901             _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1902                               rtlphy->iqk_bb_backup,
1903                               IQK_BB_REG_NUM - 1);
1904         /* load 0xe30 IQC default value */
1905         rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1906         rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1907     }
1908     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "<==\n");
1909 }
1910
1911 static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
1912                            long result[][8], u8 t)
1913 {
1914     struct rtl_priv *rtlpriv = rtl_priv(hw);
1915     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1916     struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1917     u8 patha_ok, pathb_ok;
1918     static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1919         RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1920         0xe78, 0xe7c, 0xe80, 0xe84,
1921         0xe88, 0xe8c, 0xed0, 0xed4,
1922         0xed8, 0xedc, 0xee0, 0xeec
1923     };
1924     static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1925         0x522, 0x550, 0x551, 0x040
1926     };
1927     static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1928         RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1929         RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1930         RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1931         RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1932         ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1933     };
1934     u32 bbvalue;
1935     bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
1936
1937     /* Note: IQ calibration must be performed after loading
1938      * PHY_REG.txt , and radio_a, radio_b.txt */
1939
1940     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK for 5G NORMAL:Start!!!\n");
1941     mdelay(IQK_DELAY_TIME * 20);
1942     if (t == 0) {
1943         bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1944         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "==>0x%08x\n", bbvalue);
1945         RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1946             is2t ? "2T2R" : "1T1R");
1947         /* Save ADDA parameters, turn Path A ADDA on */
1948         _rtl92d_phy_save_adda_registers(hw, adda_reg,
1949                         rtlphy->adda_backup,
1950                         IQK_ADDA_REG_NUM);
1951         _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1952                            rtlphy->iqk_mac_backup);
1953         if (is2t)
1954             _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1955                             rtlphy->iqk_bb_backup,
1956                             IQK_BB_REG_NUM);
1957         else
1958             _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1959                             rtlphy->iqk_bb_backup,
1960                             IQK_BB_REG_NUM - 1);
1961     }
1962     _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1963     /* MAC settings */
1964     _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1965             rtlphy->iqk_mac_backup);
1966     if (t == 0)
1967         rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1968             RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1969     /*  Switch BB to PI mode to do IQ Calibration. */
1970     if (!rtlphy->rfpi_enable)
1971         _rtl92d_phy_pimode_switch(hw, true);
1972     rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1973     rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1974     rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1975     rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
1976     rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1977
1978     /* Page B init */
1979     rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1980     if (is2t)
1981         rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1982     /* IQ calibration setting  */
1983     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK setting!\n");
1984     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1985     rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00);
1986     rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1987     patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
1988     if (patha_ok == 0x03) {
1989         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK Success!!\n");
1990         result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1991                 0x3FF0000) >> 16;
1992         result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1993                 0x3FF0000) >> 16;
1994         result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1995                 0x3FF0000) >> 16;
1996         result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1997                 0x3FF0000) >> 16;
1998     } else if (patha_ok == 0x01) {  /* Tx IQK OK */
1999         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2000             "Path A IQK Only  Tx Success!!\n");
2001
2002         result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2003                 0x3FF0000) >> 16;
2004         result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2005                 0x3FF0000) >> 16;
2006     } else {
2007         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK Fail!!\n");
2008     }
2009     if (is2t) {
2010         /* _rtl92d_phy_patha_standby(hw); */
2011         /* Turn Path B ADDA on  */
2012         _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2013         pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2014         if (pathb_ok == 0x03) {
2015             RTPRINT(rtlpriv, FINIT, INIT_IQK,
2016                 "Path B IQK Success!!\n");
2017             result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2018                  0x3FF0000) >> 16;
2019             result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2020                  0x3FF0000) >> 16;
2021             result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
2022                  0x3FF0000) >> 16;
2023             result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
2024                  0x3FF0000) >> 16;
2025         } else if (pathb_ok == 0x01) { /* Tx IQK OK */
2026             RTPRINT(rtlpriv, FINIT, INIT_IQK,
2027                 "Path B Only Tx IQK Success!!\n");
2028             result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2029                  0x3FF0000) >> 16;
2030             result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2031                  0x3FF0000) >> 16;
2032         } else {
2033             RTPRINT(rtlpriv, FINIT, INIT_IQK,
2034                 "Path B IQK failed!!\n");
2035         }
2036     }
2037
2038     /* Back to BB mode, load original value */
2039     RTPRINT(rtlpriv, FINIT, INIT_IQK,
2040         "IQK:Back to BB mode, load original value!\n");
2041     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
2042     if (t != 0) {
2043         if (is2t)
2044             _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2045                               rtlphy->iqk_bb_backup,
2046                               IQK_BB_REG_NUM);
2047         else
2048             _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2049                               rtlphy->iqk_bb_backup,
2050                               IQK_BB_REG_NUM - 1);
2051         /* Reload MAC parameters */
2052         _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2053                 rtlphy->iqk_mac_backup);
2054         /*  Switch back BB to SI mode after finish IQ Calibration. */
2055         if (!rtlphy->rfpi_enable)
2056             _rtl92d_phy_pimode_switch(hw, false);
2057         /* Reload ADDA power saving parameters */
2058         _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2059                           rtlphy->adda_backup,
2060                           IQK_ADDA_REG_NUM);
2061     }
2062     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "<==\n");
2063 }
2064
2065 static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2066     long result[][8], u8 c1, u8 c2)
2067 {
2068     struct rtl_priv *rtlpriv = rtl_priv(hw);
2069     struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2070     u32 i, j, diff, sim_bitmap, bound;
2071     u8 final_candidate[2] = {0xFF, 0xFF};   /* for path A and path B */
2072     bool bresult = true;
2073     bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2074
2075     if (is2t)
2076         bound = 8;
2077     else
2078         bound = 4;
2079     sim_bitmap = 0;
2080     for (i = 0; i < bound; i++) {
2081         diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2082                result[c2][i]) : (result[c2][i] - result[c1][i]);
2083         if (diff > MAX_TOLERANCE_92D) {
2084             if ((i == 2 || i == 6) && !sim_bitmap) {
2085                 if (result[c1][i] + result[c1][i + 1] == 0)
2086                     final_candidate[(i / 4)] = c2;
2087                 else if (result[c2][i] + result[c2][i + 1] == 0)
2088                     final_candidate[(i / 4)] = c1;
2089                 else
2090                     sim_bitmap = sim_bitmap | (1 << i);
2091             } else {
2092                 sim_bitmap = sim_bitmap | (1 << i);
2093             }
2094         }
2095     }
2096     if (sim_bitmap == 0) {
2097         for (i = 0; i < (bound / 4); i++) {
2098             if (final_candidate[i] != 0xFF) {
2099                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2100                     result[3][j] =
2101                          result[final_candidate[i]][j];
2102                 bresult = false;
2103             }
2104         }
2105         return bresult;
2106     }
2107     if (!(sim_bitmap & 0x0F)) { /* path A OK */
2108         for (i = 0; i < 4; i++)
2109             result[3][i] = result[c1][i];
2110     } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */
2111         for (i = 0; i < 2; i++)
2112             result[3][i] = result[c1][i];
2113     }
2114     if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */
2115         for (i = 4; i < 8; i++)
2116             result[3][i] = result[c1][i];
2117     } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */
2118         for (i = 4; i < 6; i++)
2119             result[3][i] = result[c1][i];
2120     }
2121     return false;
2122 }
2123
2124 static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2125                           bool iqk_ok, long result[][8],
2126                           u8 final_candidate, bool txonly)
2127 {
2128     struct rtl_priv *rtlpriv = rtl_priv(hw);
2129     struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2130     u32 oldval_0, val_x, tx0_a, reg;
2131     long val_y, tx0_c;
2132     bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2133         rtlhal->macphymode == DUALMAC_DUALPHY;
2134
2135     RTPRINT(rtlpriv, FINIT, INIT_IQK,
2136         "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed");
2137     if (final_candidate == 0xFF) {
2138         return;
2139     } else if (iqk_ok) {
2140         oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2141             MASKDWORD) >> 22) & 0x3FF;  /* OFDM0_D */
2142         val_x = result[final_candidate][0];
2143         if ((val_x & 0x00000200) != 0)
2144             val_x = val_x | 0xFFFFFC00;
2145         tx0_a = (val_x * oldval_0) >> 8;
2146         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2147             "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
2148             val_x, tx0_a, oldval_0);
2149         rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
2150         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2151                   ((val_x * oldval_0 >> 7) & 0x1));
2152         val_y = result[final_candidate][1];
2153         if ((val_y & 0x00000200) != 0)
2154             val_y = val_y | 0xFFFFFC00;
2155         /* path B IQK result + 3 */
2156         if (rtlhal->interfaceindex == 1 &&
2157             rtlhal->current_bandtype == BAND_ON_5G)
2158             val_y += 3;
2159         tx0_c = (val_y * oldval_0) >> 8;
2160         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2161             "Y = 0x%lx, tx0_c = 0x%lx\n",
2162             val_y, tx0_c);
2163         rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
2164                   ((tx0_c & 0x3C0) >> 6));
2165         rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
2166                   (tx0_c & 0x3F));
2167         if (is2t)
2168             rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2169                       ((val_y * oldval_0 >> 7) & 0x1));
2170         RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2171             rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2172                       MASKDWORD));
2173         if (txonly) {
2174             RTPRINT(rtlpriv, FINIT, INIT_IQK,  "only Tx OK\n");
2175             return;
2176         }
2177         reg = result[final_candidate][2];
2178         rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2179         reg = result[final_candidate][3] & 0x3F;
2180         rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2181         reg = (result[final_candidate][3] >> 6) & 0xF;
2182         rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2183     }
2184 }
2185
2186 static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2187     bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2188 {
2189     struct rtl_priv *rtlpriv = rtl_priv(hw);
2190     struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2191     u32 oldval_1, val_x, tx1_a, reg;
2192     long val_y, tx1_c;
2193
2194     RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n",
2195         iqk_ok ? "Success" : "Failed");
2196     if (final_candidate == 0xFF) {
2197         return;
2198     } else if (iqk_ok) {
2199         oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
2200                       MASKDWORD) >> 22) & 0x3FF;
2201         val_x = result[final_candidate][4];
2202         if ((val_x & 0x00000200) != 0)
2203             val_x = val_x | 0xFFFFFC00;
2204         tx1_a = (val_x * oldval_1) >> 8;
2205         RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2206             val_x, tx1_a);
2207         rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
2208         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2209                   ((val_x * oldval_1 >> 7) & 0x1));
2210         val_y = result[final_candidate][5];
2211         if ((val_y & 0x00000200) != 0)
2212             val_y = val_y | 0xFFFFFC00;
2213         if (rtlhal->current_bandtype == BAND_ON_5G)
2214             val_y += 3;
2215         tx1_c = (val_y * oldval_1) >> 8;
2216         RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2217             val_y, tx1_c);
2218         rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
2219                   ((tx1_c & 0x3C0) >> 6));
2220         rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
2221                   (tx1_c & 0x3F));
2222         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2223                   ((val_y * oldval_1 >> 7) & 0x1));
2224         if (txonly)
2225             return;
2226         reg = result[final_candidate][6];
2227         rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2228         reg = result[final_candidate][7] & 0x3F;
2229         rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2230         reg = (result[final_candidate][7] >> 6) & 0xF;
2231         rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2232     }
2233 }
2234
2235 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2236 {
2237     struct rtl_priv *rtlpriv = rtl_priv(hw);
2238     struct rtl_phy *rtlphy = &(rtlpriv->phy);
2239     struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2240     long result[4][8];
2241     u8 i, final_candidate, indexforchannel;
2242     bool patha_ok, pathb_ok;
2243     long rege94, rege9c, regea4, regeac, regeb4;
2244     long regebc, regec4, regecc, regtmp = 0;
2245     bool is12simular, is13simular, is23simular;
2246     unsigned long flag = 0;
2247
2248     RTPRINT(rtlpriv, FINIT, INIT_IQK,
2249         "IQK:Start!!!channel %d\n", rtlphy->current_channel);
2250     for (i = 0; i < 8; i++) {
2251         result[0][i] = 0;
2252         result[1][i] = 0;
2253         result[2][i] = 0;
2254         result[3][i] = 0;
2255     }
2256     final_candidate = 0xff;
2257     patha_ok = false;
2258     pathb_ok = false;
2259     is12simular = false;
2260     is23simular = false;
2261     is13simular = false;
2262     RTPRINT(rtlpriv, FINIT, INIT_IQK,
2263         "IQK !!!currentband %d\n", rtlhal->current_bandtype);
2264     rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2265     for (i = 0; i < 3; i++) {
2266         if (rtlhal->current_bandtype == BAND_ON_5G) {
2267             _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2268         } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2269             if (IS_92D_SINGLEPHY(rtlhal->version))
2270                 _rtl92d_phy_iq_calibrate(hw, result, i, true);
2271             else
2272                 _rtl92d_phy_iq_calibrate(hw, result, i, false);
2273         }
2274         if (i == 1) {
2275             is12simular = _rtl92d_phy_simularity_compare(hw, result,
2276                                      0, 1);
2277             if (is12simular) {
2278                 final_candidate = 0;
2279                 break;
2280             }
2281         }
2282         if (i == 2) {
2283             is13simular = _rtl92d_phy_simularity_compare(hw, result,
2284                                      0, 2);
2285             if (is13simular) {
2286                 final_candidate = 0;
2287                 break;
2288             }
2289             is23simular = _rtl92d_phy_simularity_compare(hw, result,
2290                                      1, 2);
2291             if (is23simular) {
2292                 final_candidate = 1;
2293             } else {
2294                 for (i = 0; i < 8; i++)
2295                     regtmp += result[3][i];
2296
2297                 if (regtmp != 0)
2298                     final_candidate = 3;
2299                 else
2300                     final_candidate = 0xFF;
2301             }
2302         }
2303     }
2304     rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2305     for (i = 0; i < 4; i++) {
2306         rege94 = result[i][0];
2307         rege9c = result[i][1];
2308         regea4 = result[i][2];
2309         regeac = result[i][3];
2310         regeb4 = result[i][4];
2311         regebc = result[i][5];
2312         regec4 = result[i][6];
2313         regecc = result[i][7];
2314         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2315             "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2316             rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2317             regecc);
2318     }
2319     if (final_candidate != 0xff) {
2320         rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2321         rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2322         regea4 = result[final_candidate][2];
2323         regeac = result[final_candidate][3];
2324         rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2325         rtlphy->reg_ebc = regebc = result[final_candidate][5];
2326         regec4 = result[final_candidate][6];
2327         regecc = result[final_candidate][7];
2328         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2329             "IQK: final_candidate is %x\n", final_candidate);
2330         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2331             "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2332             rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2333             regecc);
2334         patha_ok = pathb_ok = true;
2335     } else {
2336         rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */
2337         rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;   /* Y default value */
2338     }
2339     if ((rege94 != 0) /*&&(regea4 != 0) */)
2340         _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2341                 final_candidate, (regea4 == 0));
2342     if (IS_92D_SINGLEPHY(rtlhal->version)) {
2343         if ((regeb4 != 0) /*&&(regec4 != 0) */)
2344             _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2345                         final_candidate, (regec4 == 0));
2346     }
2347     if (final_candidate != 0xFF) {
2348         indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2349                   rtlphy->current_channel);
2350
2351         for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2352             rtlphy->iqk_matrix[indexforchannel].
2353                 value[0][i] = result[final_candidate][i];
2354         rtlphy->iqk_matrix[indexforchannel].iqk_done =
2355             true;
2356
2357         rtl_dbg(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2358             "IQK OK indexforchannel %d\n", indexforchannel);
2359     }
2360 }
2361
2362 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2363 {
2364     struct rtl_priv *rtlpriv = rtl_priv(hw);
2365     struct rtl_phy *rtlphy = &(rtlpriv->phy);
2366     struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2367     u8 indexforchannel;
2368
2369     rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel);
2370     /*------Do IQK for normal chip and test chip 5G band------- */
2371     indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2372     rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n",
2373         indexforchannel,
2374          rtlphy->iqk_matrix[indexforchannel].iqk_done);
2375     if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done &&
2376         rtlphy->need_iqk) {
2377         /* Re Do IQK. */
2378         rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2379             "Do IQK Matrix reg for channel:%d....\n", channel);
2380         rtl92d_phy_iq_calibrate(hw);
2381     } else {
2382         /* Just load the value. */
2383         /* 2G band just load once. */
2384         if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2385             indexforchannel == 0) || indexforchannel > 0) {
2386             rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
2387                 "Just Read IQK Matrix reg for channel:%d....\n",
2388                 channel);
2389             _rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2390                     rtlphy->iqk_matrix[
2391                     indexforchannel].value, 0,
2392                     (rtlphy->iqk_matrix[
2393                     indexforchannel].value[0][2] == 0));
2394             if (IS_92D_SINGLEPHY(rtlhal->version)) {
2395                 if ((rtlphy->iqk_matrix[
2396                     indexforchannel].value[0][4] != 0)
2397                     /*&&(regec4 != 0) */)
2398                     _rtl92d_phy_pathb_fill_iqk_matrix(hw,
2399                         true,
2400                         rtlphy->iqk_matrix[
2401                         indexforchannel].value, 0,
2402                         (rtlphy->iqk_matrix[
2403                         indexforchannel].value[0][6]
2404                         == 0));
2405             }
2406         }
2407     }
2408     rtlphy->need_iqk = false;
2409     rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2410 }
2411
2412 static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2413 {
2414     u32 ret;
2415
2416     if (val1 >= val2)
2417         ret = val1 - val2;
2418     else
2419         ret = val2 - val1;
2420     return ret;
2421 }
2422
2423 static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2424 {
2425
2426     int i;
2427
2428     for (i = 0; i < ARRAY_SIZE(channel5g); i++)
2429         if (channel == channel5g[i])
2430             return true;
2431     return false;
2432 }
2433
2434 static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2435                        u32 *targetchnl, u32 * curvecount_val,
2436                        bool is5g, u32 *curveindex)
2437 {
2438     struct rtl_priv *rtlpriv = rtl_priv(hw);
2439     u32 smallest_abs_val = 0xffffffff, u4tmp;
2440     u8 i, j;
2441     u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2442
2443     for (i = 0; i < chnl_num; i++) {
2444         if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2445             continue;
2446         curveindex[i] = 0;
2447         for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2448             u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2449                 curvecount_val[j]);
2450
2451             if (u4tmp < smallest_abs_val) {
2452                 curveindex[i] = j;
2453                 smallest_abs_val = u4tmp;
2454             }
2455         }
2456         smallest_abs_val = 0xffffffff;
2457         RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n",
2458             i, curveindex[i]);
2459     }
2460 }
2461
2462 static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2463         u8 channel)
2464 {
2465     struct rtl_priv *rtlpriv = rtl_priv(hw);
2466     u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2467         BAND_ON_5G ? RF90_PATH_A :
2468         IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2469         RF90_PATH_B : RF90_PATH_A;
2470     u32 u4tmp = 0, u4regvalue = 0;
2471     bool bneed_powerdown_radio = false;
2472
2473     rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath);
2474     RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n",
2475         rtlpriv->rtlhal.current_bandtype);
2476     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "channel = %d\n", channel);
2477     if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2478         u4tmp = curveindex_5g[channel-1];
2479         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2480             "ver 1 set RF-A, 5G,    0x28 = 0x%x !!\n", u4tmp);
2481         if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2482             rtlpriv->rtlhal.interfaceindex == 1) {
2483             bneed_powerdown_radio =
2484                 rtl92d_phy_enable_anotherphy(hw, false);
2485             rtlpriv->rtlhal.during_mac1init_radioa = true;
2486             /* asume no this case */
2487             if (bneed_powerdown_radio)
2488                 _rtl92d_phy_enable_rf_env(hw, erfpath,
2489                               &u4regvalue);
2490         }
2491         rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2492         if (bneed_powerdown_radio)
2493             _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2494         if (rtlpriv->rtlhal.during_mac1init_radioa)
2495             rtl92d_phy_powerdown_anotherphy(hw, false);
2496     } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2497         u4tmp = curveindex_2g[channel-1];
2498         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2499             "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
2500         if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2501             rtlpriv->rtlhal.interfaceindex == 0) {
2502             bneed_powerdown_radio =
2503                 rtl92d_phy_enable_anotherphy(hw, true);
2504             rtlpriv->rtlhal.during_mac0init_radiob = true;
2505             if (bneed_powerdown_radio)
2506                 _rtl92d_phy_enable_rf_env(hw, erfpath,
2507                               &u4regvalue);
2508         }
2509         rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2510         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2511             "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
2512             rtl_get_rfreg(hw,  erfpath, RF_SYN_G4, 0x3f800));
2513         if (bneed_powerdown_radio)
2514             _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2515         if (rtlpriv->rtlhal.during_mac0init_radiob)
2516             rtl92d_phy_powerdown_anotherphy(hw, true);
2517     }
2518     rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2519 }
2520
2521 static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2522 {
2523     struct rtl_priv *rtlpriv = rtl_priv(hw);
2524     struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2525     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2526     u8 tmpreg, index, rf_mode[2];
2527     u8 path = is2t ? 2 : 1;
2528     u8 i;
2529     u32 u4tmp, offset;
2530     u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2531     u16 timeout = 800, timecount = 0;
2532
2533     /* Check continuous TX and Packet TX */
2534     tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2535     /* if Deal with contisuous TX case, disable all continuous TX */
2536     /* if Deal with Packet TX case, block all queues */
2537     if ((tmpreg & 0x70) != 0)
2538         rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2539     else
2540         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2541     rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2542     for (index = 0; index < path; index++) {
2543         /* 1. Read original RF mode */
2544         offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2545         rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2546         /* 2. Set RF mode = standby mode */
2547         rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2548                   RFREG_OFFSET_MASK, 0x010000);
2549         if (rtlpci->init_ready) {
2550             /* switch CV-curve control by LC-calibration */
2551             rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2552                       BIT(17), 0x0);
2553             /* 4. Set LC calibration begin */
2554             rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2555                       0x08000, 0x01);
2556         }
2557         u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2558                   RFREG_OFFSET_MASK);
2559         while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2560             mdelay(50);
2561             timecount += 50;
2562             u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2563                           RF_SYN_G6, RFREG_OFFSET_MASK);
2564         }
2565         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2566             "PHY_LCK finish delay for %d ms=2\n", timecount);
2567         rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK);
2568         if (index == 0 && rtlhal->interfaceindex == 0) {
2569             RTPRINT(rtlpriv, FINIT, INIT_IQK,
2570                 "path-A / 5G LCK\n");
2571         } else {
2572             RTPRINT(rtlpriv, FINIT, INIT_IQK,
2573                 "path-B / 2.4G LCK\n");
2574         }
2575         memset(curvecount_val, 0, sizeof(curvecount_val));
2576         /* Set LC calibration off */
2577         rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2578                   0x08000, 0x0);
2579         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "set RF 0x18[15] = 0\n");
2580         /* save Curve-counting number */
2581         for (i = 0; i < CV_CURVE_CNT; i++) {
2582             u32 readval = 0, readval2 = 0;
2583             rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2584                       0x7f, i);
2585
2586             rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2587                 RFREG_OFFSET_MASK, 0x0);
2588             readval = rtl_get_rfreg(hw, (enum radio_path)index,
2589                       0x4F, RFREG_OFFSET_MASK);
2590             curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2591             /* reg 0x4f [4:0] */
2592             /* reg 0x50 [19:10] */
2593             readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2594                          0x50, 0xffc00);
2595             curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2596                          readval2);
2597         }
2598         if (index == 0 && rtlhal->interfaceindex == 0)
2599             _rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2600                            curvecount_val,
2601                            true, curveindex_5g);
2602         else
2603             _rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2604                            curvecount_val,
2605                            false, curveindex_2g);
2606         /* switch CV-curve control mode */
2607         rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2608                   BIT(17), 0x1);
2609     }
2610
2611     /* Restore original situation  */
2612     for (index = 0; index < path; index++) {
2613         offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2614         rtl_write_byte(rtlpriv, offset, 0x50);
2615         rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2616     }
2617     if ((tmpreg & 0x70) != 0)
2618         rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2619     else /*Deal with Packet TX case */
2620         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2621     rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2622     _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2623 }
2624
2625 static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2626 {
2627     struct rtl_priv *rtlpriv = rtl_priv(hw);
2628
2629     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "cosa PHY_LCK ver=2\n");
2630     _rtl92d_phy_lc_calibrate_sw(hw, is2t);
2631 }
2632
2633 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2634 {
2635     struct rtl_priv *rtlpriv = rtl_priv(hw);
2636     struct rtl_phy *rtlphy = &(rtlpriv->phy);
2637     struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2638     u32 timeout = 2000, timecount = 0;
2639
2640     while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2641         udelay(50);
2642         timecount += 50;
2643     }
2644
2645     rtlphy->lck_inprogress = true;
2646     RTPRINT(rtlpriv, FINIT, INIT_IQK,
2647         "LCK:Start!!! currentband %x delay %d ms\n",
2648         rtlhal->current_bandtype, timecount);
2649     if (IS_92D_SINGLEPHY(rtlhal->version)) {
2650         _rtl92d_phy_lc_calibrate(hw, true);
2651     } else {
2652         /* For 1T1R */
2653         _rtl92d_phy_lc_calibrate(hw, false);
2654     }
2655     rtlphy->lck_inprogress = false;
2656     RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LCK:Finish!!!\n");
2657 }
2658
2659 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
2660 {
2661     return;
2662 }
2663
2664 static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2665         u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2666         u32 para1, u32 para2, u32 msdelay)
2667 {
2668     struct swchnlcmd *pcmd;
2669
2670     if (cmdtable == NULL) {
2671         WARN_ONCE(true, "rtl8192de: cmdtable cannot be NULL\n");
2672         return false;
2673     }
2674     if (cmdtableidx >= cmdtablesz)
2675         return false;
2676
2677     pcmd = cmdtable + cmdtableidx;
2678     pcmd->cmdid = cmdid;
2679     pcmd->para1 = para1;
2680     pcmd->para2 = para2;
2681     pcmd->msdelay = msdelay;
2682     return true;
2683 }
2684
2685 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2686 {
2687     struct rtl_priv *rtlpriv = rtl_priv(hw);
2688     struct rtl_phy *rtlphy = &(rtlpriv->phy);
2689     u8 i;
2690
2691     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2692         "settings regs %zu default regs %d\n",
2693         ARRAY_SIZE(rtlphy->iqk_matrix),
2694         IQK_MATRIX_REG_NUM);
2695     /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
2696     for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
2697         rtlphy->iqk_matrix[i].value[0][0] = 0x100;
2698         rtlphy->iqk_matrix[i].value[0][2] = 0x100;
2699         rtlphy->iqk_matrix[i].value[0][4] = 0x100;
2700         rtlphy->iqk_matrix[i].value[0][6] = 0x100;
2701         rtlphy->iqk_matrix[i].value[0][1] = 0x0;
2702         rtlphy->iqk_matrix[i].value[0][3] = 0x0;
2703         rtlphy->iqk_matrix[i].value[0][5] = 0x0;
2704         rtlphy->iqk_matrix[i].value[0][7] = 0x0;
2705         rtlphy->iqk_matrix[i].iqk_done = false;
2706     }
2707 }
2708
2709 static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2710                          u8 channel, u8 *stage, u8 *step,
2711                          u32 *delay)
2712 {
2713     struct rtl_priv *rtlpriv = rtl_priv(hw);
2714     struct rtl_phy *rtlphy = &(rtlpriv->phy);
2715     struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2716     u32 precommoncmdcnt;
2717     struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2718     u32 postcommoncmdcnt;
2719     struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
2720     u32 rfdependcmdcnt;
2721     struct swchnlcmd *currentcmd = NULL;
2722     u8 rfpath;
2723     u8 num_total_rfpath = rtlphy->num_total_rfpath;
2724
2725     precommoncmdcnt = 0;
2726     _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2727                      MAX_PRECMD_CNT,
2728                      CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
2729     _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2730                      MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
2731     postcommoncmdcnt = 0;
2732     _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
2733                      MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
2734     rfdependcmdcnt = 0;
2735     _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2736                      MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
2737                      RF_CHNLBW, channel, 0);
2738     _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2739                      MAX_RFDEPENDCMD_CNT, CMDID_END,
2740                      0, 0, 0);
2741
2742     do {
2743         switch (*stage) {
2744         case 0:
2745             currentcmd = &precommoncmd[*step];
2746             break;
2747         case 1:
2748             currentcmd = &rfdependcmd[*step];
2749             break;
2750         case 2:
2751             currentcmd = &postcommoncmd[*step];
2752             break;
2753         }
2754         if (currentcmd->cmdid == CMDID_END) {
2755             if ((*stage) == 2) {
2756                 return true;
2757             } else {
2758                 (*stage)++;
2759                 (*step) = 0;
2760                 continue;
2761             }
2762         }
2763         switch (currentcmd->cmdid) {
2764         case CMDID_SET_TXPOWEROWER_LEVEL:
2765             rtl92d_phy_set_txpower_level(hw, channel);
2766             break;
2767         case CMDID_WRITEPORT_ULONG:
2768             rtl_write_dword(rtlpriv, currentcmd->para1,
2769                     currentcmd->para2);
2770             break;
2771         case CMDID_WRITEPORT_USHORT:
2772             rtl_write_word(rtlpriv, currentcmd->para1,
2773                        (u16)currentcmd->para2);
2774             break;
2775         case CMDID_WRITEPORT_UCHAR:
2776             rtl_write_byte(rtlpriv, currentcmd->para1,
2777                        (u8)currentcmd->para2);
2778             break;
2779         case CMDID_RF_WRITEREG:
2780             for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
2781                 rtlphy->rfreg_chnlval[rfpath] =
2782                     ((rtlphy->rfreg_chnlval[rfpath] &
2783                     0xffffff00) | currentcmd->para2);
2784                 if (rtlpriv->rtlhal.current_bandtype ==
2785                     BAND_ON_5G) {
2786                     if (currentcmd->para2 > 99)
2787                         rtlphy->rfreg_chnlval[rfpath] =
2788                             rtlphy->rfreg_chnlval
2789                             [rfpath] | (BIT(18));
2790                     else
2791                         rtlphy->rfreg_chnlval[rfpath] =
2792                             rtlphy->rfreg_chnlval
2793                             [rfpath] & (~BIT(18));
2794                     rtlphy->rfreg_chnlval[rfpath] |=
2795                          (BIT(16) | BIT(8));
2796                 } else {
2797                     rtlphy->rfreg_chnlval[rfpath] &=
2798                         ~(BIT(8) | BIT(16) | BIT(18));
2799                 }
2800                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
2801                           currentcmd->para1,
2802                           RFREG_OFFSET_MASK,
2803                           rtlphy->rfreg_chnlval[rfpath]);
2804                 _rtl92d_phy_reload_imr_setting(hw, channel,
2805                                    rfpath);
2806             }
2807             _rtl92d_phy_switch_rf_setting(hw, channel);
2808             /* do IQK when all parameters are ready */
2809             rtl92d_phy_reload_iqk_setting(hw, channel);
2810             break;
2811         default:
2812             pr_err("switch case %#x not processed\n",
2813                    currentcmd->cmdid);
2814             break;
2815         }
2816         break;
2817     } while (true);
2818     (*delay) = currentcmd->msdelay;
2819     (*step)++;
2820     return false;
2821 }
2822
2823 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
2824 {
2825     struct rtl_priv *rtlpriv = rtl_priv(hw);
2826     struct rtl_phy *rtlphy = &(rtlpriv->phy);
2827     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2828     u32 delay;
2829     u32 timeout = 1000, timecount = 0;
2830     u8 channel = rtlphy->current_channel;
2831     u32 ret_value;
2832
2833     if (rtlphy->sw_chnl_inprogress)
2834         return 0;
2835     if (rtlphy->set_bwmode_inprogress)
2836         return 0;
2837
2838     if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
2839         rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
2840             "sw_chnl_inprogress false driver sleep or unload\n");
2841         return 0;
2842     }
2843     while (rtlphy->lck_inprogress && timecount < timeout) {
2844         mdelay(50);
2845         timecount += 50;
2846     }
2847     if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
2848         rtlhal->bandset == BAND_ON_BOTH) {
2849         ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
2850                       MASKDWORD);
2851         if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2852             rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
2853         else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
2854             rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
2855     }
2856     switch (rtlhal->current_bandtype) {
2857     case BAND_ON_5G:
2858         /* Get first channel error when change between
2859          * 5G and 2.4G band. */
2860         if (WARN_ONCE(channel <= 14, "rtl8192de: 5G but channel<=14\n"))
2861             return 0;
2862         break;
2863     case BAND_ON_2_4G:
2864         /* Get first channel error when change between
2865          * 5G and 2.4G band. */
2866         if (WARN_ONCE(channel > 14, "rtl8192de: 2G but channel>14\n"))
2867             return 0;
2868         break;
2869     default:
2870         WARN_ONCE(true, "rtl8192de: Invalid WirelessMode(%#x)!!\n",
2871               rtlpriv->mac80211.mode);
2872         break;
2873     }
2874     rtlphy->sw_chnl_inprogress = true;
2875     if (channel == 0)
2876         channel = 1;
2877     rtlphy->sw_chnl_stage = 0;
2878     rtlphy->sw_chnl_step = 0;
2879     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
2880         "switch to channel%d\n", rtlphy->current_channel);
2881
2882     do {
2883         if (!rtlphy->sw_chnl_inprogress)
2884             break;
2885         if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
2886                               rtlphy->current_channel,
2887             &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
2888             if (delay > 0)
2889                 mdelay(delay);
2890             else
2891                 continue;
2892         } else {
2893             rtlphy->sw_chnl_inprogress = false;
2894         }
2895         break;
2896     } while (true);
2897     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
2898     rtlphy->sw_chnl_inprogress = false;
2899     return 1;
2900 }
2901
2902 static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
2903 {
2904     struct rtl_priv *rtlpriv = rtl_priv(hw);
2905     struct dig_t *de_digtable = &rtlpriv->dm_digtable;
2906     struct rtl_phy *rtlphy = &(rtlpriv->phy);
2907
2908     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2909         "--->Cmd(%#x), set_io_inprogress(%d)\n",
2910         rtlphy->current_io_type, rtlphy->set_io_inprogress);
2911     switch (rtlphy->current_io_type) {
2912     case IO_CMD_RESUME_DM_BY_SCAN:
2913         de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2914         rtl92d_dm_write_dig(hw);
2915         rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
2916         break;
2917     case IO_CMD_PAUSE_DM_BY_SCAN:
2918         rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue;
2919         de_digtable->cur_igvalue = 0x37;
2920         rtl92d_dm_write_dig(hw);
2921         break;
2922     default:
2923         pr_err("switch case %#x not processed\n",
2924                rtlphy->current_io_type);
2925         break;
2926     }
2927     rtlphy->set_io_inprogress = false;
2928     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
2929         rtlphy->current_io_type);
2930 }
2931
2932 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2933 {
2934     struct rtl_priv *rtlpriv = rtl_priv(hw);
2935     struct rtl_phy *rtlphy = &(rtlpriv->phy);
2936     bool postprocessing = false;
2937
2938     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2939         "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2940          iotype, rtlphy->set_io_inprogress);
2941     do {
2942         switch (iotype) {
2943         case IO_CMD_RESUME_DM_BY_SCAN:
2944             rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2945                 "[IO CMD] Resume DM after scan\n");
2946             postprocessing = true;
2947             break;
2948         case IO_CMD_PAUSE_DM_BY_SCAN:
2949             rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2950                 "[IO CMD] Pause DM before scan\n");
2951             postprocessing = true;
2952             break;
2953         default:
2954             pr_err("switch case %#x not processed\n",
2955                    iotype);
2956             break;
2957         }
2958     } while (false);
2959     if (postprocessing && !rtlphy->set_io_inprogress) {
2960         rtlphy->set_io_inprogress = true;
2961         rtlphy->current_io_type = iotype;
2962     } else {
2963         return false;
2964     }
2965     rtl92d_phy_set_io(hw);
2966     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
2967     return true;
2968 }
2969
2970 static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
2971 {
2972     struct rtl_priv *rtlpriv = rtl_priv(hw);
2973
2974     /* a.  SYS_CLKR 0x08[11] = 1  restore MAC clock */
2975     /* b.  SPS_CTRL 0x11[7:0] = 0x2b */
2976     if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
2977         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2978     /* c.  For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
2979     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2980     /* RF_ON_EXCEP(d~g): */
2981     /* d.  APSD_CTRL 0x600[7:0] = 0x00 */
2982     rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2983     /* e.  SYS_FUNC_EN 0x02[7:0] = 0xE2  reset BB TRX function again */
2984     /* f.  SYS_FUNC_EN 0x02[7:0] = 0xE3  enable BB TRX function*/
2985     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2986     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2987     /* g.   txpause 0x522[7:0] = 0x00  enable mac tx queue */
2988     rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2989 }
2990
2991 static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
2992 {
2993     struct rtl_priv *rtlpriv = rtl_priv(hw);
2994     u32 u4btmp;
2995     u8 delay = 5;
2996
2997     /* a.   TXPAUSE 0x522[7:0] = 0xFF  Pause MAC TX queue  */
2998     rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2999     /* b.   RF path 0 offset 0x00 = 0x00  disable RF  */
3000     rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3001     /* c.   APSD_CTRL 0x600[7:0] = 0x40 */
3002     rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3003     /* d. APSD_CTRL 0x600[7:0] = 0x00
3004      * APSD_CTRL 0x600[7:0] = 0x00
3005      * RF path 0 offset 0x00 = 0x00
3006      * APSD_CTRL 0x600[7:0] = 0x40
3007      * */
3008     u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3009     while (u4btmp != 0 && delay > 0) {
3010         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3011         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3012         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3013         u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3014         delay--;
3015     }
3016     if (delay == 0) {
3017         /* Jump out the LPS turn off sequence to RF_ON_EXCEP */
3018         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3019
3020         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3021         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3022         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3023         rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3024             "Fail !!! Switch RF timeout\n");
3025         return;
3026     }
3027     /* e.   For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
3028     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3029     /* f.   SPS_CTRL 0x11[7:0] = 0x22 */
3030     if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3031         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3032     /* g.    SYS_CLKR 0x08[11] = 0  gated MAC clock */
3033 }
3034
3035 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3036                    enum rf_pwrstate rfpwr_state)
3037 {
3038
3039     bool bresult = true;
3040     struct rtl_priv *rtlpriv = rtl_priv(hw);
3041     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3042     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3043     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3044     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3045     u8 i, queue_id;
3046     struct rtl8192_tx_ring *ring = NULL;
3047
3048     if (rfpwr_state == ppsc->rfpwr_state)
3049         return false;
3050     switch (rfpwr_state) {
3051     case ERFON:
3052         if ((ppsc->rfpwr_state == ERFOFF) &&
3053             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3054             bool rtstatus;
3055             u32 initializecount = 0;
3056             do {
3057                 initializecount++;
3058                 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3059                     "IPS Set eRf nic enable\n");
3060                 rtstatus = rtl_ps_enable_nic(hw);
3061             } while (!rtstatus && (initializecount < 10));
3062
3063             RT_CLEAR_PS_LEVEL(ppsc,
3064                       RT_RF_OFF_LEVL_HALT_NIC);
3065         } else {
3066             rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3067                 "awake, slept:%d ms state_inap:%x\n",
3068                 jiffies_to_msecs(jiffies -
3069                          ppsc->last_sleep_jiffies),
3070                  rtlpriv->psc.state_inap);
3071             ppsc->last_awake_jiffies = jiffies;
3072             _rtl92d_phy_set_rfon(hw);
3073         }
3074
3075         if (mac->link_state == MAC80211_LINKED)
3076             rtlpriv->cfg->ops->led_control(hw,
3077                      LED_CTL_LINK);
3078         else
3079             rtlpriv->cfg->ops->led_control(hw,
3080                      LED_CTL_NO_LINK);
3081         break;
3082     case ERFOFF:
3083         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3084             rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3085                 "IPS Set eRf nic disable\n");
3086             rtl_ps_disable_nic(hw);
3087             RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3088         } else {
3089             if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3090                 rtlpriv->cfg->ops->led_control(hw,
3091                          LED_CTL_NO_LINK);
3092             else
3093                 rtlpriv->cfg->ops->led_control(hw,
3094                          LED_CTL_POWER_OFF);
3095         }
3096         break;
3097     case ERFSLEEP:
3098         if (ppsc->rfpwr_state == ERFOFF)
3099             return false;
3100
3101         for (queue_id = 0, i = 0;
3102              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3103             ring = &pcipriv->dev.tx_ring[queue_id];
3104             if (skb_queue_len(&ring->queue) == 0 ||
3105                 queue_id == BEACON_QUEUE) {
3106                 queue_id++;
3107                 continue;
3108             } else if (rtlpci->pdev->current_state != PCI_D0) {
3109                 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3110                     "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n",
3111                     i + 1, queue_id);
3112                 break;
3113             } else {
3114                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3115                     "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3116                     i + 1, queue_id,
3117                     skb_queue_len(&ring->queue));
3118                 udelay(10);
3119                 i++;
3120             }
3121
3122             if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3123                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3124                     "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
3125                     MAX_DOZE_WAITING_TIMES_9x, queue_id,
3126                     skb_queue_len(&ring->queue));
3127                 break;
3128             }
3129         }
3130         rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3131             "Set rfsleep awakened:%d ms\n",
3132              jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
3133         rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3134             "sleep awakened:%d ms state_inap:%x\n",
3135             jiffies_to_msecs(jiffies -
3136                      ppsc->last_awake_jiffies),
3137             rtlpriv->psc.state_inap);
3138         ppsc->last_sleep_jiffies = jiffies;
3139         _rtl92d_phy_set_rfsleep(hw);
3140         break;
3141     default:
3142         pr_err("switch case %#x not processed\n",
3143                rfpwr_state);
3144         bresult = false;
3145         break;
3146     }
3147     if (bresult)
3148         ppsc->rfpwr_state = rfpwr_state;
3149     return bresult;
3150 }
3151
3152 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3153 {
3154     struct rtl_priv *rtlpriv = rtl_priv(hw);
3155     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3156     u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3157
3158     switch (rtlhal->macphymode) {
3159     case DUALMAC_DUALPHY:
3160         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3161             "MacPhyMode: DUALMAC_DUALPHY\n");
3162         rtl_write_byte(rtlpriv, offset, 0xF3);
3163         break;
3164     case SINGLEMAC_SINGLEPHY:
3165         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3166             "MacPhyMode: SINGLEMAC_SINGLEPHY\n");
3167         rtl_write_byte(rtlpriv, offset, 0xF4);
3168         break;
3169     case DUALMAC_SINGLEPHY:
3170         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3171             "MacPhyMode: DUALMAC_SINGLEPHY\n");
3172         rtl_write_byte(rtlpriv, offset, 0xF1);
3173         break;
3174     }
3175 }
3176
3177 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3178 {
3179     struct rtl_priv *rtlpriv = rtl_priv(hw);
3180     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3181     struct rtl_phy *rtlphy = &(rtlpriv->phy);
3182
3183     switch (rtlhal->macphymode) {
3184     case DUALMAC_SINGLEPHY:
3185         rtlphy->rf_type = RF_2T2R;
3186         rtlhal->version |= RF_TYPE_2T2R;
3187         rtlhal->bandset = BAND_ON_BOTH;
3188         rtlhal->current_bandtype = BAND_ON_2_4G;
3189         break;
3190
3191     case SINGLEMAC_SINGLEPHY:
3192         rtlphy->rf_type = RF_2T2R;
3193         rtlhal->version |= RF_TYPE_2T2R;
3194         rtlhal->bandset = BAND_ON_BOTH;
3195         rtlhal->current_bandtype = BAND_ON_2_4G;
3196         break;
3197
3198     case DUALMAC_DUALPHY:
3199         rtlphy->rf_type = RF_1T1R;
3200         rtlhal->version &= RF_TYPE_1T1R;
3201         /* Now we let MAC0 run on 5G band. */
3202         if (rtlhal->interfaceindex == 0) {
3203             rtlhal->bandset = BAND_ON_5G;
3204             rtlhal->current_bandtype = BAND_ON_5G;
3205         } else {
3206             rtlhal->bandset = BAND_ON_2_4G;
3207             rtlhal->current_bandtype = BAND_ON_2_4G;
3208         }
3209         break;
3210     default:
3211         break;
3212     }
3213 }
3214
3215 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3216 {
3217     u8 group;
3218
3219     if (channel_all[chnl] <= 3)
3220         group = 0;
3221     else if (channel_all[chnl] <= 9)
3222         group = 1;
3223     else if (channel_all[chnl] <= 14)
3224         group = 2;
3225     else if (channel_all[chnl] <= 44)
3226         group = 3;
3227     else if (channel_all[chnl] <= 54)
3228         group = 4;
3229     else if (channel_all[chnl] <= 64)
3230         group = 5;
3231     else if (channel_all[chnl] <= 112)
3232         group = 6;
3233     else if (channel_all[chnl] <= 126)
3234         group = 7;
3235     else if (channel_all[chnl] <= 140)
3236         group = 8;
3237     else if (channel_all[chnl] <= 153)
3238         group = 9;
3239     else if (channel_all[chnl] <= 159)
3240         group = 10;
3241     else
3242         group = 11;
3243     return group;
3244 }
3245
3246 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3247 {
3248     struct rtl_priv *rtlpriv = rtl_priv(hw);
3249     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3250     unsigned long flags;
3251     u8 value8;
3252     u16 i;
3253     u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3254
3255     /* notice fw know band status  0x81[1]/0x53[1] = 0: 5G, 1: 2G */
3256     if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3257         value8 = rtl_read_byte(rtlpriv, mac_reg);
3258         value8 |= BIT(1);
3259         rtl_write_byte(rtlpriv, mac_reg, value8);
3260     } else {
3261         value8 = rtl_read_byte(rtlpriv, mac_reg);
3262         value8 &= (~BIT(1));
3263         rtl_write_byte(rtlpriv, mac_reg, value8);
3264     }
3265
3266     if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3267         value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3268         rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3269     } else {
3270         spin_lock_irqsave(&globalmutex_power, flags);
3271         if (rtlhal->interfaceindex == 0) {
3272             value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3273             rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3274         } else {
3275             value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3276             rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3277         }
3278         value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3279         spin_unlock_irqrestore(&globalmutex_power, flags);
3280         for (i = 0; i < 200; i++) {
3281             if ((value8 & BIT(7)) == 0) {
3282                 break;
3283             } else {
3284                 udelay(500);
3285                 spin_lock_irqsave(&globalmutex_power, flags);
3286                 value8 = rtl_read_byte(rtlpriv,
3287                             REG_POWER_OFF_IN_PROCESS);
3288                 spin_unlock_irqrestore(&globalmutex_power,
3289                                flags);
3290             }
3291         }
3292         if (i == 200)
3293             WARN_ONCE(true, "rtl8192de: Another mac power off over time\n");
3294     }
3295 }
3296
3297 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3298 {
3299     struct rtl_priv *rtlpriv = rtl_priv(hw);
3300
3301     switch (rtlpriv->rtlhal.macphymode) {
3302     case DUALMAC_DUALPHY:
3303         rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3304         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3305         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3306         break;
3307     case DUALMAC_SINGLEPHY:
3308         rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3309         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3310         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3311         break;
3312     case SINGLEMAC_SINGLEPHY:
3313         rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3314         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3315         rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3316         break;
3317     default:
3318         break;
3319     }
3320 }
3321
3322 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3323 {
3324     struct rtl_priv *rtlpriv = rtl_priv(hw);
3325     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3326     struct rtl_phy *rtlphy = &(rtlpriv->phy);
3327     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3328     u8 rfpath, i;
3329
3330     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
3331     /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
3332     if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3333         /* r_select_5G for path_A/B,0x878 */
3334         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3335         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3336         if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3337             rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3338             rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3339         }
3340         /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3341         rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3342         /* fc_area  0xd2c */
3343         rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3344         /* 5G LAN ON */
3345         rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3346         /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3347         rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3348                   0x40000100);
3349         rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3350                   0x40000100);
3351         if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3352             rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3353                       BIT(10) | BIT(6) | BIT(5),
3354                       ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3355                       (rtlefuse->eeprom_c9 & BIT(1)) |
3356                       ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3357             rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3358                       BIT(10) | BIT(6) | BIT(5),
3359                       ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3360                       ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3361                       ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3362             rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3363         } else {
3364             rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3365                       BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3366                       BIT(6) | BIT(5),
3367                       ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3368                       (rtlefuse->eeprom_c9 & BIT(1)) |
3369                       ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3370                       ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3371                       ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3372                       ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3373             rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3374                       BIT(10) | BIT(6) | BIT(5),
3375                       ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3376                       ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3377                       ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3378             rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3379                       BIT(10) | BIT(6) | BIT(5),
3380                       ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3381                       ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3382                       ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3383             rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3384                       BIT(31) | BIT(15), 0);
3385         }
3386         /* 1.5V_LDO */
3387     } else {
3388         /* r_select_5G for path_A/B */
3389         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3390         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3391         if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3392             rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3393             rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3394         }
3395         /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3396         rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3397         /* fc_area */
3398         rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3399         /* 5G LAN ON */
3400         rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3401         /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3402         if (rtlefuse->internal_pa_5g[0])
3403             rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3404                       0x2d4000b5);
3405         else
3406             rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3407                       0x20000080);
3408         if (rtlefuse->internal_pa_5g[1])
3409             rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3410                       0x2d4000b5);
3411         else
3412             rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3413                       0x20000080);
3414         if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3415             rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3416                       BIT(10) | BIT(6) | BIT(5),
3417                       (rtlefuse->eeprom_cc & BIT(5)));
3418             rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3419                       ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3420             rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3421                       (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3422         } else {
3423             rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3424                       BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3425                       BIT(6) | BIT(5),
3426                       (rtlefuse->eeprom_cc & BIT(5)) |
3427                       ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3428             rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3429                       ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3430             rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3431                       ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3432             rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3433                       BIT(31) | BIT(15),
3434                       ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3435                       ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3436         }
3437     }
3438     /* update IQK related settings */
3439     rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
3440     rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
3441     rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00);
3442     rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3443               BIT(26) | BIT(24), 0x00);
3444     rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00);
3445     rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3446     rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3447
3448     /* Update RF */
3449     for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3450          rfpath++) {
3451         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3452             /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
3453             rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3454                       BIT(18), 0);
3455             /* RF0x0b[16:14] =3b'111 */
3456             rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3457                       0x1c000, 0x07);
3458         } else {
3459             /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
3460             rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3461                       BIT(16) | BIT(18),
3462                       (BIT(16) | BIT(8)) >> 8);
3463         }
3464     }
3465     /* Update for all band. */
3466     /* DMDP */
3467     if (rtlphy->rf_type == RF_1T1R) {
3468         /* Use antenna 0,0xc04,0xd04 */
3469         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
3470         rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3471
3472         /* enable ad/da clock1 for dual-phy reg0x888 */
3473         if (rtlhal->interfaceindex == 0) {
3474             rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3475                       BIT(13), 0x3);
3476         } else {
3477             rtl92d_phy_enable_anotherphy(hw, false);
3478             rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3479                 "MAC1 use DBI to update 0x888\n");
3480             /* 0x888 */
3481             rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3482                         rtl92de_read_dword_dbi(hw,
3483                         RFPGA0_ADDALLOCKEN,
3484                         BIT(3)) | BIT(12) | BIT(13),
3485                         BIT(3));
3486             rtl92d_phy_powerdown_anotherphy(hw, false);
3487         }
3488     } else {
3489         /* Single PHY */
3490         /* Use antenna 0 & 1,0xc04,0xd04 */
3491         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
3492         rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3493         /* disable ad/da clock1,0x888 */
3494         rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3495     }
3496     for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3497          rfpath++) {
3498         rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3499                         RF_CHNLBW, RFREG_OFFSET_MASK);
3500         rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3501             RFREG_OFFSET_MASK);
3502     }
3503     for (i = 0; i < 2; i++)
3504         rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
3505             rtlphy->rfreg_chnlval[i]);
3506     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n");
3507
3508 }
3509
3510 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3511 {
3512     struct rtl_priv *rtlpriv = rtl_priv(hw);
3513     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3514     u8 u1btmp;
3515     unsigned long flags;
3516
3517     if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3518         u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3519         rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3520         return true;
3521     }
3522     spin_lock_irqsave(&globalmutex_power, flags);
3523     if (rtlhal->interfaceindex == 0) {
3524         u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3525         rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3526         u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3527         u1btmp &= MAC1_ON;
3528     } else {
3529         u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3530         rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3531         u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3532         u1btmp &= MAC0_ON;
3533     }
3534     if (u1btmp) {
3535         spin_unlock_irqrestore(&globalmutex_power, flags);
3536         return false;
3537     }
3538     u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3539     u1btmp |= BIT(7);
3540     rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3541     spin_unlock_irqrestore(&globalmutex_power, flags);
3542     return true;
3543 }