rtlwifi/rtl8192de/def.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003
0004 #ifndef __RTL92D_DEF_H__
0005 #define __RTL92D_DEF_H__
0006
0007 /* Min Spacing related settings. */
0008 #define MAX_MSS_DENSITY_2T              0x13
0009 #define MAX_MSS_DENSITY_1T              0x0A
0010
0011 #define RF6052_MAX_TX_PWR               0x3F
0012 #define RF6052_MAX_PATH                 2
0013
0014 #define PHY_RSSI_SLID_WIN_MAX               100
0015 #define PHY_LINKQUALITY_SLID_WIN_MAX            20
0016 #define PHY_BEACON_RSSI_SLID_WIN_MAX            10
0017
0018 #define RT_AC_INT_MASKS     (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
0019
0020 #define RX_SMOOTH_FACTOR                20
0021
0022 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
0023 #define HAL_PRIME_CHNL_OFFSET_LOWER         1
0024 #define HAL_PRIME_CHNL_OFFSET_UPPER         2
0025
0026 #define RX_MPDU_QUEUE                   0
0027 #define RX_CMD_QUEUE                    1
0028
0029 enum version_8192d {
0030     VERSION_TEST_CHIP_88C = 0x0000,
0031     VERSION_TEST_CHIP_92C = 0x0020,
0032     VERSION_TEST_UMC_CHIP_8723 = 0x0081,
0033     VERSION_NORMAL_TSMC_CHIP_88C = 0x0008,
0034     VERSION_NORMAL_TSMC_CHIP_92C = 0x0028,
0035     VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018,
0036     VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088,
0037     VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8,
0038     VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098,
0039     VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089,
0040     VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089,
0041     VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088,
0042     VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8,
0043     VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090,
0044     VERSION_TEST_CHIP_92D_SINGLEPHY = 0x0022,
0045     VERSION_TEST_CHIP_92D_DUALPHY = 0x0002,
0046     VERSION_NORMAL_CHIP_92D_SINGLEPHY = 0x002a,
0047     VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a,
0048     VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a,
0049     VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a,
0050     VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a,
0051     VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a,
0052     VERSION_NORMAL_CHIP_92D_E_CUT_SINGLEPHY = 0x402a,
0053     VERSION_NORMAL_CHIP_92D_E_CUT_DUALPHY = 0x400a,
0054 };
0055
0056 /* for 92D */
0057 #define CHIP_92D_SINGLEPHY      BIT(9)
0058
0059 /* Chip specific */
0060 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
0061 #define CHIP_BONDING_92C_1T2R           0x1
0062 #define CHIP_BONDING_88C_USB_MCARD      0x2
0063 #define CHIP_BONDING_88C_USB_HP         0x1
0064
0065 /* [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3 */
0066 /* [7] Manufacturer: TSMC=0, UMC=1 */
0067 /* [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2 */
0068 /* [3] Chip type: TEST=0, NORMAL=1 */
0069 /* [2:0] IC type: 81xxC=0, 8723=1, 92D=2 */
0070 #define CHIP_8723           BIT(0)
0071 #define CHIP_92D            BIT(1)
0072 #define NORMAL_CHIP         BIT(3)
0073 #define RF_TYPE_1T1R            (~(BIT(4)|BIT(5)|BIT(6)))
0074 #define RF_TYPE_1T2R            BIT(4)
0075 #define RF_TYPE_2T2R            BIT(5)
0076 #define CHIP_VENDOR_UMC         BIT(7)
0077 #define CHIP_92D_B_CUT          BIT(12)
0078 #define CHIP_92D_C_CUT          BIT(13)
0079 #define CHIP_92D_D_CUT          (BIT(13)|BIT(12))
0080 #define CHIP_92D_E_CUT          BIT(14)
0081
0082 /* MASK */
0083 #define IC_TYPE_MASK            (BIT(0)|BIT(1)|BIT(2))
0084 #define CHIP_TYPE_MASK          BIT(3)
0085 #define RF_TYPE_MASK            (BIT(4)|BIT(5)|BIT(6))
0086 #define MANUFACTUER_MASK        BIT(7)
0087 #define ROM_VERSION_MASK        (BIT(11)|BIT(10)|BIT(9)|BIT(8))
0088 #define CUT_VERSION_MASK        (BIT(15)|BIT(14)|BIT(13)|BIT(12))
0089
0090
0091 /* Get element */
0092 #define GET_CVID_IC_TYPE(version)   ((version) & IC_TYPE_MASK)
0093 #define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
0094 #define GET_CVID_RF_TYPE(version)   ((version) & RF_TYPE_MASK)
0095 #define GET_CVID_MANUFACTUER(version)   ((version) & MANUFACTUER_MASK)
0096 #define GET_CVID_ROM_VERSION(version)   ((version) & ROM_VERSION_MASK)
0097 #define GET_CVID_CUT_VERSION(version)   ((version) & CUT_VERSION_MASK)
0098
0099 #define IS_1T1R(version)        ((GET_CVID_RF_TYPE(version)) ?  \
0100                      false : true)
0101 #define IS_1T2R(version)        ((GET_CVID_RF_TYPE(version) ==  \
0102                      RF_TYPE_1T2R) ? true : false)
0103 #define IS_2T2R(version)        ((GET_CVID_RF_TYPE(version) ==  \
0104                      RF_TYPE_2T2R) ? true : false)
0105
0106 #define IS_92D_SINGLEPHY(version)   ((IS_92D(version)) ?        \
0107                  (IS_2T2R(version) ? true : false) : false)
0108 #define IS_92D(version)         ((GET_CVID_IC_TYPE(version) ==  \
0109                      CHIP_92D) ? true : false)
0110 #define IS_92D_C_CUT(version)       ((IS_92D(version)) ?        \
0111                  ((GET_CVID_CUT_VERSION(version) == \
0112                  CHIP_92D_C_CUT) ? true : false) : false)
0113 #define IS_92D_D_CUT(version)           ((IS_92D(version)) ?    \
0114                  ((GET_CVID_CUT_VERSION(version) == \
0115                  CHIP_92D_D_CUT) ? true : false) : false)
0116 #define IS_92D_E_CUT(version)       ((IS_92D(version)) ?        \
0117                  ((GET_CVID_CUT_VERSION(version) == \
0118                  CHIP_92D_E_CUT) ? true : false) : false)
0119
0120 enum rf_optype {
0121     RF_OP_BY_SW_3WIRE = 0,
0122     RF_OP_BY_FW,
0123     RF_OP_MAX
0124 };
0125
0126 enum rtl_desc_qsel {
0127     QSLT_BK = 0x2,
0128     QSLT_BE = 0x0,
0129     QSLT_VI = 0x5,
0130     QSLT_VO = 0x7,
0131     QSLT_BEACON = 0x10,
0132     QSLT_HIGH = 0x11,
0133     QSLT_MGNT = 0x12,
0134     QSLT_CMD = 0x13,
0135 };
0136
0137 enum channel_plan {
0138     CHPL_FCC    = 0,
0139     CHPL_IC     = 1,
0140     CHPL_ETSI   = 2,
0141     CHPL_SPAIN  = 3,
0142     CHPL_FRANCE = 4,
0143     CHPL_MKK    = 5,
0144     CHPL_MKK1   = 6,
0145     CHPL_ISRAEL = 7,
0146     CHPL_TELEC  = 8,
0147     CHPL_GLOBAL = 9,
0148     CHPL_WORLD  = 10,
0149 };
0150
0151 struct phy_sts_cck_8192d {
0152     u8 adc_pwdb_X[4];
0153     u8 sq_rpt;
0154     u8 cck_agc_rpt;
0155 };
0156
0157 struct h2c_cmd_8192c {
0158     u8 element_id;
0159     u32 cmd_len;
0160     u8 *p_cmdbuffer;
0161 };
0162
0163 struct txpower_info {
0164     u8 cck_index[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
0165     u8 ht40_1sindex[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
0166     u8 ht40_2sindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
0167     u8 ht20indexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
0168     u8 ofdmindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
0169     u8 ht40maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
0170     u8 ht20maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
0171     u8 tssi_a[3];       /* 5GL/5GM/5GH */
0172     u8 tssi_b[3];
0173 };
0174
0175 #endif