0001
0002
0003
0004 #include "../wifi.h"
0005 #include "../pci.h"
0006 #include "../ps.h"
0007 #include "../core.h"
0008 #include "reg.h"
0009 #include "def.h"
0010 #include "hw.h"
0011 #include "phy.h"
0012 #include "../rtl8192c/phy_common.h"
0013 #include "rf.h"
0014 #include "dm.h"
0015 #include "../rtl8192c/dm_common.h"
0016 #include "../rtl8192c/fw_common.h"
0017 #include "table.h"
0018
0019 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
0020
0021 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
0022 enum radio_path rfpath, u32 regaddr, u32 bitmask)
0023 {
0024 struct rtl_priv *rtlpriv = rtl_priv(hw);
0025 u32 original_value, readback_value, bitshift;
0026 struct rtl_phy *rtlphy = &(rtlpriv->phy);
0027
0028 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0029 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
0030 regaddr, rfpath, bitmask);
0031
0032 spin_lock(&rtlpriv->locks.rf_lock);
0033
0034 if (rtlphy->rf_mode != RF_OP_BY_FW) {
0035 original_value = _rtl92c_phy_rf_serial_read(hw,
0036 rfpath, regaddr);
0037 } else {
0038 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
0039 rfpath, regaddr);
0040 }
0041
0042 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
0043 readback_value = (original_value & bitmask) >> bitshift;
0044
0045 spin_unlock(&rtlpriv->locks.rf_lock);
0046
0047 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0048 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
0049 regaddr, rfpath, bitmask, original_value);
0050
0051 return readback_value;
0052 }
0053
0054 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
0055 {
0056 struct rtl_priv *rtlpriv = rtl_priv(hw);
0057 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0058 bool is92c = IS_92C_SERIAL(rtlhal->version);
0059 bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
0060
0061 if (is92c)
0062 rtl_write_byte(rtlpriv, 0x14, 0x71);
0063 else
0064 rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
0065 return rtstatus;
0066 }
0067
0068 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
0069 {
0070 bool rtstatus = true;
0071 struct rtl_priv *rtlpriv = rtl_priv(hw);
0072 u16 regval;
0073 u32 regvaldw;
0074 u8 reg_hwparafile = 1;
0075
0076 _rtl92c_phy_init_bb_rf_register_definition(hw);
0077 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
0078 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
0079 regval | BIT(13) | BIT(0) | BIT(1));
0080 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
0081 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
0082 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
0083 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
0084 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
0085 FEN_BB_GLB_RSTN | FEN_BBRSTB);
0086 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
0087 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
0088 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
0089 if (reg_hwparafile == 1)
0090 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
0091 return rtstatus;
0092 }
0093
0094 void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
0095 enum radio_path rfpath,
0096 u32 regaddr, u32 bitmask, u32 data)
0097 {
0098 struct rtl_priv *rtlpriv = rtl_priv(hw);
0099 struct rtl_phy *rtlphy = &(rtlpriv->phy);
0100 u32 original_value, bitshift;
0101
0102 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0103 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
0104 regaddr, bitmask, data, rfpath);
0105
0106 spin_lock(&rtlpriv->locks.rf_lock);
0107
0108 if (rtlphy->rf_mode != RF_OP_BY_FW) {
0109 if (bitmask != RFREG_OFFSET_MASK) {
0110 original_value = _rtl92c_phy_rf_serial_read(hw,
0111 rfpath,
0112 regaddr);
0113 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
0114 data =
0115 ((original_value & (~bitmask)) |
0116 (data << bitshift));
0117 }
0118
0119 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
0120 } else {
0121 if (bitmask != RFREG_OFFSET_MASK) {
0122 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
0123 rfpath,
0124 regaddr);
0125 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
0126 data =
0127 ((original_value & (~bitmask)) |
0128 (data << bitshift));
0129 }
0130 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
0131 }
0132
0133 spin_unlock(&rtlpriv->locks.rf_lock);
0134
0135 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0136 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
0137 regaddr, bitmask, data, rfpath);
0138 }
0139
0140 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
0141 {
0142 struct rtl_priv *rtlpriv = rtl_priv(hw);
0143 u32 i;
0144 u32 arraylength;
0145 u32 *ptrarray;
0146
0147 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
0148 arraylength = MAC_2T_ARRAYLENGTH;
0149 ptrarray = RTL8192CEMAC_2T_ARRAY;
0150 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CEMAC_2T_ARRAY\n");
0151 for (i = 0; i < arraylength; i = i + 2)
0152 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
0153 return true;
0154 }
0155
0156 bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
0157 u8 configtype)
0158 {
0159 int i;
0160 u32 *phy_regarray_table;
0161 u32 *agctab_array_table;
0162 u16 phy_reg_arraylen, agctab_arraylen;
0163 struct rtl_priv *rtlpriv = rtl_priv(hw);
0164 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0165
0166 if (IS_92C_SERIAL(rtlhal->version)) {
0167 agctab_arraylen = AGCTAB_2TARRAYLENGTH;
0168 agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
0169 phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
0170 phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
0171 } else {
0172 agctab_arraylen = AGCTAB_1TARRAYLENGTH;
0173 agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
0174 phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
0175 phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
0176 }
0177 if (configtype == BASEBAND_CONFIG_PHY_REG) {
0178 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
0179 rtl_addr_delay(phy_regarray_table[i]);
0180 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
0181 phy_regarray_table[i + 1]);
0182 udelay(1);
0183 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0184 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
0185 phy_regarray_table[i],
0186 phy_regarray_table[i + 1]);
0187 }
0188 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
0189 for (i = 0; i < agctab_arraylen; i = i + 2) {
0190 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
0191 agctab_array_table[i + 1]);
0192 udelay(1);
0193 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0194 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
0195 agctab_array_table[i],
0196 agctab_array_table[i + 1]);
0197 }
0198 }
0199 return true;
0200 }
0201
0202 bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
0203 u8 configtype)
0204 {
0205 struct rtl_priv *rtlpriv = rtl_priv(hw);
0206 int i;
0207 u32 *phy_regarray_table_pg;
0208 u16 phy_regarray_pg_len;
0209
0210 phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
0211 phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
0212
0213 if (configtype == BASEBAND_CONFIG_PHY_REG) {
0214 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
0215 rtl_addr_delay(phy_regarray_table_pg[i]);
0216
0217 _rtl92c_store_pwrindex_diffrate_offset(hw,
0218 phy_regarray_table_pg[i],
0219 phy_regarray_table_pg[i + 1],
0220 phy_regarray_table_pg[i + 2]);
0221 }
0222 } else {
0223
0224 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,
0225 "configtype != BaseBand_Config_PHY_REG\n");
0226 }
0227 return true;
0228 }
0229
0230 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
0231 enum radio_path rfpath)
0232 {
0233
0234 int i;
0235 u32 *radioa_array_table;
0236 u32 *radiob_array_table;
0237 u16 radioa_arraylen, radiob_arraylen;
0238 struct rtl_priv *rtlpriv = rtl_priv(hw);
0239 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0240
0241 if (IS_92C_SERIAL(rtlhal->version)) {
0242 radioa_arraylen = RADIOA_2TARRAYLENGTH;
0243 radioa_array_table = RTL8192CERADIOA_2TARRAY;
0244 radiob_arraylen = RADIOB_2TARRAYLENGTH;
0245 radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
0246 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0247 "Radio_A:RTL8192CERADIOA_2TARRAY\n");
0248 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0249 "Radio_B:RTL8192CE_RADIOB_2TARRAY\n");
0250 } else {
0251 radioa_arraylen = RADIOA_1TARRAYLENGTH;
0252 radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
0253 radiob_arraylen = RADIOB_1TARRAYLENGTH;
0254 radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
0255 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0256 "Radio_A:RTL8192CE_RADIOA_1TARRAY\n");
0257 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0258 "Radio_B:RTL8192CE_RADIOB_1TARRAY\n");
0259 }
0260 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
0261 switch (rfpath) {
0262 case RF90_PATH_A:
0263 for (i = 0; i < radioa_arraylen; i = i + 2) {
0264 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
0265 RFREG_OFFSET_MASK,
0266 radioa_array_table[i + 1]);
0267 }
0268 break;
0269 case RF90_PATH_B:
0270 for (i = 0; i < radiob_arraylen; i = i + 2) {
0271 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
0272 RFREG_OFFSET_MASK,
0273 radiob_array_table[i + 1]);
0274 }
0275 break;
0276 case RF90_PATH_C:
0277 case RF90_PATH_D:
0278 pr_info("Incorrect rfpath %#x\n", rfpath);
0279 break;
0280 default:
0281 pr_info("switch case %#x not processed\n", rfpath);
0282 break;
0283 }
0284 return true;
0285 }
0286
0287 void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
0288 {
0289 struct rtl_priv *rtlpriv = rtl_priv(hw);
0290 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0291 struct rtl_phy *rtlphy = &(rtlpriv->phy);
0292 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
0293 u8 reg_bw_opmode;
0294 u8 reg_prsr_rsc;
0295
0296 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
0297 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
0298 "20MHz" : "40MHz");
0299
0300 if (is_hal_stop(rtlhal)) {
0301 rtlphy->set_bwmode_inprogress = false;
0302 return;
0303 }
0304
0305 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
0306 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
0307
0308 switch (rtlphy->current_chan_bw) {
0309 case HT_CHANNEL_WIDTH_20:
0310 reg_bw_opmode |= BW_OPMODE_20MHZ;
0311 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
0312 break;
0313 case HT_CHANNEL_WIDTH_20_40:
0314 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
0315 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
0316 reg_prsr_rsc =
0317 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
0318 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
0319 break;
0320 default:
0321 pr_info("unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
0322 break;
0323 }
0324
0325 switch (rtlphy->current_chan_bw) {
0326 case HT_CHANNEL_WIDTH_20:
0327 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
0328 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
0329 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
0330 break;
0331 case HT_CHANNEL_WIDTH_20_40:
0332 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
0333 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
0334
0335 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
0336 (mac->cur_40_prime_sc >> 1));
0337 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
0338 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
0339
0340 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
0341 (mac->cur_40_prime_sc ==
0342 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
0343 break;
0344 default:
0345 pr_err("unknown bandwidth: %#X\n",
0346 rtlphy->current_chan_bw);
0347 break;
0348 }
0349 rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
0350 rtlphy->set_bwmode_inprogress = false;
0351 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
0352 }
0353
0354 void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
0355 {
0356 u8 tmpreg;
0357 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
0358 struct rtl_priv *rtlpriv = rtl_priv(hw);
0359
0360 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
0361
0362 if ((tmpreg & 0x70) != 0)
0363 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
0364 else
0365 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
0366
0367 if ((tmpreg & 0x70) != 0) {
0368 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
0369
0370 if (is2t)
0371 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
0372 MASK12BITS);
0373
0374 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
0375 (rf_a_mode & 0x8FFFF) | 0x10000);
0376
0377 if (is2t)
0378 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
0379 (rf_b_mode & 0x8FFFF) | 0x10000);
0380 }
0381 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
0382
0383 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
0384
0385 mdelay(100);
0386
0387 if ((tmpreg & 0x70) != 0) {
0388 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
0389 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
0390
0391 if (is2t)
0392 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
0393 rf_b_mode);
0394 } else {
0395 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
0396 }
0397 }
0398
0399 static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
0400 enum rf_pwrstate rfpwr_state)
0401 {
0402 struct rtl_priv *rtlpriv = rtl_priv(hw);
0403 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
0404 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
0405 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
0406 bool bresult = true;
0407 u8 i, queue_id;
0408 struct rtl8192_tx_ring *ring = NULL;
0409
0410 switch (rfpwr_state) {
0411 case ERFON:{
0412 if ((ppsc->rfpwr_state == ERFOFF) &&
0413 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
0414 bool rtstatus;
0415 u32 initializecount = 0;
0416
0417 do {
0418 initializecount++;
0419 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
0420 "IPS Set eRf nic enable\n");
0421 rtstatus = rtl_ps_enable_nic(hw);
0422 } while (!rtstatus && (initializecount < 10));
0423 RT_CLEAR_PS_LEVEL(ppsc,
0424 RT_RF_OFF_LEVL_HALT_NIC);
0425 } else {
0426 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
0427 "Set ERFON slept:%d ms\n",
0428 jiffies_to_msecs(jiffies -
0429 ppsc->last_sleep_jiffies));
0430 ppsc->last_awake_jiffies = jiffies;
0431 rtl92ce_phy_set_rf_on(hw);
0432 }
0433 if (mac->link_state == MAC80211_LINKED) {
0434 rtlpriv->cfg->ops->led_control(hw,
0435 LED_CTL_LINK);
0436 } else {
0437 rtlpriv->cfg->ops->led_control(hw,
0438 LED_CTL_NO_LINK);
0439 }
0440 break;
0441 }
0442 case ERFOFF:{
0443 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
0444 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
0445 "IPS Set eRf nic disable\n");
0446 rtl_ps_disable_nic(hw);
0447 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
0448 } else {
0449 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
0450 rtlpriv->cfg->ops->led_control(hw,
0451 LED_CTL_NO_LINK);
0452 } else {
0453 rtlpriv->cfg->ops->led_control(hw,
0454 LED_CTL_POWER_OFF);
0455 }
0456 }
0457 break;
0458 }
0459 case ERFSLEEP:{
0460 if (ppsc->rfpwr_state == ERFOFF)
0461 break;
0462 for (queue_id = 0, i = 0;
0463 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
0464 ring = &pcipriv->dev.tx_ring[queue_id];
0465 if (queue_id == BEACON_QUEUE ||
0466 skb_queue_len(&ring->queue) == 0) {
0467 queue_id++;
0468 continue;
0469 } else {
0470 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
0471 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
0472 i + 1, queue_id,
0473 skb_queue_len(&ring->queue));
0474
0475 udelay(10);
0476 i++;
0477 }
0478 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
0479 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
0480 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
0481 MAX_DOZE_WAITING_TIMES_9x,
0482 queue_id,
0483 skb_queue_len(&ring->queue));
0484 break;
0485 }
0486 }
0487 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
0488 "Set ERFSLEEP awaked:%d ms\n",
0489 jiffies_to_msecs(jiffies -
0490 ppsc->last_awake_jiffies));
0491 ppsc->last_sleep_jiffies = jiffies;
0492 _rtl92c_phy_set_rf_sleep(hw);
0493 break;
0494 }
0495 default:
0496 pr_err("switch case %#x not processed\n",
0497 rfpwr_state);
0498 bresult = false;
0499 break;
0500 }
0501 if (bresult)
0502 ppsc->rfpwr_state = rfpwr_state;
0503 return bresult;
0504 }
0505
0506 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
0507 enum rf_pwrstate rfpwr_state)
0508 {
0509 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
0510
0511 bool bresult = false;
0512
0513 if (rfpwr_state == ppsc->rfpwr_state)
0514 return bresult;
0515 bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
0516 return bresult;
0517 }
