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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003 
0004 #include "../wifi.h"
0005 #include "../efuse.h"
0006 #include "../base.h"
0007 #include "../regd.h"
0008 #include "../cam.h"
0009 #include "../ps.h"
0010 #include "../pci.h"
0011 #include "reg.h"
0012 #include "def.h"
0013 #include "phy.h"
0014 #include "../rtl8192c/dm_common.h"
0015 #include "../rtl8192c/fw_common.h"
0016 #include "../rtl8192c/phy_common.h"
0017 #include "dm.h"
0018 #include "led.h"
0019 #include "hw.h"
0020 
0021 #define LLT_CONFIG  5
0022 
0023 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
0024                       u8 set_bits, u8 clear_bits)
0025 {
0026     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0027     struct rtl_priv *rtlpriv = rtl_priv(hw);
0028 
0029     rtlpci->reg_bcn_ctrl_val |= set_bits;
0030     rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
0031 
0032     rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
0033 }
0034 
0035 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
0036 {
0037     struct rtl_priv *rtlpriv = rtl_priv(hw);
0038     u8 tmp1byte;
0039 
0040     tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
0041     rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
0042     rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
0043     tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
0044     tmp1byte &= ~(BIT(0));
0045     rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
0046 }
0047 
0048 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
0049 {
0050     struct rtl_priv *rtlpriv = rtl_priv(hw);
0051     u8 tmp1byte;
0052 
0053     tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
0054     rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
0055     rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
0056     tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
0057     tmp1byte |= BIT(0);
0058     rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
0059 }
0060 
0061 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
0062 {
0063     _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
0064 }
0065 
0066 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
0067 {
0068     _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
0069 }
0070 
0071 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
0072 {
0073     struct rtl_priv *rtlpriv = rtl_priv(hw);
0074     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
0075     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0076 
0077     switch (variable) {
0078     case HW_VAR_RCR:
0079         *((u32 *) (val)) = rtlpci->receive_config;
0080         break;
0081     case HW_VAR_RF_STATE:
0082         *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
0083         break;
0084     case HW_VAR_FWLPS_RF_ON:{
0085             enum rf_pwrstate rfstate;
0086             u32 val_rcr;
0087 
0088             rtlpriv->cfg->ops->get_hw_reg(hw,
0089                               HW_VAR_RF_STATE,
0090                               (u8 *)(&rfstate));
0091             if (rfstate == ERFOFF) {
0092                 *((bool *) (val)) = true;
0093             } else {
0094                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
0095                 val_rcr &= 0x00070000;
0096                 if (val_rcr)
0097                     *((bool *) (val)) = false;
0098                 else
0099                     *((bool *) (val)) = true;
0100             }
0101             break;
0102         }
0103     case HW_VAR_FW_PSMODE_STATUS:
0104         *((bool *) (val)) = ppsc->fw_current_inpsmode;
0105         break;
0106     case HW_VAR_CORRECT_TSF:{
0107         u64 tsf;
0108         u32 *ptsf_low = (u32 *)&tsf;
0109         u32 *ptsf_high = ((u32 *)&tsf) + 1;
0110 
0111         *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
0112         *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
0113 
0114         *((u64 *) (val)) = tsf;
0115 
0116         break;
0117         }
0118     case HAL_DEF_WOWLAN:
0119         break;
0120     default:
0121         pr_err("switch case %#x not processed\n", variable);
0122         break;
0123     }
0124 }
0125 
0126 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
0127 {
0128     struct rtl_priv *rtlpriv = rtl_priv(hw);
0129     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0130     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
0131     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0132     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0133     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
0134     u8 idx;
0135 
0136     switch (variable) {
0137     case HW_VAR_ETHER_ADDR:{
0138             for (idx = 0; idx < ETH_ALEN; idx++) {
0139                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
0140                            val[idx]);
0141             }
0142             break;
0143         }
0144     case HW_VAR_BASIC_RATE:{
0145             u16 rate_cfg = ((u16 *) val)[0];
0146             u8 rate_index = 0;
0147 
0148             rate_cfg &= 0x15f;
0149             rate_cfg |= 0x01;
0150             rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
0151             rtl_write_byte(rtlpriv, REG_RRSR + 1,
0152                        (rate_cfg >> 8) & 0xff);
0153             while (rate_cfg > 0x1) {
0154                 rate_cfg = (rate_cfg >> 1);
0155                 rate_index++;
0156             }
0157             rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
0158                        rate_index);
0159             break;
0160         }
0161     case HW_VAR_BSSID:{
0162             for (idx = 0; idx < ETH_ALEN; idx++) {
0163                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
0164                            val[idx]);
0165             }
0166             break;
0167         }
0168     case HW_VAR_SIFS:{
0169             rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
0170             rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
0171 
0172             rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
0173             rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
0174 
0175             if (!mac->ht_enable)
0176                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
0177                            0x0e0e);
0178             else
0179                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
0180                            *((u16 *) val));
0181             break;
0182         }
0183     case HW_VAR_SLOT_TIME:{
0184             u8 e_aci;
0185 
0186             rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
0187                 "HW_VAR_SLOT_TIME %x\n", val[0]);
0188 
0189             rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
0190 
0191             for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
0192                 rtlpriv->cfg->ops->set_hw_reg(hw,
0193                                   HW_VAR_AC_PARAM,
0194                                   &e_aci);
0195             }
0196             break;
0197         }
0198     case HW_VAR_ACK_PREAMBLE:{
0199             u8 reg_tmp;
0200             u8 short_preamble = (bool)*val;
0201 
0202             reg_tmp = (mac->cur_40_prime_sc) << 5;
0203             if (short_preamble)
0204                 reg_tmp |= 0x80;
0205 
0206             rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
0207             break;
0208         }
0209     case HW_VAR_AMPDU_MIN_SPACE:{
0210             u8 min_spacing_to_set;
0211             u8 sec_min_space;
0212 
0213             min_spacing_to_set = *val;
0214             if (min_spacing_to_set <= 7) {
0215                 sec_min_space = 0;
0216 
0217                 if (min_spacing_to_set < sec_min_space)
0218                     min_spacing_to_set = sec_min_space;
0219 
0220                 mac->min_space_cfg = ((mac->min_space_cfg &
0221                                0xf8) |
0222                               min_spacing_to_set);
0223 
0224                 *val = min_spacing_to_set;
0225 
0226                 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
0227                     "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
0228                     mac->min_space_cfg);
0229 
0230                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
0231                            mac->min_space_cfg);
0232             }
0233             break;
0234         }
0235     case HW_VAR_SHORTGI_DENSITY:{
0236             u8 density_to_set;
0237 
0238             density_to_set = *val;
0239             mac->min_space_cfg |= (density_to_set << 3);
0240 
0241             rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
0242                 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
0243                 mac->min_space_cfg);
0244 
0245             rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
0246                        mac->min_space_cfg);
0247 
0248             break;
0249         }
0250     case HW_VAR_AMPDU_FACTOR:{
0251             u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
0252             u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
0253 
0254             u8 factor_toset;
0255             u8 *p_regtoset = NULL;
0256             u8 index = 0;
0257 
0258             if ((rtlpriv->btcoexist.bt_coexistence) &&
0259                 (rtlpriv->btcoexist.bt_coexist_type ==
0260                 BT_CSR_BC4))
0261                 p_regtoset = regtoset_bt;
0262             else
0263                 p_regtoset = regtoset_normal;
0264 
0265             factor_toset = *(val);
0266             if (factor_toset <= 3) {
0267                 factor_toset = (1 << (factor_toset + 2));
0268                 if (factor_toset > 0xf)
0269                     factor_toset = 0xf;
0270 
0271                 for (index = 0; index < 4; index++) {
0272                     if ((p_regtoset[index] & 0xf0) >
0273                         (factor_toset << 4))
0274                         p_regtoset[index] =
0275                             (p_regtoset[index] & 0x0f) |
0276                             (factor_toset << 4);
0277 
0278                     if ((p_regtoset[index] & 0x0f) >
0279                         factor_toset)
0280                         p_regtoset[index] =
0281                             (p_regtoset[index] & 0xf0) |
0282                             (factor_toset);
0283 
0284                     rtl_write_byte(rtlpriv,
0285                                (REG_AGGLEN_LMT + index),
0286                                p_regtoset[index]);
0287 
0288                 }
0289 
0290                 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
0291                     "Set HW_VAR_AMPDU_FACTOR: %#x\n",
0292                     factor_toset);
0293             }
0294             break;
0295         }
0296     case HW_VAR_AC_PARAM:{
0297             u8 e_aci = *(val);
0298 
0299             rtl92c_dm_init_edca_turbo(hw);
0300 
0301             if (rtlpci->acm_method != EACMWAY2_SW)
0302                 rtlpriv->cfg->ops->set_hw_reg(hw,
0303                                   HW_VAR_ACM_CTRL,
0304                                   (&e_aci));
0305             break;
0306         }
0307     case HW_VAR_ACM_CTRL:{
0308             u8 e_aci = *(val);
0309             union aci_aifsn *p_aci_aifsn =
0310                 (union aci_aifsn *)(&(mac->ac[0].aifs));
0311             u8 acm = p_aci_aifsn->f.acm;
0312             u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
0313 
0314             acm_ctrl =
0315                 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
0316 
0317             if (acm) {
0318                 switch (e_aci) {
0319                 case AC0_BE:
0320                     acm_ctrl |= ACMHW_BEQEN;
0321                     break;
0322                 case AC2_VI:
0323                     acm_ctrl |= ACMHW_VIQEN;
0324                     break;
0325                 case AC3_VO:
0326                     acm_ctrl |= ACMHW_VOQEN;
0327                     break;
0328                 default:
0329                     rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
0330                         "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
0331                         acm);
0332                     break;
0333                 }
0334             } else {
0335                 switch (e_aci) {
0336                 case AC0_BE:
0337                     acm_ctrl &= (~ACMHW_BEQEN);
0338                     break;
0339                 case AC2_VI:
0340                     acm_ctrl &= (~ACMHW_VIQEN);
0341                     break;
0342                 case AC3_VO:
0343                     acm_ctrl &= (~ACMHW_VOQEN);
0344                     break;
0345                 default:
0346                     pr_err("switch case %#x not processed\n",
0347                            e_aci);
0348                     break;
0349                 }
0350             }
0351 
0352             rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
0353                 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
0354                 acm_ctrl);
0355             rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
0356             break;
0357         }
0358     case HW_VAR_RCR:{
0359             rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
0360             rtlpci->receive_config = ((u32 *) (val))[0];
0361             break;
0362         }
0363     case HW_VAR_RETRY_LIMIT:{
0364             u8 retry_limit = val[0];
0365 
0366             rtl_write_word(rtlpriv, REG_RL,
0367                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
0368                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
0369             break;
0370         }
0371     case HW_VAR_DUAL_TSF_RST:
0372         rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
0373         break;
0374     case HW_VAR_EFUSE_BYTES:
0375         rtlefuse->efuse_usedbytes = *((u16 *) val);
0376         break;
0377     case HW_VAR_EFUSE_USAGE:
0378         rtlefuse->efuse_usedpercentage = *val;
0379         break;
0380     case HW_VAR_IO_CMD:
0381         rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
0382         break;
0383     case HW_VAR_WPA_CONFIG:
0384         rtl_write_byte(rtlpriv, REG_SECCFG, *val);
0385         break;
0386     case HW_VAR_SET_RPWM:{
0387             u8 rpwm_val;
0388 
0389             rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
0390             udelay(1);
0391 
0392             if (rpwm_val & BIT(7)) {
0393                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
0394             } else {
0395                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
0396                            *val | BIT(7));
0397             }
0398 
0399             break;
0400         }
0401     case HW_VAR_H2C_FW_PWRMODE:{
0402             u8 psmode = *val;
0403 
0404             if ((psmode != FW_PS_ACTIVE_MODE) &&
0405                 (!IS_92C_SERIAL(rtlhal->version))) {
0406                 rtl92c_dm_rf_saving(hw, true);
0407             }
0408 
0409             rtl92c_set_fw_pwrmode_cmd(hw, *val);
0410             break;
0411         }
0412     case HW_VAR_FW_PSMODE_STATUS:
0413         ppsc->fw_current_inpsmode = *((bool *) val);
0414         break;
0415     case HW_VAR_H2C_FW_JOINBSSRPT:{
0416             u8 mstatus = *val;
0417             u8 tmp_regcr, tmp_reg422;
0418             bool recover = false;
0419 
0420             if (mstatus == RT_MEDIA_CONNECT) {
0421                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
0422                                   NULL);
0423 
0424                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
0425                 rtl_write_byte(rtlpriv, REG_CR + 1,
0426                            (tmp_regcr | BIT(0)));
0427 
0428                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
0429                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
0430 
0431                 tmp_reg422 =
0432                     rtl_read_byte(rtlpriv,
0433                           REG_FWHW_TXQ_CTRL + 2);
0434                 if (tmp_reg422 & BIT(6))
0435                     recover = true;
0436                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
0437                            tmp_reg422 & (~BIT(6)));
0438 
0439                 rtl92c_set_fw_rsvdpagepkt(hw, NULL);
0440 
0441                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
0442                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
0443 
0444                 if (recover) {
0445                     rtl_write_byte(rtlpriv,
0446                                REG_FWHW_TXQ_CTRL + 2,
0447                                tmp_reg422);
0448                 }
0449 
0450                 rtl_write_byte(rtlpriv, REG_CR + 1,
0451                            (tmp_regcr & ~(BIT(0))));
0452             }
0453             rtl92c_set_fw_joinbss_report_cmd(hw, *val);
0454 
0455             break;
0456         }
0457     case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
0458         rtl92c_set_p2p_ps_offload_cmd(hw, *val);
0459         break;
0460     case HW_VAR_AID:{
0461             u16 u2btmp;
0462 
0463             u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
0464             u2btmp &= 0xC000;
0465             rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
0466                         mac->assoc_id));
0467 
0468             break;
0469         }
0470     case HW_VAR_CORRECT_TSF:{
0471             u8 btype_ibss = val[0];
0472 
0473             if (btype_ibss)
0474                 _rtl92ce_stop_tx_beacon(hw);
0475 
0476             _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
0477 
0478             rtl_write_dword(rtlpriv, REG_TSFTR,
0479                     (u32) (mac->tsf & 0xffffffff));
0480             rtl_write_dword(rtlpriv, REG_TSFTR + 4,
0481                     (u32) ((mac->tsf >> 32) & 0xffffffff));
0482 
0483             _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
0484 
0485             if (btype_ibss)
0486                 _rtl92ce_resume_tx_beacon(hw);
0487 
0488             break;
0489 
0490         }
0491     case HW_VAR_FW_LPS_ACTION: {
0492             bool enter_fwlps = *((bool *)val);
0493             u8 rpwm_val, fw_pwrmode;
0494             bool fw_current_inps;
0495 
0496             if (enter_fwlps) {
0497                 rpwm_val = 0x02;    /* RF off */
0498                 fw_current_inps = true;
0499                 rtlpriv->cfg->ops->set_hw_reg(hw,
0500                         HW_VAR_FW_PSMODE_STATUS,
0501                         (u8 *)(&fw_current_inps));
0502                 rtlpriv->cfg->ops->set_hw_reg(hw,
0503                         HW_VAR_H2C_FW_PWRMODE,
0504                         &ppsc->fwctrl_psmode);
0505 
0506                 rtlpriv->cfg->ops->set_hw_reg(hw,
0507                                   HW_VAR_SET_RPWM,
0508                                   &rpwm_val);
0509             } else {
0510                 rpwm_val = 0x0C;    /* RF on */
0511                 fw_pwrmode = FW_PS_ACTIVE_MODE;
0512                 fw_current_inps = false;
0513                 rtlpriv->cfg->ops->set_hw_reg(hw,
0514                                   HW_VAR_SET_RPWM,
0515                                   &rpwm_val);
0516                 rtlpriv->cfg->ops->set_hw_reg(hw,
0517                         HW_VAR_H2C_FW_PWRMODE,
0518                         &fw_pwrmode);
0519 
0520                 rtlpriv->cfg->ops->set_hw_reg(hw,
0521                         HW_VAR_FW_PSMODE_STATUS,
0522                         (u8 *)(&fw_current_inps));
0523             }
0524         break; }
0525     case HW_VAR_KEEP_ALIVE: {
0526         u8 array[2];
0527 
0528         array[0] = 0xff;
0529         array[1] = *((u8 *)val);
0530         rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, array);
0531         break; }
0532     default:
0533         pr_err("switch case %d not processed\n", variable);
0534         break;
0535     }
0536 }
0537 
0538 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
0539 {
0540     struct rtl_priv *rtlpriv = rtl_priv(hw);
0541     bool status = true;
0542     long count = 0;
0543     u32 value = _LLT_INIT_ADDR(address) |
0544         _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
0545 
0546     rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
0547 
0548     do {
0549         value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
0550         if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
0551             break;
0552 
0553         if (count > POLLING_LLT_THRESHOLD) {
0554             pr_err("Failed to polling write LLT done at address %d!\n",
0555                    address);
0556             status = false;
0557             break;
0558         }
0559     } while (++count);
0560 
0561     return status;
0562 }
0563 
0564 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
0565 {
0566     struct rtl_priv *rtlpriv = rtl_priv(hw);
0567     unsigned short i;
0568     u8 txpktbuf_bndy;
0569     u8 maxpage;
0570     bool status;
0571 
0572 #if LLT_CONFIG == 1
0573     maxpage = 255;
0574     txpktbuf_bndy = 252;
0575 #elif LLT_CONFIG == 2
0576     maxpage = 127;
0577     txpktbuf_bndy = 124;
0578 #elif LLT_CONFIG == 3
0579     maxpage = 255;
0580     txpktbuf_bndy = 174;
0581 #elif LLT_CONFIG == 4
0582     maxpage = 255;
0583     txpktbuf_bndy = 246;
0584 #elif LLT_CONFIG == 5
0585     maxpage = 255;
0586     txpktbuf_bndy = 246;
0587 #endif
0588 
0589 #if LLT_CONFIG == 1
0590     rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
0591     rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
0592 #elif LLT_CONFIG == 2
0593     rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
0594 #elif LLT_CONFIG == 3
0595     rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
0596 #elif LLT_CONFIG == 4
0597     rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
0598 #elif LLT_CONFIG == 5
0599     rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
0600 
0601     rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
0602 #endif
0603 
0604     rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
0605     rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
0606 
0607     rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
0608     rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
0609 
0610     rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
0611     rtl_write_byte(rtlpriv, REG_PBP, 0x11);
0612     rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
0613 
0614     for (i = 0; i < (txpktbuf_bndy - 1); i++) {
0615         status = _rtl92ce_llt_write(hw, i, i + 1);
0616         if (!status)
0617             return status;
0618     }
0619 
0620     status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
0621     if (!status)
0622         return status;
0623 
0624     for (i = txpktbuf_bndy; i < maxpage; i++) {
0625         status = _rtl92ce_llt_write(hw, i, (i + 1));
0626         if (!status)
0627             return status;
0628     }
0629 
0630     status = _rtl92ce_llt_write(hw, maxpage, txpktbuf_bndy);
0631     if (!status)
0632         return status;
0633 
0634     return true;
0635 }
0636 
0637 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
0638 {
0639     struct rtl_priv *rtlpriv = rtl_priv(hw);
0640     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0641     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
0642     struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
0643 
0644     if (rtlpci->up_first_time)
0645         return;
0646 
0647     if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
0648         rtl92ce_sw_led_on(hw, pled0);
0649     else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
0650         rtl92ce_sw_led_on(hw, pled0);
0651     else
0652         rtl92ce_sw_led_off(hw, pled0);
0653 }
0654 
0655 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
0656 {
0657     struct rtl_priv *rtlpriv = rtl_priv(hw);
0658     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0659     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0660 
0661     unsigned char bytetmp;
0662     unsigned short wordtmp;
0663     u16 retry;
0664 
0665     rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
0666     if (rtlpriv->btcoexist.bt_coexistence) {
0667         u32 value32;
0668 
0669         value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
0670         value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
0671         rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
0672     }
0673     rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
0674     rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
0675 
0676     if (rtlpriv->btcoexist.bt_coexistence) {
0677         u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
0678 
0679         u4b_tmp &= (~0x00024800);
0680         rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
0681     }
0682 
0683     bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
0684     udelay(2);
0685 
0686     rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
0687     udelay(2);
0688 
0689     bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
0690     udelay(2);
0691 
0692     retry = 0;
0693     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
0694         rtl_read_dword(rtlpriv, 0xEC), bytetmp);
0695 
0696     while ((bytetmp & BIT(0)) && retry < 1000) {
0697         retry++;
0698         udelay(50);
0699         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
0700         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
0701             rtl_read_dword(rtlpriv, 0xEC), bytetmp);
0702         udelay(50);
0703     }
0704 
0705     rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
0706 
0707     rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
0708     udelay(2);
0709 
0710     if (rtlpriv->btcoexist.bt_coexistence) {
0711         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
0712         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
0713     }
0714 
0715     rtl_write_word(rtlpriv, REG_CR, 0x2ff);
0716 
0717     if (!_rtl92ce_llt_table_init(hw))
0718         return false;
0719 
0720     rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
0721     rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
0722 
0723     rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
0724 
0725     wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
0726     wordtmp &= 0xf;
0727     wordtmp |= 0xF771;
0728     rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
0729 
0730     rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
0731     rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
0732     rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
0733 
0734     rtl_write_byte(rtlpriv, 0x4d0, 0x0);
0735 
0736     rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
0737             ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
0738             DMA_BIT_MASK(32));
0739     rtl_write_dword(rtlpriv, REG_MGQ_DESA,
0740             (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
0741             DMA_BIT_MASK(32));
0742     rtl_write_dword(rtlpriv, REG_VOQ_DESA,
0743             (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
0744     rtl_write_dword(rtlpriv, REG_VIQ_DESA,
0745             (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
0746     rtl_write_dword(rtlpriv, REG_BEQ_DESA,
0747             (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
0748     rtl_write_dword(rtlpriv, REG_BKQ_DESA,
0749             (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
0750     rtl_write_dword(rtlpriv, REG_HQ_DESA,
0751             (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
0752             DMA_BIT_MASK(32));
0753     rtl_write_dword(rtlpriv, REG_RX_DESA,
0754             (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
0755             DMA_BIT_MASK(32));
0756 
0757     if (IS_92C_SERIAL(rtlhal->version))
0758         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
0759     else
0760         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
0761 
0762     rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
0763 
0764     bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
0765     rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
0766     do {
0767         retry++;
0768         bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
0769     } while ((retry < 200) && (bytetmp & BIT(7)));
0770 
0771     _rtl92ce_gen_refresh_led_state(hw);
0772 
0773     rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
0774 
0775     return true;
0776 }
0777 
0778 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
0779 {
0780     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0781     struct rtl_priv *rtlpriv = rtl_priv(hw);
0782     u8 reg_bw_opmode;
0783     u32 reg_prsr;
0784 
0785     reg_bw_opmode = BW_OPMODE_20MHZ;
0786     reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
0787 
0788     rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
0789 
0790     rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
0791 
0792     rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
0793 
0794     rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
0795 
0796     rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
0797 
0798     rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
0799 
0800     rtl_write_word(rtlpriv, REG_RL, 0x0707);
0801 
0802     rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
0803 
0804     rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
0805 
0806     rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
0807     rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
0808     rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
0809     rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
0810 
0811     if ((rtlpriv->btcoexist.bt_coexistence) &&
0812         (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
0813         rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
0814     else
0815         rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
0816 
0817     rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
0818 
0819     rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
0820 
0821     rtlpci->reg_bcn_ctrl_val = 0x1f;
0822     rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
0823 
0824     rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
0825 
0826     rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
0827 
0828     rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
0829     rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
0830 
0831     if ((rtlpriv->btcoexist.bt_coexistence) &&
0832         (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) {
0833         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
0834         rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
0835     } else {
0836         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
0837         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
0838     }
0839 
0840     if ((rtlpriv->btcoexist.bt_coexistence) &&
0841         (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
0842         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
0843     else
0844         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
0845 
0846     rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
0847 
0848     rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
0849     rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
0850 
0851     rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
0852 
0853     rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
0854 
0855     rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
0856     rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
0857 
0858 }
0859 
0860 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
0861 {
0862     struct rtl_priv *rtlpriv = rtl_priv(hw);
0863     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
0864 
0865     rtl_write_byte(rtlpriv, 0x34b, 0x93);
0866     rtl_write_word(rtlpriv, 0x350, 0x870c);
0867     rtl_write_byte(rtlpriv, 0x352, 0x1);
0868 
0869     if (ppsc->support_backdoor)
0870         rtl_write_byte(rtlpriv, 0x349, 0x1b);
0871     else
0872         rtl_write_byte(rtlpriv, 0x349, 0x03);
0873 
0874     rtl_write_word(rtlpriv, 0x350, 0x2718);
0875     rtl_write_byte(rtlpriv, 0x352, 0x1);
0876 }
0877 
0878 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
0879 {
0880     struct rtl_priv *rtlpriv = rtl_priv(hw);
0881     u8 sec_reg_value;
0882 
0883     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0884         "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
0885         rtlpriv->sec.pairwise_enc_algorithm,
0886         rtlpriv->sec.group_enc_algorithm);
0887 
0888     if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
0889         rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
0890             "not open hw encryption\n");
0891         return;
0892     }
0893 
0894     sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
0895 
0896     if (rtlpriv->sec.use_defaultkey) {
0897         sec_reg_value |= SCR_TXUSEDK;
0898         sec_reg_value |= SCR_RXUSEDK;
0899     }
0900 
0901     sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
0902 
0903     rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
0904 
0905     rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
0906         "The SECR-value %x\n", sec_reg_value);
0907 
0908     rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
0909 
0910 }
0911 
0912 int rtl92ce_hw_init(struct ieee80211_hw *hw)
0913 {
0914     struct rtl_priv *rtlpriv = rtl_priv(hw);
0915     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0916     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
0917     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0918     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0919     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
0920     bool rtstatus = true;
0921     bool is92c;
0922     int err;
0923     u8 tmp_u1b;
0924     unsigned long flags;
0925 
0926     rtlpci->being_init_adapter = true;
0927 
0928     /* Since this function can take a very long time (up to 350 ms)
0929      * and can be called with irqs disabled, reenable the irqs
0930      * to let the other devices continue being serviced.
0931      *
0932      * It is safe doing so since our own interrupts will only be enabled
0933      * in a subsequent step.
0934      */
0935     local_save_flags(flags);
0936     local_irq_enable();
0937 
0938     rtlhal->fw_ready = false;
0939     rtlpriv->intf_ops->disable_aspm(hw);
0940     rtstatus = _rtl92ce_init_mac(hw);
0941     if (!rtstatus) {
0942         pr_err("Init MAC failed\n");
0943         err = 1;
0944         goto exit;
0945     }
0946 
0947     err = rtl92c_download_fw(hw);
0948     if (err) {
0949         rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
0950             "Failed to download FW. Init HW without FW now..\n");
0951         err = 1;
0952         goto exit;
0953     }
0954 
0955     rtlhal->fw_ready = true;
0956     rtlhal->last_hmeboxnum = 0;
0957     rtl92c_phy_mac_config(hw);
0958     /* because last function modify RCR, so we update
0959      * rcr var here, or TP will unstable for receive_config
0960      * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
0961      * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
0962     rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
0963     rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
0964     rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
0965     rtl92c_phy_bb_config(hw);
0966     rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
0967     rtl92c_phy_rf_config(hw);
0968     if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
0969         !IS_92C_SERIAL(rtlhal->version)) {
0970         rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
0971         rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
0972     } else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
0973         rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
0974         rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
0975         rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
0976         rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
0977         rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
0978         rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
0979     }
0980     rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
0981                          RF_CHNLBW, RFREG_OFFSET_MASK);
0982     rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
0983                          RF_CHNLBW, RFREG_OFFSET_MASK);
0984     rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
0985     rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
0986     rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
0987     _rtl92ce_hw_configure(hw);
0988     rtl_cam_reset_all_entry(hw);
0989     rtl92ce_enable_hw_security_config(hw);
0990 
0991     ppsc->rfpwr_state = ERFON;
0992 
0993     rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
0994     _rtl92ce_enable_aspm_back_door(hw);
0995     rtlpriv->intf_ops->enable_aspm(hw);
0996 
0997     rtl8192ce_bt_hw_init(hw);
0998 
0999     if (ppsc->rfpwr_state == ERFON) {
1000         rtl92c_phy_set_rfpath_switch(hw, 1);
1001         if (rtlphy->iqk_initialized) {
1002             rtl92c_phy_iq_calibrate(hw, true);
1003         } else {
1004             rtl92c_phy_iq_calibrate(hw, false);
1005             rtlphy->iqk_initialized = true;
1006         }
1007 
1008         rtl92c_dm_check_txpower_tracking(hw);
1009         rtl92c_phy_lc_calibrate(hw);
1010     }
1011 
1012     is92c = IS_92C_SERIAL(rtlhal->version);
1013     tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1014     if (!(tmp_u1b & BIT(0))) {
1015         rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1016         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1017     }
1018 
1019     if (!(tmp_u1b & BIT(1)) && is92c) {
1020         rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1021         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n");
1022     }
1023 
1024     if (!(tmp_u1b & BIT(4))) {
1025         tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1026         tmp_u1b &= 0x0F;
1027         rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1028         udelay(10);
1029         rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1030         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1031     }
1032     rtl92c_dm_init(hw);
1033 exit:
1034     local_irq_restore(flags);
1035     rtlpci->being_init_adapter = false;
1036     return err;
1037 }
1038 
1039 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1040 {
1041     struct rtl_priv *rtlpriv = rtl_priv(hw);
1042     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1043     enum version_8192c version = VERSION_UNKNOWN;
1044     u32 value32;
1045     const char *versionid;
1046 
1047     value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1048     if (value32 & TRP_VAUX_EN) {
1049         version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1050                VERSION_A_CHIP_88C;
1051     } else {
1052         version = (enum version_8192c) (CHIP_VER_B |
1053                 ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) |
1054                 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1055         if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 &
1056              CHIP_VER_RTL_MASK)) {
1057             version = (enum version_8192c)(version |
1058                    ((((value32 & CHIP_VER_RTL_MASK) == BIT(12))
1059                    ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) |
1060                    CHIP_VENDOR_UMC));
1061         }
1062         if (IS_92C_SERIAL(version)) {
1063             value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
1064             version = (enum version_8192c)(version |
1065                    ((CHIP_BONDING_IDENTIFIER(value32)
1066                    == CHIP_BONDING_92C_1T2R) ?
1067                    RF_TYPE_1T2R : 0));
1068         }
1069     }
1070 
1071     switch (version) {
1072     case VERSION_B_CHIP_92C:
1073         versionid = "B_CHIP_92C";
1074         break;
1075     case VERSION_B_CHIP_88C:
1076         versionid = "B_CHIP_88C";
1077         break;
1078     case VERSION_A_CHIP_92C:
1079         versionid = "A_CHIP_92C";
1080         break;
1081     case VERSION_A_CHIP_88C:
1082         versionid = "A_CHIP_88C";
1083         break;
1084     case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
1085         versionid = "A_CUT_92C_1T2R";
1086         break;
1087     case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
1088         versionid = "A_CUT_92C";
1089         break;
1090     case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
1091         versionid = "A_CUT_88C";
1092         break;
1093     case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
1094         versionid = "B_CUT_92C_1T2R";
1095         break;
1096     case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
1097         versionid = "B_CUT_92C";
1098         break;
1099     case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
1100         versionid = "B_CUT_88C";
1101         break;
1102     default:
1103         versionid = "Unknown. Bug?";
1104         break;
1105     }
1106 
1107     pr_info("Chip Version ID: %s\n", versionid);
1108 
1109     switch (version & 0x3) {
1110     case CHIP_88C:
1111         rtlphy->rf_type = RF_1T1R;
1112         break;
1113     case CHIP_92C:
1114         rtlphy->rf_type = RF_2T2R;
1115         break;
1116     case CHIP_92C_1T2R:
1117         rtlphy->rf_type = RF_1T2R;
1118         break;
1119     default:
1120         rtlphy->rf_type = RF_1T1R;
1121         pr_err("ERROR RF_Type is set!!\n");
1122         break;
1123     }
1124 
1125     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1126         rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1127 
1128     return version;
1129 }
1130 
1131 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1132                      enum nl80211_iftype type)
1133 {
1134     struct rtl_priv *rtlpriv = rtl_priv(hw);
1135     u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1136     enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1137     u8 mode = MSR_NOLINK;
1138 
1139     bt_msr &= 0xfc;
1140 
1141     switch (type) {
1142     case NL80211_IFTYPE_UNSPECIFIED:
1143         mode = MSR_NOLINK;
1144         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1145             "Set Network type to NO LINK!\n");
1146         break;
1147     case NL80211_IFTYPE_ADHOC:
1148         mode = MSR_ADHOC;
1149         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1150             "Set Network type to Ad Hoc!\n");
1151         break;
1152     case NL80211_IFTYPE_STATION:
1153         mode = MSR_INFRA;
1154         ledaction = LED_CTL_LINK;
1155         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1156             "Set Network type to STA!\n");
1157         break;
1158     case NL80211_IFTYPE_AP:
1159         mode = MSR_AP;
1160         ledaction = LED_CTL_LINK;
1161         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1162             "Set Network type to AP!\n");
1163         break;
1164     case NL80211_IFTYPE_MESH_POINT:
1165         mode = MSR_ADHOC;
1166         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1167             "Set Network type to Mesh Point!\n");
1168         break;
1169     default:
1170         pr_err("Network type %d not supported!\n", type);
1171         return 1;
1172 
1173     }
1174 
1175     /* MSR_INFRA == Link in infrastructure network;
1176      * MSR_ADHOC == Link in ad hoc network;
1177      * Therefore, check link state is necessary.
1178      *
1179      * MSR_AP == AP mode; link state does not matter here.
1180      */
1181     if (mode != MSR_AP &&
1182         rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1183         mode = MSR_NOLINK;
1184         ledaction = LED_CTL_NO_LINK;
1185     }
1186     if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1187         _rtl92ce_stop_tx_beacon(hw);
1188         _rtl92ce_enable_bcn_sub_func(hw);
1189     } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1190         _rtl92ce_resume_tx_beacon(hw);
1191         _rtl92ce_disable_bcn_sub_func(hw);
1192     } else {
1193         rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1194             "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1195             mode);
1196     }
1197     rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1198 
1199     rtlpriv->cfg->ops->led_control(hw, ledaction);
1200     if (mode == MSR_AP)
1201         rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1202     else
1203         rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1204     return 0;
1205 }
1206 
1207 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1208 {
1209     struct rtl_priv *rtlpriv = rtl_priv(hw);
1210     u32 reg_rcr;
1211 
1212     if (rtlpriv->psc.rfpwr_state != ERFON)
1213         return;
1214 
1215     rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1216 
1217     if (check_bssid) {
1218         reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1219         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1220                           (u8 *) (&reg_rcr));
1221         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1222     } else if (!check_bssid) {
1223         reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1224         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1225         rtlpriv->cfg->ops->set_hw_reg(hw,
1226                           HW_VAR_RCR, (u8 *) (&reg_rcr));
1227     }
1228 
1229 }
1230 
1231 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1232 {
1233     struct rtl_priv *rtlpriv = rtl_priv(hw);
1234 
1235     if (_rtl92ce_set_media_status(hw, type))
1236         return -EOPNOTSUPP;
1237 
1238     if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1239         if (type != NL80211_IFTYPE_AP &&
1240             type != NL80211_IFTYPE_MESH_POINT)
1241             rtl92ce_set_check_bssid(hw, true);
1242     } else {
1243         rtl92ce_set_check_bssid(hw, false);
1244     }
1245 
1246     return 0;
1247 }
1248 
1249 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1250 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1251 {
1252     struct rtl_priv *rtlpriv = rtl_priv(hw);
1253 
1254     rtl92c_dm_init_edca_turbo(hw);
1255     switch (aci) {
1256     case AC1_BK:
1257         rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1258         break;
1259     case AC0_BE:
1260         /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1261         break;
1262     case AC2_VI:
1263         rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1264         break;
1265     case AC3_VO:
1266         rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1267         break;
1268     default:
1269         WARN_ONCE(true, "rtl8192ce: invalid aci: %d !\n", aci);
1270         break;
1271     }
1272 }
1273 
1274 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1275 {
1276     struct rtl_priv *rtlpriv = rtl_priv(hw);
1277     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1278 
1279     rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1280     rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1281     rtlpci->irq_enabled = true;
1282 }
1283 
1284 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1285 {
1286     struct rtl_priv *rtlpriv = rtl_priv(hw);
1287     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1288 
1289     rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1290     rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1291     rtlpci->irq_enabled = false;
1292 }
1293 
1294 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1295 {
1296     struct rtl_priv *rtlpriv = rtl_priv(hw);
1297     struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1298     u8 u1b_tmp;
1299     u32 u4b_tmp;
1300 
1301     rtlpriv->intf_ops->enable_aspm(hw);
1302     rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1303     rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1304     rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1305     rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1306     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1307     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1308     if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7))
1309         rtl92c_firmware_selfreset(hw);
1310     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1311     rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1312     rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1313     u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1314     if ((rtlpriv->btcoexist.bt_coexistence) &&
1315         ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
1316          (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8))) {
1317         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1318                 (u1b_tmp << 8));
1319     } else {
1320         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1321                 (u1b_tmp << 8));
1322     }
1323     rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1324     rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1325     rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1326     if (!IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))
1327         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1328     if (rtlpriv->btcoexist.bt_coexistence) {
1329         u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1330         u4b_tmp |= 0x03824800;
1331         rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1332     } else {
1333         rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1334     }
1335 
1336     rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1337     rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1338 }
1339 
1340 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1341 {
1342     struct rtl_priv *rtlpriv = rtl_priv(hw);
1343     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1344     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1345     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1346     enum nl80211_iftype opmode;
1347 
1348     mac->link_state = MAC80211_NOLINK;
1349     opmode = NL80211_IFTYPE_UNSPECIFIED;
1350     _rtl92ce_set_media_status(hw, opmode);
1351     if (rtlpci->driver_is_goingto_unload ||
1352         ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1353         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1354     RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1355     _rtl92ce_poweroff_adapter(hw);
1356 
1357     /* after power off we should do iqk again */
1358     rtlpriv->phy.iqk_initialized = false;
1359 }
1360 
1361 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1362                   struct rtl_int *intvec)
1363 {
1364     struct rtl_priv *rtlpriv = rtl_priv(hw);
1365     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1366 
1367     intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1368     rtl_write_dword(rtlpriv, ISR, intvec->inta);
1369 }
1370 
1371 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1372 {
1373 
1374     struct rtl_priv *rtlpriv = rtl_priv(hw);
1375     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1376     u16 bcn_interval, atim_window;
1377 
1378     bcn_interval = mac->beacon_interval;
1379     atim_window = 2;    /*FIX MERGE */
1380     rtl92ce_disable_interrupt(hw);
1381     rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1382     rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1383     rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1384     rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1385     rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1386     rtl_write_byte(rtlpriv, 0x606, 0x30);
1387     rtl92ce_enable_interrupt(hw);
1388 }
1389 
1390 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1391 {
1392     struct rtl_priv *rtlpriv = rtl_priv(hw);
1393     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1394     u16 bcn_interval = mac->beacon_interval;
1395 
1396     rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1397         "beacon_interval:%d\n", bcn_interval);
1398     rtl92ce_disable_interrupt(hw);
1399     rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1400     rtl92ce_enable_interrupt(hw);
1401 }
1402 
1403 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1404                    u32 add_msr, u32 rm_msr)
1405 {
1406     struct rtl_priv *rtlpriv = rtl_priv(hw);
1407     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1408 
1409     rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1410         add_msr, rm_msr);
1411 
1412     if (add_msr)
1413         rtlpci->irq_mask[0] |= add_msr;
1414     if (rm_msr)
1415         rtlpci->irq_mask[0] &= (~rm_msr);
1416     rtl92ce_disable_interrupt(hw);
1417     rtl92ce_enable_interrupt(hw);
1418 }
1419 
1420 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1421                          bool autoload_fail,
1422                          u8 *hwinfo)
1423 {
1424     struct rtl_priv *rtlpriv = rtl_priv(hw);
1425     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1426     u8 rf_path, index, tempval;
1427     u16 i;
1428 
1429     for (rf_path = 0; rf_path < 2; rf_path++) {
1430         for (i = 0; i < 3; i++) {
1431             if (!autoload_fail) {
1432                 rtlefuse->
1433                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1434                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1435                 rtlefuse->
1436                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1437                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1438                        i];
1439             } else {
1440                 rtlefuse->
1441                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1442                     EEPROM_DEFAULT_TXPOWERLEVEL;
1443                 rtlefuse->
1444                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1445                     EEPROM_DEFAULT_TXPOWERLEVEL;
1446             }
1447         }
1448     }
1449 
1450     for (i = 0; i < 3; i++) {
1451         if (!autoload_fail)
1452             tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1453         else
1454             tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1455         rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1456             (tempval & 0xf);
1457         rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1458             ((tempval & 0xf0) >> 4);
1459     }
1460 
1461     for (rf_path = 0; rf_path < 2; rf_path++)
1462         for (i = 0; i < 3; i++)
1463             RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1464                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1465                 rf_path, i,
1466                 rtlefuse->
1467                 eeprom_chnlarea_txpwr_cck[rf_path][i]);
1468     for (rf_path = 0; rf_path < 2; rf_path++)
1469         for (i = 0; i < 3; i++)
1470             RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1471                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1472                 rf_path, i,
1473                 rtlefuse->
1474                 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1475     for (rf_path = 0; rf_path < 2; rf_path++)
1476         for (i = 0; i < 3; i++)
1477             RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1478                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1479                 rf_path, i,
1480                 rtlefuse->
1481                 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
1482 
1483     for (rf_path = 0; rf_path < 2; rf_path++) {
1484         for (i = 0; i < 14; i++) {
1485             index = rtl92c_get_chnl_group((u8)i);
1486 
1487             rtlefuse->txpwrlevel_cck[rf_path][i] =
1488                 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1489             rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1490                 rtlefuse->
1491                 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1492 
1493             if ((rtlefuse->
1494                  eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1495                  rtlefuse->
1496                  eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
1497                 > 0) {
1498                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1499                     rtlefuse->
1500                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1501                     [index] -
1502                     rtlefuse->
1503                     eprom_chnl_txpwr_ht40_2sdf[rf_path]
1504                     [index];
1505             } else {
1506                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1507             }
1508         }
1509 
1510         for (i = 0; i < 14; i++) {
1511             RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1512                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1513                 rf_path, i,
1514                 rtlefuse->txpwrlevel_cck[rf_path][i],
1515                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1516                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1517         }
1518     }
1519 
1520     for (i = 0; i < 3; i++) {
1521         if (!autoload_fail) {
1522             rtlefuse->eeprom_pwrlimit_ht40[i] =
1523                 hwinfo[EEPROM_TXPWR_GROUP + i];
1524             rtlefuse->eeprom_pwrlimit_ht20[i] =
1525                 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1526         } else {
1527             rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1528             rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1529         }
1530     }
1531 
1532     for (rf_path = 0; rf_path < 2; rf_path++) {
1533         for (i = 0; i < 14; i++) {
1534             index = rtl92c_get_chnl_group((u8)i);
1535 
1536             if (rf_path == RF90_PATH_A) {
1537                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1538                     (rtlefuse->eeprom_pwrlimit_ht20[index]
1539                      & 0xf);
1540                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1541                     (rtlefuse->eeprom_pwrlimit_ht40[index]
1542                      & 0xf);
1543             } else if (rf_path == RF90_PATH_B) {
1544                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1545                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
1546                       & 0xf0) >> 4);
1547                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1548                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
1549                       & 0xf0) >> 4);
1550             }
1551 
1552             RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1553                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1554                 rf_path, i,
1555                 rtlefuse->pwrgroup_ht20[rf_path][i]);
1556             RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1557                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1558                 rf_path, i,
1559                 rtlefuse->pwrgroup_ht40[rf_path][i]);
1560         }
1561     }
1562 
1563     for (i = 0; i < 14; i++) {
1564         index = rtl92c_get_chnl_group((u8)i);
1565 
1566         if (!autoload_fail)
1567             tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1568         else
1569             tempval = EEPROM_DEFAULT_HT20_DIFF;
1570 
1571         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1572         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1573             ((tempval >> 4) & 0xF);
1574 
1575         if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1576             rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1577 
1578         if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1579             rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1580 
1581         index = rtl92c_get_chnl_group((u8)i);
1582 
1583         if (!autoload_fail)
1584             tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1585         else
1586             tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1587 
1588         rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1589         rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1590             ((tempval >> 4) & 0xF);
1591     }
1592 
1593     rtlefuse->legacy_ht_txpowerdiff =
1594         rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1595 
1596     for (i = 0; i < 14; i++)
1597         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1598             "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1599             i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1600     for (i = 0; i < 14; i++)
1601         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1602             "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1603             i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1604     for (i = 0; i < 14; i++)
1605         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1606             "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1607             i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1608     for (i = 0; i < 14; i++)
1609         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1610             "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1611             i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1612 
1613     if (!autoload_fail)
1614         rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1615     else
1616         rtlefuse->eeprom_regulatory = 0;
1617     RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1618         "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1619 
1620     if (!autoload_fail) {
1621         rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1622         rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1623     } else {
1624         rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1625         rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1626     }
1627     RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1628         rtlefuse->eeprom_tssi[RF90_PATH_A],
1629         rtlefuse->eeprom_tssi[RF90_PATH_B]);
1630 
1631     if (!autoload_fail)
1632         tempval = hwinfo[EEPROM_THERMAL_METER];
1633     else
1634         tempval = EEPROM_DEFAULT_THERMALMETER;
1635     rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1636 
1637     if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1638         rtlefuse->apk_thermalmeterignore = true;
1639 
1640     rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1641     RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1642         "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1643 }
1644 
1645 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1646 {
1647     struct rtl_priv *rtlpriv = rtl_priv(hw);
1648     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1649     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1650     int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1651             EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1652             EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1653             COUNTRY_CODE_WORLD_WIDE_13};
1654     u8 *hwinfo;
1655 
1656     hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1657     if (!hwinfo)
1658         return;
1659 
1660     if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1661         goto exit;
1662 
1663     _rtl92ce_read_txpower_info_from_hwpg(hw,
1664                          rtlefuse->autoload_failflag,
1665                          hwinfo);
1666 
1667     rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1668                          rtlefuse->autoload_failflag,
1669                          hwinfo);
1670     if (rtlhal->oem_id == RT_CID_DEFAULT) {
1671         switch (rtlefuse->eeprom_oemid) {
1672         case EEPROM_CID_DEFAULT:
1673             if (rtlefuse->eeprom_did == 0x8176) {
1674                 if ((rtlefuse->eeprom_svid == 0x103C &&
1675                      rtlefuse->eeprom_smid == 0x1629))
1676                     rtlhal->oem_id = RT_CID_819X_HP;
1677                 else
1678                     rtlhal->oem_id = RT_CID_DEFAULT;
1679             } else {
1680                 rtlhal->oem_id = RT_CID_DEFAULT;
1681             }
1682             break;
1683         case EEPROM_CID_TOSHIBA:
1684             rtlhal->oem_id = RT_CID_TOSHIBA;
1685             break;
1686         case EEPROM_CID_QMI:
1687             rtlhal->oem_id = RT_CID_819X_QMI;
1688             break;
1689         case EEPROM_CID_WHQL:
1690         default:
1691             rtlhal->oem_id = RT_CID_DEFAULT;
1692             break;
1693         }
1694     }
1695 exit:
1696     kfree(hwinfo);
1697 }
1698 
1699 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1700 {
1701     struct rtl_priv *rtlpriv = rtl_priv(hw);
1702     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1703 
1704     switch (rtlhal->oem_id) {
1705     case RT_CID_819X_HP:
1706         rtlpriv->ledctl.led_opendrain = true;
1707         break;
1708     case RT_CID_819X_LENOVO:
1709     case RT_CID_DEFAULT:
1710     case RT_CID_TOSHIBA:
1711     case RT_CID_CCX:
1712     case RT_CID_819X_ACER:
1713     case RT_CID_WHQL:
1714     default:
1715         break;
1716     }
1717     rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1718         "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1719 }
1720 
1721 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1722 {
1723     struct rtl_priv *rtlpriv = rtl_priv(hw);
1724     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1725     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1726     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1727     u8 tmp_u1b;
1728 
1729     rtlhal->version = _rtl92ce_read_chip_version(hw);
1730     if (get_rf_type(rtlphy) == RF_1T1R)
1731         rtlpriv->dm.rfpath_rxenable[0] = true;
1732     else
1733         rtlpriv->dm.rfpath_rxenable[0] =
1734             rtlpriv->dm.rfpath_rxenable[1] = true;
1735     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1736         rtlhal->version);
1737     tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1738     if (tmp_u1b & BIT(4)) {
1739         rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1740         rtlefuse->epromtype = EEPROM_93C46;
1741     } else {
1742         rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1743         rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1744     }
1745     if (tmp_u1b & BIT(5)) {
1746         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1747         rtlefuse->autoload_failflag = false;
1748         _rtl92ce_read_adapter_info(hw);
1749     } else {
1750         pr_err("Autoload ERR!!\n");
1751     }
1752     _rtl92ce_hal_customized_behavior(hw);
1753 }
1754 
1755 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1756         struct ieee80211_sta *sta)
1757 {
1758     struct rtl_priv *rtlpriv = rtl_priv(hw);
1759     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1760     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1761     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1762     u32 ratr_value;
1763     u8 ratr_index = 0;
1764     u8 nmode = mac->ht_enable;
1765     u16 shortgi_rate;
1766     u32 tmp_ratr_value;
1767     u8 curtxbw_40mhz = mac->bw_40;
1768     u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1769                    1 : 0;
1770     u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1771                    1 : 0;
1772     enum wireless_mode wirelessmode = mac->mode;
1773     u32 ratr_mask;
1774 
1775     if (rtlhal->current_bandtype == BAND_ON_5G)
1776         ratr_value = sta->deflink.supp_rates[1] << 4;
1777     else
1778         ratr_value = sta->deflink.supp_rates[0];
1779     if (mac->opmode == NL80211_IFTYPE_ADHOC)
1780         ratr_value = 0xfff;
1781 
1782     ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1783             sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1784     switch (wirelessmode) {
1785     case WIRELESS_MODE_B:
1786         if (ratr_value & 0x0000000c)
1787             ratr_value &= 0x0000000d;
1788         else
1789             ratr_value &= 0x0000000f;
1790         break;
1791     case WIRELESS_MODE_G:
1792         ratr_value &= 0x00000FF5;
1793         break;
1794     case WIRELESS_MODE_N_24G:
1795     case WIRELESS_MODE_N_5G:
1796         nmode = 1;
1797         if (get_rf_type(rtlphy) == RF_1T2R ||
1798             get_rf_type(rtlphy) == RF_1T1R)
1799             ratr_mask = 0x000ff005;
1800         else
1801             ratr_mask = 0x0f0ff005;
1802 
1803         ratr_value &= ratr_mask;
1804         break;
1805     default:
1806         if (rtlphy->rf_type == RF_1T2R)
1807             ratr_value &= 0x000ff0ff;
1808         else
1809             ratr_value &= 0x0f0ff0ff;
1810 
1811         break;
1812     }
1813 
1814     if ((rtlpriv->btcoexist.bt_coexistence) &&
1815         (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
1816         (rtlpriv->btcoexist.bt_cur_state) &&
1817         (rtlpriv->btcoexist.bt_ant_isolation) &&
1818         ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
1819         (rtlpriv->btcoexist.bt_service == BT_BUSY)))
1820         ratr_value &= 0x0fffcfc0;
1821     else
1822         ratr_value &= 0x0FFFFFFF;
1823 
1824     if (nmode && ((curtxbw_40mhz &&
1825              curshortgi_40mhz) || (!curtxbw_40mhz &&
1826                            curshortgi_20mhz))) {
1827 
1828         ratr_value |= 0x10000000;
1829         tmp_ratr_value = (ratr_value >> 12);
1830 
1831         for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1832             if ((1 << shortgi_rate) & tmp_ratr_value)
1833                 break;
1834         }
1835 
1836         shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1837             (shortgi_rate << 4) | (shortgi_rate);
1838     }
1839 
1840     rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1841 
1842     rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1843         rtl_read_dword(rtlpriv, REG_ARFR0));
1844 }
1845 
1846 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1847         struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
1848 {
1849     struct rtl_priv *rtlpriv = rtl_priv(hw);
1850     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1851     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1852     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1853     struct rtl_sta_info *sta_entry = NULL;
1854     u32 ratr_bitmap;
1855     u8 ratr_index;
1856     u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap &
1857                 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
1858     u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap &
1859                    IEEE80211_HT_CAP_SGI_40) ?  1 : 0;
1860     u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1861                 1 : 0;
1862     enum wireless_mode wirelessmode = 0;
1863     bool shortgi = false;
1864     u8 rate_mask[5];
1865     u8 macid = 0;
1866 
1867     sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1868     wirelessmode = sta_entry->wireless_mode;
1869     if (mac->opmode == NL80211_IFTYPE_STATION ||
1870         mac->opmode == NL80211_IFTYPE_MESH_POINT)
1871         curtxbw_40mhz = mac->bw_40;
1872     else if (mac->opmode == NL80211_IFTYPE_AP ||
1873         mac->opmode == NL80211_IFTYPE_ADHOC)
1874         macid = sta->aid + 1;
1875 
1876     if (rtlhal->current_bandtype == BAND_ON_5G)
1877         ratr_bitmap = sta->deflink.supp_rates[1] << 4;
1878     else
1879         ratr_bitmap = sta->deflink.supp_rates[0];
1880     if (mac->opmode == NL80211_IFTYPE_ADHOC)
1881         ratr_bitmap = 0xfff;
1882     ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1883             sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1884     switch (wirelessmode) {
1885     case WIRELESS_MODE_B:
1886         ratr_index = RATR_INX_WIRELESS_B;
1887         if (ratr_bitmap & 0x0000000c)
1888             ratr_bitmap &= 0x0000000d;
1889         else
1890             ratr_bitmap &= 0x0000000f;
1891         break;
1892     case WIRELESS_MODE_G:
1893         ratr_index = RATR_INX_WIRELESS_GB;
1894 
1895         if (rssi_level == 1)
1896             ratr_bitmap &= 0x00000f00;
1897         else if (rssi_level == 2)
1898             ratr_bitmap &= 0x00000ff0;
1899         else
1900             ratr_bitmap &= 0x00000ff5;
1901         break;
1902     case WIRELESS_MODE_A:
1903         ratr_index = RATR_INX_WIRELESS_A;
1904         ratr_bitmap &= 0x00000ff0;
1905         break;
1906     case WIRELESS_MODE_N_24G:
1907     case WIRELESS_MODE_N_5G:
1908         ratr_index = RATR_INX_WIRELESS_NGB;
1909 
1910         if (rtlphy->rf_type == RF_1T2R ||
1911             rtlphy->rf_type == RF_1T1R) {
1912             if (curtxbw_40mhz) {
1913                 if (rssi_level == 1)
1914                     ratr_bitmap &= 0x000f0000;
1915                 else if (rssi_level == 2)
1916                     ratr_bitmap &= 0x000ff000;
1917                 else
1918                     ratr_bitmap &= 0x000ff015;
1919             } else {
1920                 if (rssi_level == 1)
1921                     ratr_bitmap &= 0x000f0000;
1922                 else if (rssi_level == 2)
1923                     ratr_bitmap &= 0x000ff000;
1924                 else
1925                     ratr_bitmap &= 0x000ff005;
1926             }
1927         } else {
1928             if (curtxbw_40mhz) {
1929                 if (rssi_level == 1)
1930                     ratr_bitmap &= 0x0f0f0000;
1931                 else if (rssi_level == 2)
1932                     ratr_bitmap &= 0x0f0ff000;
1933                 else
1934                     ratr_bitmap &= 0x0f0ff015;
1935             } else {
1936                 if (rssi_level == 1)
1937                     ratr_bitmap &= 0x0f0f0000;
1938                 else if (rssi_level == 2)
1939                     ratr_bitmap &= 0x0f0ff000;
1940                 else
1941                     ratr_bitmap &= 0x0f0ff005;
1942             }
1943         }
1944 
1945         if ((curtxbw_40mhz && curshortgi_40mhz) ||
1946             (!curtxbw_40mhz && curshortgi_20mhz)) {
1947 
1948             if (macid == 0)
1949                 shortgi = true;
1950             else if (macid == 1)
1951                 shortgi = false;
1952         }
1953         break;
1954     default:
1955         ratr_index = RATR_INX_WIRELESS_NGB;
1956 
1957         if (rtlphy->rf_type == RF_1T2R)
1958             ratr_bitmap &= 0x000ff0ff;
1959         else
1960             ratr_bitmap &= 0x0f0ff0ff;
1961         break;
1962     }
1963     sta_entry->ratr_index = ratr_index;
1964 
1965     rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
1966         "ratr_bitmap :%x\n", ratr_bitmap);
1967     *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
1968                      (ratr_index << 28);
1969     rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1970     rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
1971         "Rate_index:%x, ratr_val:%x, %5phC\n",
1972         ratr_index, ratr_bitmap, rate_mask);
1973     rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1974 }
1975 
1976 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1977         struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
1978 {
1979     struct rtl_priv *rtlpriv = rtl_priv(hw);
1980 
1981     if (rtlpriv->dm.useramask)
1982         rtl92ce_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
1983     else
1984         rtl92ce_update_hal_rate_table(hw, sta);
1985 }
1986 
1987 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1988 {
1989     struct rtl_priv *rtlpriv = rtl_priv(hw);
1990     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1991     u16 sifs_timer;
1992 
1993     rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1994                       &mac->slot_time);
1995     if (!mac->ht_enable)
1996         sifs_timer = 0x0a0a;
1997     else
1998         sifs_timer = 0x1010;
1999     rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2000 }
2001 
2002 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2003 {
2004     struct rtl_priv *rtlpriv = rtl_priv(hw);
2005     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2006     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2007     enum rf_pwrstate e_rfpowerstate_toset;
2008     u8 u1tmp;
2009     bool actuallyset = false;
2010     unsigned long flag;
2011 
2012     if (rtlpci->being_init_adapter)
2013         return false;
2014 
2015     if (ppsc->swrf_processing)
2016         return false;
2017 
2018     spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2019     if (ppsc->rfchange_inprogress) {
2020         spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2021         return false;
2022     } else {
2023         ppsc->rfchange_inprogress = true;
2024         spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2025     }
2026 
2027     rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2028                REG_MAC_PINMUX_CFG)&~(BIT(3)));
2029 
2030     u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2031     e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2032 
2033     if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2034         rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2035             "GPIOChangeRF  - HW Radio ON, RF ON\n");
2036 
2037         e_rfpowerstate_toset = ERFON;
2038         ppsc->hwradiooff = false;
2039         actuallyset = true;
2040     } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2041         rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2042             "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2043 
2044         e_rfpowerstate_toset = ERFOFF;
2045         ppsc->hwradiooff = true;
2046         actuallyset = true;
2047     }
2048 
2049     if (actuallyset) {
2050         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2051         ppsc->rfchange_inprogress = false;
2052         spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2053     } else {
2054         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2055             RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2056 
2057         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2058         ppsc->rfchange_inprogress = false;
2059         spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2060     }
2061 
2062     *valid = 1;
2063     return !ppsc->hwradiooff;
2064 
2065 }
2066 
2067 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2068              u8 *p_macaddr, bool is_group, u8 enc_algo,
2069              bool is_wepkey, bool clear_all)
2070 {
2071     struct rtl_priv *rtlpriv = rtl_priv(hw);
2072     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2073     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2074     u8 *macaddr = p_macaddr;
2075     u32 entry_id = 0;
2076     bool is_pairwise = false;
2077 
2078     static u8 cam_const_addr[4][6] = {
2079         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2080         {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2081         {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2082         {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2083     };
2084     static u8 cam_const_broad[] = {
2085         0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2086     };
2087 
2088     if (clear_all) {
2089         u8 idx = 0;
2090         u8 cam_offset = 0;
2091         u8 clear_number = 5;
2092 
2093         rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2094 
2095         for (idx = 0; idx < clear_number; idx++) {
2096             rtl_cam_mark_invalid(hw, cam_offset + idx);
2097             rtl_cam_empty_entry(hw, cam_offset + idx);
2098 
2099             if (idx < 5) {
2100                 memset(rtlpriv->sec.key_buf[idx], 0,
2101                        MAX_KEY_LEN);
2102                 rtlpriv->sec.key_len[idx] = 0;
2103             }
2104         }
2105 
2106     } else {
2107         switch (enc_algo) {
2108         case WEP40_ENCRYPTION:
2109             enc_algo = CAM_WEP40;
2110             break;
2111         case WEP104_ENCRYPTION:
2112             enc_algo = CAM_WEP104;
2113             break;
2114         case TKIP_ENCRYPTION:
2115             enc_algo = CAM_TKIP;
2116             break;
2117         case AESCCMP_ENCRYPTION:
2118             enc_algo = CAM_AES;
2119             break;
2120         default:
2121             pr_err("switch case %#x not processed\n",
2122                    enc_algo);
2123             enc_algo = CAM_TKIP;
2124             break;
2125         }
2126 
2127         if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2128             macaddr = cam_const_addr[key_index];
2129             entry_id = key_index;
2130         } else {
2131             if (is_group) {
2132                 macaddr = cam_const_broad;
2133                 entry_id = key_index;
2134             } else {
2135                 if (mac->opmode == NL80211_IFTYPE_AP ||
2136                     mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2137                     entry_id = rtl_cam_get_free_entry(hw,
2138                                  p_macaddr);
2139                     if (entry_id >=  TOTAL_CAM_ENTRY) {
2140                         pr_err("Can not find free hw security cam entry\n");
2141                         return;
2142                     }
2143                 } else {
2144                     entry_id = CAM_PAIRWISE_KEY_POSITION;
2145                 }
2146 
2147                 key_index = PAIRWISE_KEYIDX;
2148                 is_pairwise = true;
2149             }
2150         }
2151 
2152         if (rtlpriv->sec.key_len[key_index] == 0) {
2153             rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2154                 "delete one entry, entry_id is %d\n",
2155                  entry_id);
2156             if (mac->opmode == NL80211_IFTYPE_AP ||
2157                 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2158                 rtl_cam_del_entry(hw, p_macaddr);
2159             rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2160         } else {
2161             rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
2162                 "The insert KEY length is %d\n",
2163                 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2164             rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
2165                 "The insert KEY is %x %x\n",
2166                 rtlpriv->sec.key_buf[0][0],
2167                 rtlpriv->sec.key_buf[0][1]);
2168 
2169             rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2170                 "add one entry\n");
2171             if (is_pairwise) {
2172                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2173                           "Pairwise Key content",
2174                           rtlpriv->sec.pairwise_key,
2175                           rtlpriv->sec.
2176                           key_len[PAIRWISE_KEYIDX]);
2177 
2178                 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2179                     "set Pairwise key\n");
2180 
2181                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2182                               entry_id, enc_algo,
2183                               CAM_CONFIG_NO_USEDK,
2184                               rtlpriv->sec.
2185                               key_buf[key_index]);
2186             } else {
2187                 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2188                     "set group key\n");
2189 
2190                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2191                     rtl_cam_add_one_entry(hw,
2192                         rtlefuse->dev_addr,
2193                         PAIRWISE_KEYIDX,
2194                         CAM_PAIRWISE_KEY_POSITION,
2195                         enc_algo,
2196                         CAM_CONFIG_NO_USEDK,
2197                         rtlpriv->sec.key_buf
2198                         [entry_id]);
2199                 }
2200 
2201                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2202                         entry_id, enc_algo,
2203                         CAM_CONFIG_NO_USEDK,
2204                         rtlpriv->sec.key_buf[entry_id]);
2205             }
2206 
2207         }
2208     }
2209 }
2210 
2211 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2212 {
2213     struct rtl_priv *rtlpriv = rtl_priv(hw);
2214 
2215     rtlpriv->btcoexist.bt_coexistence =
2216             rtlpriv->btcoexist.eeprom_bt_coexist;
2217     rtlpriv->btcoexist.bt_ant_num =
2218             rtlpriv->btcoexist.eeprom_bt_ant_num;
2219     rtlpriv->btcoexist.bt_coexist_type =
2220             rtlpriv->btcoexist.eeprom_bt_type;
2221 
2222     if (rtlpriv->btcoexist.reg_bt_iso == 2)
2223         rtlpriv->btcoexist.bt_ant_isolation =
2224             rtlpriv->btcoexist.eeprom_bt_ant_isol;
2225     else
2226         rtlpriv->btcoexist.bt_ant_isolation =
2227             rtlpriv->btcoexist.reg_bt_iso;
2228 
2229     rtlpriv->btcoexist.bt_radio_shared_type =
2230             rtlpriv->btcoexist.eeprom_bt_radio_shared;
2231 
2232     if (rtlpriv->btcoexist.bt_coexistence) {
2233         if (rtlpriv->btcoexist.reg_bt_sco == 1)
2234             rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2235         else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2236             rtlpriv->btcoexist.bt_service = BT_SCO;
2237         else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2238             rtlpriv->btcoexist.bt_service = BT_BUSY;
2239         else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2240             rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2241         else
2242             rtlpriv->btcoexist.bt_service = BT_IDLE;
2243 
2244         rtlpriv->btcoexist.bt_edca_ul = 0;
2245         rtlpriv->btcoexist.bt_edca_dl = 0;
2246         rtlpriv->btcoexist.bt_rssi_state = 0xff;
2247     }
2248 }
2249 
2250 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2251                           bool auto_load_fail, u8 *hwinfo)
2252 {
2253     struct rtl_priv *rtlpriv = rtl_priv(hw);
2254     u8 val;
2255 
2256     if (!auto_load_fail) {
2257         rtlpriv->btcoexist.eeprom_bt_coexist =
2258                     ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2259         val = hwinfo[RF_OPTION4];
2260         rtlpriv->btcoexist.eeprom_bt_type = ((val & 0xe) >> 1);
2261         rtlpriv->btcoexist.eeprom_bt_ant_num = (val & 0x1);
2262         rtlpriv->btcoexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4);
2263         rtlpriv->btcoexist.eeprom_bt_radio_shared =
2264                              ((val & 0x20) >> 5);
2265     } else {
2266         rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2267         rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2268         rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2269         rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2270         rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2271     }
2272 
2273     rtl8192ce_bt_var_init(hw);
2274 }
2275 
2276 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2277 {
2278     struct rtl_priv *rtlpriv = rtl_priv(hw);
2279 
2280     /* 0:Low, 1:High, 2:From Efuse. */
2281     rtlpriv->btcoexist.reg_bt_iso = 2;
2282     /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2283     rtlpriv->btcoexist.reg_bt_sco = 3;
2284     /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2285     rtlpriv->btcoexist.reg_bt_sco = 0;
2286 }
2287 
2288 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2289 {
2290     struct rtl_priv *rtlpriv = rtl_priv(hw);
2291     struct rtl_phy *rtlphy = &(rtlpriv->phy);
2292 
2293     u8 u1_tmp;
2294 
2295     if (rtlpriv->btcoexist.bt_coexistence &&
2296         ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2297           rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2298 
2299         if (rtlpriv->btcoexist.bt_ant_isolation)
2300             rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2301 
2302         u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & BIT(0);
2303         u1_tmp = u1_tmp |
2304              ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2305              0 : BIT(1)) |
2306              ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2307              0 : BIT(2));
2308         rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2309 
2310         rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2311         rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2312         rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2313 
2314         /* Config to 1T1R. */
2315         if (rtlphy->rf_type == RF_1T1R) {
2316             u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2317             u1_tmp &= ~(BIT(1));
2318             rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2319 
2320             u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2321             u1_tmp &= ~(BIT(1));
2322             rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2323         }
2324     }
2325 }
2326 
2327 void rtl92ce_suspend(struct ieee80211_hw *hw)
2328 {
2329 }
2330 
2331 void rtl92ce_resume(struct ieee80211_hw *hw)
2332 {
2333 }
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