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0002
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0004 #ifndef __RTL92C_PHY_COMMON_H__
0005 #define __RTL92C_PHY_COMMON_H__
0006
0007 #define MAX_PRECMD_CNT 16
0008 #define MAX_RFDEPENDCMD_CNT 16
0009 #define MAX_POSTCMD_CNT 16
0010
0011 #define MAX_DOZE_WAITING_TIMES_9x 64
0012
0013 #define RT_CANNOT_IO(hw) false
0014 #define HIGHPOWER_RADIOA_ARRAYLEN 22
0015
0016 #define MAX_TOLERANCE 5
0017
0018 #define APK_BB_REG_NUM 5
0019 #define APK_AFE_REG_NUM 16
0020 #define APK_CURVE_REG_NUM 4
0021 #define PATH_NUM 2
0022
0023 #define LOOP_LIMIT 5
0024 #define MAX_STALL_TIME 50
0025 #define ANTENNADIVERSITYVALUE 0x80
0026 #define MAX_TXPWR_IDX_NMODE_92S 63
0027 #define RESET_CNT_LIMIT 3
0028
0029 #define IQK_ADDA_REG_NUM 16
0030 #define IQK_MAC_REG_NUM 4
0031
0032 #define IQK_DELAY_TIME 1
0033 #define RF90_PATH_MAX 2
0034
0035 #define CT_OFFSET_MAC_ADDR 0X16
0036
0037 #define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
0038 #define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
0039 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIF 0x66
0040 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
0041 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
0042
0043 #define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
0044 #define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
0045
0046 #define CT_OFFSET_CHANNEL_PLAH 0x75
0047 #define CT_OFFSET_THERMAL_METER 0x78
0048 #define CT_OFFSET_RF_OPTION 0x79
0049 #define CT_OFFSET_VERSION 0x7E
0050 #define CT_OFFSET_CUSTOMER_ID 0x7F
0051
0052 #define RTL92C_MAX_PATH_NUM 2
0053 #define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255
0054
0055 enum swchnlcmd_id {
0056 CMDID_END,
0057 CMDID_SET_TXPOWEROWER_LEVEL,
0058 CMDID_BBREGWRITE10,
0059 CMDID_WRITEPORT_ULONG,
0060 CMDID_WRITEPORT_USHORT,
0061 CMDID_WRITEPORT_UCHAR,
0062 CMDID_RF_WRITEREG,
0063 };
0064
0065 struct swchnlcmd {
0066 enum swchnlcmd_id cmdid;
0067 u32 para1;
0068 u32 para2;
0069 u32 msdelay;
0070 };
0071
0072 enum hw90_block_e {
0073 HW90_BLOCK_MAC = 0,
0074 HW90_BLOCK_PHY0 = 1,
0075 HW90_BLOCK_PHY1 = 2,
0076 HW90_BLOCK_RF = 3,
0077 HW90_BLOCK_MAXIMUM = 4,
0078 };
0079
0080 enum baseband_config_type {
0081 BASEBAND_CONFIG_PHY_REG = 0,
0082 BASEBAND_CONFIG_AGC_TAB = 1,
0083 };
0084
0085 enum ra_offset_area {
0086 RA_OFFSET_LEGACY_OFDM1,
0087 RA_OFFSET_LEGACY_OFDM2,
0088 RA_OFFSET_HT_OFDM1,
0089 RA_OFFSET_HT_OFDM2,
0090 RA_OFFSET_HT_OFDM3,
0091 RA_OFFSET_HT_OFDM4,
0092 RA_OFFSET_HT_CCK,
0093 };
0094
0095 enum antenna_path {
0096 ANTENNA_NONE,
0097 ANTENNA_D,
0098 ANTENNA_C,
0099 ANTENNA_CD,
0100 ANTENNA_B,
0101 ANTENNA_BD,
0102 ANTENNA_BC,
0103 ANTENNA_BCD,
0104 ANTENNA_A,
0105 ANTENNA_AD,
0106 ANTENNA_AC,
0107 ANTENNA_ACD,
0108 ANTENNA_AB,
0109 ANTENNA_ABD,
0110 ANTENNA_ABC,
0111 ANTENNA_ABCD
0112 };
0113
0114 struct r_antenna_select_ofdm {
0115 u32 r_tx_antenna:4;
0116 u32 r_ant_l:4;
0117 u32 r_ant_non_ht:4;
0118 u32 r_ant_ht1:4;
0119 u32 r_ant_ht2:4;
0120 u32 r_ant_ht_s1:4;
0121 u32 r_ant_non_ht_s1:4;
0122 u32 ofdm_txsc:2;
0123 u32 reserved:2;
0124 };
0125
0126 struct r_antenna_select_cck {
0127 u8 r_cckrx_enable_2:2;
0128 u8 r_cckrx_enable:2;
0129 u8 r_ccktx_enable:4;
0130 };
0131
0132 struct efuse_contents {
0133 u8 mac_addr[ETH_ALEN];
0134 u8 cck_tx_power_idx[6];
0135 u8 ht40_1s_tx_power_idx[6];
0136 u8 ht40_2s_tx_power_idx_diff[3];
0137 u8 ht20_tx_power_idx_diff[3];
0138 u8 ofdm_tx_power_idx_diff[3];
0139 u8 ht40_max_power_offset[3];
0140 u8 ht20_max_power_offset[3];
0141 u8 channel_plan;
0142 u8 thermal_meter;
0143 u8 rf_option[5];
0144 u8 version;
0145 u8 oem_id;
0146 u8 regulatory;
0147 };
0148
0149 struct tx_power_struct {
0150 u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0151 u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0152 u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0153 u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0154 u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0155 u8 legacy_ht_txpowerdiff;
0156 u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0157 u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0158 u8 pwrgroup_cnt;
0159 u32 mcs_original_offset[4][16];
0160 };
0161
0162 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw,
0163 u32 regaddr, u32 bitmask);
0164 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
0165 u32 regaddr, u32 bitmask, u32 data);
0166 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
0167 enum radio_path rfpath, u32 regaddr,
0168 u32 bitmask);
0169 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
0170 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
0171 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
0172 bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
0173 enum radio_path rfpath);
0174 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
0175 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw,
0176 long *powerlevel);
0177 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
0178 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
0179 long power_indbm);
0180 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
0181 enum nl80211_channel_type ch_type);
0182 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
0183 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
0184 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
0185 void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw,
0186 u16 beaconinterval);
0187 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta);
0188 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
0189 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
0190 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
0191 enum radio_path rfpath);
0192 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
0193 u32 rfpath);
0194 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
0195 enum rf_pwrstate rfpwr_state);
0196 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
0197 void rtl92c_phy_set_io(struct ieee80211_hw *hw);
0198 void rtl92c_bb_block_on(struct ieee80211_hw *hw);
0199 u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
0200 long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
0201 enum wireless_mode wirelessmode,
0202 u8 txpwridx);
0203 u8 _rtl92c_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
0204 enum wireless_mode wirelessmode,
0205 long power_indbm);
0206 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
0207 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw);
0208 bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
0209 u8 channel, u8 *stage, u8 *step,
0210 u32 *delay);
0211 u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw);
0212 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
0213 enum radio_path rfpath, u32 offset);
0214 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
0215 enum radio_path rfpath, u32 offset,
0216 u32 data);
0217 u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
0218 enum radio_path rfpath, u32 offset);
0219 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
0220 enum radio_path rfpath, u32 offset,
0221 u32 data);
0222 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
0223 void _rtl92c_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
0224 u32 regaddr, u32 bitmask,
0225 u32 data);
0226 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
0227
0228 #endif
