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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003 
0004 #include "../wifi.h"
0005 #include "../rtl8192ce/reg.h"
0006 #include "../rtl8192ce/def.h"
0007 #include "dm_common.h"
0008 #include "fw_common.h"
0009 #include "phy_common.h"
0010 #include <linux/export.h>
0011 
0012 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
0013 {
0014     struct rtl_priv *rtlpriv = rtl_priv(hw);
0015     u32 returnvalue, originalvalue, bitshift;
0016 
0017     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
0018         regaddr, bitmask);
0019     originalvalue = rtl_read_dword(rtlpriv, regaddr);
0020     bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
0021     returnvalue = (originalvalue & bitmask) >> bitshift;
0022 
0023     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0024         "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
0025         bitmask, regaddr, originalvalue);
0026 
0027     return returnvalue;
0028 }
0029 EXPORT_SYMBOL(rtl92c_phy_query_bb_reg);
0030 
0031 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
0032                u32 regaddr, u32 bitmask, u32 data)
0033 {
0034     struct rtl_priv *rtlpriv = rtl_priv(hw);
0035     u32 originalvalue, bitshift;
0036 
0037     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0038         "regaddr(%#x), bitmask(%#x), data(%#x)\n",
0039         regaddr, bitmask, data);
0040 
0041     if (bitmask != MASKDWORD) {
0042         originalvalue = rtl_read_dword(rtlpriv, regaddr);
0043         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
0044         data = ((originalvalue & (~bitmask)) | (data << bitshift));
0045     }
0046 
0047     rtl_write_dword(rtlpriv, regaddr, data);
0048 
0049     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
0050         "regaddr(%#x), bitmask(%#x), data(%#x)\n",
0051         regaddr, bitmask, data);
0052 }
0053 EXPORT_SYMBOL(rtl92c_phy_set_bb_reg);
0054 
0055 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
0056                   enum radio_path rfpath, u32 offset)
0057 {
0058     WARN_ONCE(true, "rtl8192c-common: _rtl92c_phy_fw_rf_serial_read deprecated!\n");
0059     return 0;
0060 }
0061 EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_read);
0062 
0063 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
0064                     enum radio_path rfpath, u32 offset,
0065                     u32 data)
0066 {
0067     WARN_ONCE(true, "rtl8192c-common: _rtl92c_phy_fw_rf_serial_write deprecated!\n");
0068 }
0069 EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_write);
0070 
0071 u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
0072                    enum radio_path rfpath, u32 offset)
0073 {
0074     struct rtl_priv *rtlpriv = rtl_priv(hw);
0075     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0076     struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
0077     u32 newoffset;
0078     u32 tmplong, tmplong2;
0079     u8 rfpi_enable = 0;
0080     u32 retvalue;
0081 
0082     offset &= 0x3f;
0083     newoffset = offset;
0084     if (RT_CANNOT_IO(hw)) {
0085         pr_err("return all one\n");
0086         return 0xFFFFFFFF;
0087     }
0088     tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
0089     if (rfpath == RF90_PATH_A)
0090         tmplong2 = tmplong;
0091     else
0092         tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
0093     tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
0094         (newoffset << 23) | BLSSIREADEDGE;
0095     rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
0096               tmplong & (~BLSSIREADEDGE));
0097     mdelay(1);
0098     rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
0099     mdelay(1);
0100     rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
0101               tmplong | BLSSIREADEDGE);
0102     mdelay(1);
0103     if (rfpath == RF90_PATH_A)
0104         rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
0105                          BIT(8));
0106     else if (rfpath == RF90_PATH_B)
0107         rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
0108                          BIT(8));
0109     if (rfpi_enable)
0110         retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
0111                      BLSSIREADBACKDATA);
0112     else
0113         retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
0114                      BLSSIREADBACKDATA);
0115     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
0116         rfpath, pphyreg->rf_rb,
0117         retvalue);
0118     return retvalue;
0119 }
0120 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read);
0121 
0122 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
0123                  enum radio_path rfpath, u32 offset,
0124                  u32 data)
0125 {
0126     u32 data_and_addr;
0127     u32 newoffset;
0128     struct rtl_priv *rtlpriv = rtl_priv(hw);
0129     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0130     struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
0131 
0132     if (RT_CANNOT_IO(hw)) {
0133         pr_err("stop\n");
0134         return;
0135     }
0136     offset &= 0x3f;
0137     newoffset = offset;
0138     data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
0139     rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
0140     rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
0141         rfpath, pphyreg->rf3wire_offset,
0142         data_and_addr);
0143 }
0144 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write);
0145 
0146 u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
0147 {
0148     u32 i = ffs(bitmask);
0149 
0150     return i ? i - 1 : 32;
0151 }
0152 EXPORT_SYMBOL(_rtl92c_phy_calculate_bit_shift);
0153 
0154 static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw)
0155 {
0156     rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
0157     rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
0158     rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
0159     rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
0160     rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
0161     rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
0162     rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
0163     rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
0164     rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
0165     rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
0166 }
0167 
0168 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw)
0169 {
0170     struct rtl_priv *rtlpriv = rtl_priv(hw);
0171 
0172     return rtlpriv->cfg->ops->phy_rf6052_config(hw);
0173 }
0174 EXPORT_SYMBOL(rtl92c_phy_rf_config);
0175 
0176 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
0177 {
0178     struct rtl_priv *rtlpriv = rtl_priv(hw);
0179     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0180     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0181     bool rtstatus;
0182 
0183     rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
0184                          BASEBAND_CONFIG_PHY_REG);
0185     if (!rtstatus) {
0186         pr_err("Write BB Reg Fail!!\n");
0187         return false;
0188     }
0189     if (rtlphy->rf_type == RF_1T2R) {
0190         _rtl92c_phy_bb_config_1t(hw);
0191         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
0192     }
0193     if (rtlefuse->autoload_failflag == false) {
0194         rtlphy->pwrgroup_cnt = 0;
0195         rtstatus = rtlpriv->cfg->ops->config_bb_with_pgheaderfile(hw,
0196                            BASEBAND_CONFIG_PHY_REG);
0197     }
0198     if (!rtstatus) {
0199         pr_err("BB_PG Reg Fail!!\n");
0200         return false;
0201     }
0202     rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
0203                          BASEBAND_CONFIG_AGC_TAB);
0204     if (!rtstatus) {
0205         pr_err("AGC Table Fail\n");
0206         return false;
0207     }
0208     rtlphy->cck_high_power =
0209         (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200));
0210 
0211     return true;
0212 }
0213 
0214 EXPORT_SYMBOL(_rtl92c_phy_bb8192c_config_parafile);
0215 
0216 void _rtl92c_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
0217                         u32 regaddr, u32 bitmask,
0218                         u32 data)
0219 {
0220     struct rtl_priv *rtlpriv = rtl_priv(hw);
0221     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0222 
0223     if (regaddr == RTXAGC_A_RATE18_06) {
0224         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
0225             data;
0226         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0227             "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
0228             rtlphy->pwrgroup_cnt,
0229             rtlphy->mcs_txpwrlevel_origoffset
0230             [rtlphy->pwrgroup_cnt][0]);
0231     }
0232     if (regaddr == RTXAGC_A_RATE54_24) {
0233         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
0234             data;
0235         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0236             "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
0237             rtlphy->pwrgroup_cnt,
0238             rtlphy->mcs_txpwrlevel_origoffset
0239             [rtlphy->pwrgroup_cnt][1]);
0240     }
0241     if (regaddr == RTXAGC_A_CCK1_MCS32) {
0242         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
0243             data;
0244         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0245             "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
0246             rtlphy->pwrgroup_cnt,
0247             rtlphy->mcs_txpwrlevel_origoffset
0248             [rtlphy->pwrgroup_cnt][6]);
0249     }
0250     if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
0251         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
0252             data;
0253         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0254             "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
0255             rtlphy->pwrgroup_cnt,
0256             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0257                                 pwrgroup_cnt][7]);
0258     }
0259     if (regaddr == RTXAGC_A_MCS03_MCS00) {
0260         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
0261             data;
0262         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0263             "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
0264             rtlphy->pwrgroup_cnt,
0265             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0266                                 pwrgroup_cnt][2]);
0267     }
0268     if (regaddr == RTXAGC_A_MCS07_MCS04) {
0269         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
0270             data;
0271         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0272             "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
0273             rtlphy->pwrgroup_cnt,
0274             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0275                                 pwrgroup_cnt][3]);
0276     }
0277     if (regaddr == RTXAGC_A_MCS11_MCS08) {
0278         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
0279             data;
0280         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0281             "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
0282             rtlphy->pwrgroup_cnt,
0283             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0284                                 pwrgroup_cnt][4]);
0285     }
0286     if (regaddr == RTXAGC_A_MCS15_MCS12) {
0287         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
0288             data;
0289         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0290             "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
0291             rtlphy->pwrgroup_cnt,
0292             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0293                                 pwrgroup_cnt][5]);
0294     }
0295     if (regaddr == RTXAGC_B_RATE18_06) {
0296         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
0297             data;
0298         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0299             "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
0300             rtlphy->pwrgroup_cnt,
0301             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0302                                 pwrgroup_cnt][8]);
0303     }
0304     if (regaddr == RTXAGC_B_RATE54_24) {
0305         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
0306             data;
0307         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0308             "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
0309             rtlphy->pwrgroup_cnt,
0310             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0311                                 pwrgroup_cnt][9]);
0312     }
0313     if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
0314         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
0315             data;
0316         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0317             "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
0318             rtlphy->pwrgroup_cnt,
0319             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0320                                 pwrgroup_cnt][14]);
0321     }
0322     if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
0323         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
0324             data;
0325         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0326             "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
0327             rtlphy->pwrgroup_cnt,
0328             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0329                                 pwrgroup_cnt][15]);
0330     }
0331     if (regaddr == RTXAGC_B_MCS03_MCS00) {
0332         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
0333             data;
0334         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0335             "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
0336             rtlphy->pwrgroup_cnt,
0337             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0338                                 pwrgroup_cnt][10]);
0339     }
0340     if (regaddr == RTXAGC_B_MCS07_MCS04) {
0341         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
0342             data;
0343         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0344             "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
0345             rtlphy->pwrgroup_cnt,
0346             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0347                                 pwrgroup_cnt][11]);
0348     }
0349     if (regaddr == RTXAGC_B_MCS11_MCS08) {
0350         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
0351             data;
0352         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0353             "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
0354             rtlphy->pwrgroup_cnt,
0355             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0356                                 pwrgroup_cnt][12]);
0357     }
0358     if (regaddr == RTXAGC_B_MCS15_MCS12) {
0359         rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
0360             data;
0361         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0362             "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
0363             rtlphy->pwrgroup_cnt,
0364             rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
0365                                 pwrgroup_cnt][13]);
0366 
0367         rtlphy->pwrgroup_cnt++;
0368     }
0369 }
0370 EXPORT_SYMBOL(_rtl92c_store_pwrindex_diffrate_offset);
0371 
0372 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
0373 {
0374     struct rtl_priv *rtlpriv = rtl_priv(hw);
0375     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0376 
0377     rtlphy->default_initialgain[0] =
0378         (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
0379     rtlphy->default_initialgain[1] =
0380         (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
0381     rtlphy->default_initialgain[2] =
0382         (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
0383     rtlphy->default_initialgain[3] =
0384         (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
0385 
0386     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0387         "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
0388         rtlphy->default_initialgain[0],
0389         rtlphy->default_initialgain[1],
0390         rtlphy->default_initialgain[2],
0391         rtlphy->default_initialgain[3]);
0392 
0393     rtlphy->framesync = (u8)rtl_get_bbreg(hw,
0394                            ROFDM0_RXDETECTOR3, MASKBYTE0);
0395     rtlphy->framesync_c34 = rtl_get_bbreg(hw,
0396                           ROFDM0_RXDETECTOR2, MASKDWORD);
0397 
0398     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0399         "Default framesync (0x%x) = 0x%x\n",
0400         ROFDM0_RXDETECTOR3, rtlphy->framesync);
0401 }
0402 
0403 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
0404 {
0405     struct rtl_priv *rtlpriv = rtl_priv(hw);
0406     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0407 
0408     rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
0409     rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
0410     rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
0411     rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
0412 
0413     rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
0414     rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
0415     rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
0416     rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
0417 
0418     rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
0419     rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
0420 
0421     rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
0422     rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
0423 
0424     rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
0425         RFPGA0_XA_LSSIPARAMETER;
0426     rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
0427         RFPGA0_XB_LSSIPARAMETER;
0428 
0429     rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
0430     rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
0431     rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
0432     rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
0433 
0434     rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0435     rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0436     rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0437     rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
0438 
0439     rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
0440     rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
0441 
0442     rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
0443     rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
0444 
0445     rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
0446     rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
0447     rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
0448     rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
0449 
0450     rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
0451     rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
0452     rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
0453     rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
0454 
0455     rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
0456     rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
0457     rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
0458     rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
0459 
0460     rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
0461     rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
0462     rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
0463     rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
0464 
0465     rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
0466     rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
0467     rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
0468     rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
0469 
0470     rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
0471     rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
0472     rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
0473     rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
0474 
0475     rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
0476     rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
0477     rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
0478     rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
0479 
0480     rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
0481     rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
0482     rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
0483     rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
0484 
0485     rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
0486     rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
0487 
0488 }
0489 EXPORT_SYMBOL(_rtl92c_phy_init_bb_rf_register_definition);
0490 
0491 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
0492 {
0493     struct rtl_priv *rtlpriv = rtl_priv(hw);
0494     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0495     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0496     u8 txpwr_level;
0497     long txpwr_dbm;
0498 
0499     txpwr_level = rtlphy->cur_cck_txpwridx;
0500     txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B,
0501                          txpwr_level);
0502     txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
0503         rtlefuse->legacy_ht_txpowerdiff;
0504     if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
0505                      txpwr_level) > txpwr_dbm)
0506         txpwr_dbm =
0507             _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
0508                          txpwr_level);
0509     txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
0510     if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
0511                      txpwr_level) > txpwr_dbm)
0512         txpwr_dbm =
0513             _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
0514                          txpwr_level);
0515     *powerlevel = txpwr_dbm;
0516 }
0517 
0518 static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
0519                       u8 *cckpowerlevel, u8 *ofdmpowerlevel)
0520 {
0521     struct rtl_priv *rtlpriv = rtl_priv(hw);
0522     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0523     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0524     u8 index = (channel - 1);
0525 
0526     cckpowerlevel[RF90_PATH_A] =
0527         rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
0528     cckpowerlevel[RF90_PATH_B] =
0529         rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
0530     if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
0531         ofdmpowerlevel[RF90_PATH_A] =
0532             rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
0533         ofdmpowerlevel[RF90_PATH_B] =
0534             rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
0535     } else if (get_rf_type(rtlphy) == RF_2T2R) {
0536         ofdmpowerlevel[RF90_PATH_A] =
0537             rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
0538         ofdmpowerlevel[RF90_PATH_B] =
0539             rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
0540     }
0541 }
0542 
0543 static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
0544                      u8 channel, u8 *cckpowerlevel,
0545                      u8 *ofdmpowerlevel)
0546 {
0547     struct rtl_priv *rtlpriv = rtl_priv(hw);
0548     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0549 
0550     rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
0551     rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
0552 }
0553 
0554 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
0555 {
0556     struct rtl_priv *rtlpriv = rtl_priv(hw);
0557     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0558     u8 cckpowerlevel[2], ofdmpowerlevel[2];
0559 
0560     if (!rtlefuse->txpwr_fromeprom)
0561         return;
0562     _rtl92c_get_txpower_index(hw, channel,
0563                   &cckpowerlevel[0], &ofdmpowerlevel[0]);
0564     _rtl92c_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
0565                      &ofdmpowerlevel[0]);
0566     rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
0567     rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
0568                                channel);
0569 }
0570 EXPORT_SYMBOL(rtl92c_phy_set_txpower_level);
0571 
0572 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
0573 {
0574     struct rtl_priv *rtlpriv = rtl_priv(hw);
0575     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0576     struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0577     u8 idx;
0578     u8 rf_path;
0579     u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_B,
0580                               power_indbm);
0581     u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_N_24G,
0582                                power_indbm);
0583     if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
0584         ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
0585     else
0586         ofdmtxpwridx = 0;
0587     rtl_dbg(rtlpriv, COMP_TXAGC, DBG_TRACE,
0588         "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
0589         power_indbm, ccktxpwridx, ofdmtxpwridx);
0590     for (idx = 0; idx < 14; idx++) {
0591         for (rf_path = 0; rf_path < 2; rf_path++) {
0592             rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
0593             rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
0594                 ofdmtxpwridx;
0595             rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
0596                 ofdmtxpwridx;
0597         }
0598     }
0599     rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
0600     return true;
0601 }
0602 EXPORT_SYMBOL(rtl92c_phy_update_txpower_dbm);
0603 
0604 u8 _rtl92c_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
0605                 enum wireless_mode wirelessmode,
0606                 long power_indbm)
0607 {
0608     u8 txpwridx;
0609     long offset;
0610 
0611     switch (wirelessmode) {
0612     case WIRELESS_MODE_B:
0613         offset = -7;
0614         break;
0615     case WIRELESS_MODE_G:
0616     case WIRELESS_MODE_N_24G:
0617         offset = -8;
0618         break;
0619     default:
0620         offset = -8;
0621         break;
0622     }
0623 
0624     if ((power_indbm - offset) > 0)
0625         txpwridx = (u8)((power_indbm - offset) * 2);
0626     else
0627         txpwridx = 0;
0628 
0629     if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
0630         txpwridx = MAX_TXPWR_IDX_NMODE_92S;
0631 
0632     return txpwridx;
0633 }
0634 EXPORT_SYMBOL(_rtl92c_phy_dbm_to_txpwr_idx);
0635 
0636 long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
0637                   enum wireless_mode wirelessmode,
0638                   u8 txpwridx)
0639 {
0640     long offset;
0641     long pwrout_dbm;
0642 
0643     switch (wirelessmode) {
0644     case WIRELESS_MODE_B:
0645         offset = -7;
0646         break;
0647     case WIRELESS_MODE_G:
0648     case WIRELESS_MODE_N_24G:
0649         offset = -8;
0650         break;
0651     default:
0652         offset = -8;
0653         break;
0654     }
0655     pwrout_dbm = txpwridx / 2 + offset;
0656     return pwrout_dbm;
0657 }
0658 EXPORT_SYMBOL(_rtl92c_phy_txpwr_idx_to_dbm);
0659 
0660 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
0661                 enum nl80211_channel_type ch_type)
0662 {
0663     struct rtl_priv *rtlpriv = rtl_priv(hw);
0664     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0665     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0666     u8 tmp_bw = rtlphy->current_chan_bw;
0667 
0668     if (rtlphy->set_bwmode_inprogress)
0669         return;
0670     rtlphy->set_bwmode_inprogress = true;
0671     if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
0672         rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw);
0673     } else {
0674         rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
0675             "false driver sleep or unload\n");
0676         rtlphy->set_bwmode_inprogress = false;
0677         rtlphy->current_chan_bw = tmp_bw;
0678     }
0679 }
0680 EXPORT_SYMBOL(rtl92c_phy_set_bw_mode);
0681 
0682 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
0683 {
0684     struct rtl_priv *rtlpriv = rtl_priv(hw);
0685     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0686     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0687     u32 delay;
0688 
0689     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
0690         "switch to channel%d\n", rtlphy->current_channel);
0691     if (is_hal_stop(rtlhal))
0692         return;
0693     do {
0694         if (!rtlphy->sw_chnl_inprogress)
0695             break;
0696         if (!_rtl92c_phy_sw_chnl_step_by_step
0697             (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
0698              &rtlphy->sw_chnl_step, &delay)) {
0699             if (delay > 0)
0700                 mdelay(delay);
0701             else
0702                 continue;
0703         } else {
0704             rtlphy->sw_chnl_inprogress = false;
0705         }
0706         break;
0707     } while (true);
0708     rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
0709 }
0710 EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback);
0711 
0712 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
0713 {
0714     struct rtl_priv *rtlpriv = rtl_priv(hw);
0715     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0716     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0717 
0718     if (rtlphy->sw_chnl_inprogress)
0719         return 0;
0720     if (rtlphy->set_bwmode_inprogress)
0721         return 0;
0722     WARN_ONCE((rtlphy->current_channel > 14),
0723           "rtl8192c-common: WIRELESS_MODE_G but channel>14");
0724     rtlphy->sw_chnl_inprogress = true;
0725     rtlphy->sw_chnl_stage = 0;
0726     rtlphy->sw_chnl_step = 0;
0727     if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
0728         rtl92c_phy_sw_chnl_callback(hw);
0729         rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
0730             "sw_chnl_inprogress false schedule workitem\n");
0731         rtlphy->sw_chnl_inprogress = false;
0732     } else {
0733         rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
0734             "sw_chnl_inprogress false driver sleep or unload\n");
0735         rtlphy->sw_chnl_inprogress = false;
0736     }
0737     return 1;
0738 }
0739 EXPORT_SYMBOL(rtl92c_phy_sw_chnl);
0740 
0741 static void _rtl92c_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel)
0742 {
0743     struct rtl_priv *rtlpriv = rtl_priv(hw);
0744     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0745     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0746 
0747     if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
0748         if (channel == 6 &&
0749             rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
0750             rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
0751                       MASKDWORD, 0x00255);
0752         } else {
0753             u32 backuprf0x1A =
0754               (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
0755                          RFREG_OFFSET_MASK);
0756             rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
0757                       backuprf0x1A);
0758         }
0759     }
0760 }
0761 
0762 static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
0763                          u32 cmdtableidx, u32 cmdtablesz,
0764                          enum swchnlcmd_id cmdid,
0765                          u32 para1, u32 para2, u32 msdelay)
0766 {
0767     struct swchnlcmd *pcmd;
0768 
0769     if (cmdtable == NULL) {
0770         WARN_ONCE(true, "rtl8192c-common: cmdtable cannot be NULL.\n");
0771         return false;
0772     }
0773 
0774     if (cmdtableidx >= cmdtablesz)
0775         return false;
0776 
0777     pcmd = cmdtable + cmdtableidx;
0778     pcmd->cmdid = cmdid;
0779     pcmd->para1 = para1;
0780     pcmd->para2 = para2;
0781     pcmd->msdelay = msdelay;
0782     return true;
0783 }
0784 
0785 bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
0786                       u8 channel, u8 *stage, u8 *step,
0787                       u32 *delay)
0788 {
0789     struct rtl_priv *rtlpriv = rtl_priv(hw);
0790     struct rtl_phy *rtlphy = &(rtlpriv->phy);
0791     struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
0792     u32 precommoncmdcnt;
0793     struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
0794     u32 postcommoncmdcnt;
0795     struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
0796     u32 rfdependcmdcnt;
0797     struct swchnlcmd *currentcmd = NULL;
0798     u8 rfpath;
0799     u8 num_total_rfpath = rtlphy->num_total_rfpath;
0800 
0801     precommoncmdcnt = 0;
0802     _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
0803                      MAX_PRECMD_CNT,
0804                      CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
0805     _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
0806                      MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
0807 
0808     postcommoncmdcnt = 0;
0809 
0810     _rtl92c_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
0811                      MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
0812 
0813     rfdependcmdcnt = 0;
0814 
0815     WARN_ONCE((channel < 1 || channel > 14),
0816           "rtl8192c-common: illegal channel for Zebra: %d\n", channel);
0817 
0818     _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
0819                      MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
0820                      RF_CHNLBW, channel, 10);
0821 
0822     _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
0823                      MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
0824                      0);
0825 
0826     do {
0827         switch (*stage) {
0828         case 0:
0829             currentcmd = &precommoncmd[*step];
0830             break;
0831         case 1:
0832             currentcmd = &rfdependcmd[*step];
0833             break;
0834         case 2:
0835             currentcmd = &postcommoncmd[*step];
0836             break;
0837         default:
0838             pr_err("Invalid 'stage' = %d, Check it!\n",
0839                    *stage);
0840             return true;
0841         }
0842 
0843         if (currentcmd->cmdid == CMDID_END) {
0844             if ((*stage) == 2) {
0845                 return true;
0846             } else {
0847                 (*stage)++;
0848                 (*step) = 0;
0849                 continue;
0850             }
0851         }
0852 
0853         switch (currentcmd->cmdid) {
0854         case CMDID_SET_TXPOWEROWER_LEVEL:
0855             rtl92c_phy_set_txpower_level(hw, channel);
0856             break;
0857         case CMDID_WRITEPORT_ULONG:
0858             rtl_write_dword(rtlpriv, currentcmd->para1,
0859                     currentcmd->para2);
0860             break;
0861         case CMDID_WRITEPORT_USHORT:
0862             rtl_write_word(rtlpriv, currentcmd->para1,
0863                        (u16) currentcmd->para2);
0864             break;
0865         case CMDID_WRITEPORT_UCHAR:
0866             rtl_write_byte(rtlpriv, currentcmd->para1,
0867                        (u8)currentcmd->para2);
0868             break;
0869         case CMDID_RF_WRITEREG:
0870             for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
0871                 rtlphy->rfreg_chnlval[rfpath] =
0872                     ((rtlphy->rfreg_chnlval[rfpath] &
0873                       0xfffffc00) | currentcmd->para2);
0874 
0875                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
0876                           currentcmd->para1,
0877                           RFREG_OFFSET_MASK,
0878                           rtlphy->rfreg_chnlval[rfpath]);
0879             }
0880             _rtl92c_phy_sw_rf_seting(hw, channel);
0881             break;
0882         default:
0883             rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
0884                 "switch case %#x not processed\n",
0885                 currentcmd->cmdid);
0886             break;
0887         }
0888 
0889         break;
0890     } while (true);
0891 
0892     (*delay) = currentcmd->msdelay;
0893     (*step)++;
0894     return false;
0895 }
0896 
0897 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath)
0898 {
0899     return true;
0900 }
0901 EXPORT_SYMBOL(rtl8192_phy_check_is_legal_rfpath);
0902 
0903 static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
0904 {
0905     u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
0906     u8 result = 0x00;
0907 
0908     rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
0909     rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
0910     rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
0911     rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
0912               config_pathb ? 0x28160202 : 0x28160502);
0913 
0914     if (config_pathb) {
0915         rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
0916         rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
0917         rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
0918         rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
0919     }
0920 
0921     rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
0922     rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
0923     rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
0924 
0925     mdelay(IQK_DELAY_TIME);
0926 
0927     reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
0928     reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
0929     reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
0930     reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
0931 
0932     if (!(reg_eac & BIT(28)) &&
0933         (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
0934         (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
0935         result |= 0x01;
0936     else
0937         return result;
0938 
0939     if (!(reg_eac & BIT(27)) &&
0940         (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
0941         (((reg_eac & 0x03FF0000) >> 16) != 0x36))
0942         result |= 0x02;
0943     return result;
0944 }
0945 
0946 static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
0947 {
0948     u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
0949     u8 result = 0x00;
0950 
0951     rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
0952     rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
0953     mdelay(IQK_DELAY_TIME);
0954     reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
0955     reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
0956     reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
0957     reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
0958     reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
0959 
0960     if (!(reg_eac & BIT(31)) &&
0961         (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
0962         (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
0963         result |= 0x01;
0964     else
0965         return result;
0966     if (!(reg_eac & BIT(30)) &&
0967         (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
0968         (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
0969         result |= 0x02;
0970     return result;
0971 }
0972 
0973 static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
0974                            bool b_iqk_ok, long result[][8],
0975                            u8 final_candidate, bool btxonly)
0976 {
0977     u32 oldval_0, x, tx0_a, reg;
0978     long y, tx0_c;
0979 
0980     if (final_candidate == 0xFF) {
0981         return;
0982     } else if (b_iqk_ok) {
0983         oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
0984                       MASKDWORD) >> 22) & 0x3FF;
0985         x = result[final_candidate][0];
0986         if ((x & 0x00000200) != 0)
0987             x = x | 0xFFFFFC00;
0988         tx0_a = (x * oldval_0) >> 8;
0989         rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
0990         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
0991                   ((x * oldval_0 >> 7) & 0x1));
0992         y = result[final_candidate][1];
0993         if ((y & 0x00000200) != 0)
0994             y = y | 0xFFFFFC00;
0995         tx0_c = (y * oldval_0) >> 8;
0996         rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
0997                   ((tx0_c & 0x3C0) >> 6));
0998         rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
0999                   (tx0_c & 0x3F));
1000         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1001                   ((y * oldval_0 >> 7) & 0x1));
1002         if (btxonly)
1003             return;
1004         reg = result[final_candidate][2];
1005         rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1006         reg = result[final_candidate][3] & 0x3F;
1007         rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1008         reg = (result[final_candidate][3] >> 6) & 0xF;
1009         rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1010     }
1011 }
1012 
1013 static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
1014                            bool b_iqk_ok, long result[][8],
1015                            u8 final_candidate, bool btxonly)
1016 {
1017     u32 oldval_1, x, tx1_a, reg;
1018     long y, tx1_c;
1019 
1020     if (final_candidate == 0xFF) {
1021         return;
1022     } else if (b_iqk_ok) {
1023         oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
1024                       MASKDWORD) >> 22) & 0x3FF;
1025         x = result[final_candidate][4];
1026         if ((x & 0x00000200) != 0)
1027             x = x | 0xFFFFFC00;
1028         tx1_a = (x * oldval_1) >> 8;
1029         rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
1030         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
1031                   ((x * oldval_1 >> 7) & 0x1));
1032         y = result[final_candidate][5];
1033         if ((y & 0x00000200) != 0)
1034             y = y | 0xFFFFFC00;
1035         tx1_c = (y * oldval_1) >> 8;
1036         rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
1037                   ((tx1_c & 0x3C0) >> 6));
1038         rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
1039                   (tx1_c & 0x3F));
1040         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
1041                   ((y * oldval_1 >> 7) & 0x1));
1042         if (btxonly)
1043             return;
1044         reg = result[final_candidate][6];
1045         rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
1046         reg = result[final_candidate][7] & 0x3F;
1047         rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
1048         reg = (result[final_candidate][7] >> 6) & 0xF;
1049         rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
1050     }
1051 }
1052 
1053 static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw,
1054                         u32 *addareg, u32 *addabackup,
1055                         u32 registernum)
1056 {
1057     u32 i;
1058 
1059     for (i = 0; i < registernum; i++)
1060         addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1061 }
1062 
1063 static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw,
1064                        u32 *macreg, u32 *macbackup)
1065 {
1066     struct rtl_priv *rtlpriv = rtl_priv(hw);
1067     u32 i;
1068 
1069     for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1070         macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1071     macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1072 }
1073 
1074 static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw,
1075                           u32 *addareg, u32 *addabackup,
1076                           u32 regiesternum)
1077 {
1078     u32 i;
1079 
1080     for (i = 0; i < regiesternum; i++)
1081         rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1082 }
1083 
1084 static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
1085                          u32 *macreg, u32 *macbackup)
1086 {
1087     struct rtl_priv *rtlpriv = rtl_priv(hw);
1088     u32 i;
1089 
1090     for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1091         rtl_write_byte(rtlpriv, macreg[i], (u8)macbackup[i]);
1092     rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1093 }
1094 
1095 static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
1096                      u32 *addareg, bool is_patha_on, bool is2t)
1097 {
1098     u32 pathon;
1099     u32 i;
1100 
1101     pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1102     if (!is2t) {
1103         pathon = 0x0bdb25a0;
1104         rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1105     } else {
1106         rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
1107     }
1108 
1109     for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1110         rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
1111 }
1112 
1113 static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1114                         u32 *macreg, u32 *macbackup)
1115 {
1116     struct rtl_priv *rtlpriv = rtl_priv(hw);
1117     u32 i = 0;
1118 
1119     rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1120 
1121     for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1122         rtl_write_byte(rtlpriv, macreg[i],
1123                    (u8)(macbackup[i] & (~BIT(3))));
1124     rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & (~BIT(5))));
1125 }
1126 
1127 static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
1128 {
1129     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1130     rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1131     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1132 }
1133 
1134 static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1135 {
1136     u32 mode;
1137 
1138     mode = pi_mode ? 0x01000100 : 0x01000000;
1139     rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1140     rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1141 }
1142 
1143 static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
1144                        long result[][8], u8 c1, u8 c2)
1145 {
1146     u32 i, j, diff, simularity_bitmap, bound;
1147     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1148 
1149     u8 final_candidate[2] = { 0xFF, 0xFF };
1150     bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1151 
1152     if (is2t)
1153         bound = 8;
1154     else
1155         bound = 4;
1156 
1157     simularity_bitmap = 0;
1158 
1159     for (i = 0; i < bound; i++) {
1160         diff = (result[c1][i] > result[c2][i]) ?
1161             (result[c1][i] - result[c2][i]) :
1162             (result[c2][i] - result[c1][i]);
1163 
1164         if (diff > MAX_TOLERANCE) {
1165             if ((i == 2 || i == 6) && !simularity_bitmap) {
1166                 if (result[c1][i] + result[c1][i + 1] == 0)
1167                     final_candidate[(i / 4)] = c2;
1168                 else if (result[c2][i] + result[c2][i + 1] == 0)
1169                     final_candidate[(i / 4)] = c1;
1170                 else
1171                     simularity_bitmap = simularity_bitmap |
1172                         (1 << i);
1173             } else
1174                 simularity_bitmap =
1175                     simularity_bitmap | (1 << i);
1176         }
1177     }
1178 
1179     if (simularity_bitmap == 0) {
1180         for (i = 0; i < (bound / 4); i++) {
1181             if (final_candidate[i] != 0xFF) {
1182                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1183                     result[3][j] =
1184                         result[final_candidate[i]][j];
1185                 bresult = false;
1186             }
1187         }
1188         return bresult;
1189     } else if (!(simularity_bitmap & 0x0F)) {
1190         for (i = 0; i < 4; i++)
1191             result[3][i] = result[c1][i];
1192         return false;
1193     } else if (!(simularity_bitmap & 0xF0) && is2t) {
1194         for (i = 4; i < 8; i++)
1195             result[3][i] = result[c1][i];
1196         return false;
1197     } else {
1198         return false;
1199     }
1200 }
1201 
1202 static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1203                      long result[][8], u8 t, bool is2t)
1204 {
1205     struct rtl_priv *rtlpriv = rtl_priv(hw);
1206     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1207     u32 i;
1208     u8 patha_ok, pathb_ok;
1209     u32 adda_reg[IQK_ADDA_REG_NUM] = {
1210         0x85c, 0xe6c, 0xe70, 0xe74,
1211         0xe78, 0xe7c, 0xe80, 0xe84,
1212         0xe88, 0xe8c, 0xed0, 0xed4,
1213         0xed8, 0xedc, 0xee0, 0xeec
1214     };
1215     u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1216         0x522, 0x550, 0x551, 0x040
1217     };
1218     const u32 retrycount = 2;
1219 
1220     if (t == 0) {
1221         rtl_get_bbreg(hw, 0x800, MASKDWORD);
1222 
1223         _rtl92c_phy_save_adda_registers(hw, adda_reg,
1224                         rtlphy->adda_backup, 16);
1225         _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
1226                            rtlphy->iqk_mac_backup);
1227     }
1228     _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
1229     if (t == 0) {
1230         rtlphy->rfpi_enable =
1231            (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
1232                      BIT(8));
1233     }
1234 
1235     if (!rtlphy->rfpi_enable)
1236         _rtl92c_phy_pi_mode_switch(hw, true);
1237     if (t == 0) {
1238         rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1239         rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1240         rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1241     }
1242     rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1243     rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1244     rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1245     if (is2t) {
1246         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1247         rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1248     }
1249     _rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg,
1250                         rtlphy->iqk_mac_backup);
1251     rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1252     if (is2t)
1253         rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1254     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1255     rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1256     rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1257     for (i = 0; i < retrycount; i++) {
1258         patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t);
1259         if (patha_ok == 0x03) {
1260             result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1261                     0x3FF0000) >> 16;
1262             result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1263                     0x3FF0000) >> 16;
1264             result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1265                     0x3FF0000) >> 16;
1266             result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1267                     0x3FF0000) >> 16;
1268             break;
1269         } else if (i == (retrycount - 1) && patha_ok == 0x01)
1270 
1271             result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1272                               MASKDWORD) & 0x3FF0000) >>
1273                 16;
1274         result[t][1] =
1275             (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1276 
1277     }
1278 
1279     if (is2t) {
1280         _rtl92c_phy_path_a_standby(hw);
1281         _rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t);
1282         for (i = 0; i < retrycount; i++) {
1283             pathb_ok = _rtl92c_phy_path_b_iqk(hw);
1284             if (pathb_ok == 0x03) {
1285                 result[t][4] = (rtl_get_bbreg(hw,
1286                                   0xeb4,
1287                                   MASKDWORD) &
1288                         0x3FF0000) >> 16;
1289                 result[t][5] =
1290                     (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1291                      0x3FF0000) >> 16;
1292                 result[t][6] =
1293                     (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1294                      0x3FF0000) >> 16;
1295                 result[t][7] =
1296                     (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1297                      0x3FF0000) >> 16;
1298                 break;
1299             } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1300                 result[t][4] = (rtl_get_bbreg(hw,
1301                                   0xeb4,
1302                                   MASKDWORD) &
1303                         0x3FF0000) >> 16;
1304             }
1305             result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1306                     0x3FF0000) >> 16;
1307         }
1308     }
1309     rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1310     rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1311     rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1312     rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1313     rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1314     if (is2t)
1315         rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1316     if (t != 0) {
1317         if (!rtlphy->rfpi_enable)
1318             _rtl92c_phy_pi_mode_switch(hw, false);
1319         _rtl92c_phy_reload_adda_registers(hw, adda_reg,
1320                           rtlphy->adda_backup, 16);
1321         _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
1322                          rtlphy->iqk_mac_backup);
1323     }
1324 }
1325 
1326 static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
1327                      s8 delta, bool is2t)
1328 {
1329 }
1330 
1331 static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1332                       bool bmain, bool is2t)
1333 {
1334     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1335 
1336     if (is_hal_stop(rtlhal)) {
1337         rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1338         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1339     }
1340     if (is2t) {
1341         if (bmain)
1342             rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1343                       BIT(5) | BIT(6), 0x1);
1344         else
1345             rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1346                       BIT(5) | BIT(6), 0x2);
1347     } else {
1348         if (bmain)
1349             rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1350         else
1351             rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1352     }
1353 }
1354 
1355 #undef IQK_ADDA_REG_NUM
1356 #undef IQK_DELAY_TIME
1357 
1358 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1359 {
1360     struct rtl_priv *rtlpriv = rtl_priv(hw);
1361     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1362     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1363 
1364     long result[4][8];
1365     u8 i, final_candidate;
1366     bool b_patha_ok, b_pathb_ok;
1367     long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_ec4,
1368         reg_tmp = 0;
1369     bool is12simular, is13simular, is23simular;
1370     u32 iqk_bb_reg[10] = {
1371         ROFDM0_XARXIQIMBALANCE,
1372         ROFDM0_XBRXIQIMBALANCE,
1373         ROFDM0_ECCATHRESHOLD,
1374         ROFDM0_AGCRSSITABLE,
1375         ROFDM0_XATXIQIMBALANCE,
1376         ROFDM0_XBTXIQIMBALANCE,
1377         ROFDM0_XCTXIQIMBALANCE,
1378         ROFDM0_XCTXAFE,
1379         ROFDM0_XDTXAFE,
1380         ROFDM0_RXIQEXTANTA
1381     };
1382 
1383     if (b_recovery) {
1384         _rtl92c_phy_reload_adda_registers(hw,
1385                           iqk_bb_reg,
1386                           rtlphy->iqk_bb_backup, 10);
1387         return;
1388     }
1389     for (i = 0; i < 8; i++) {
1390         result[0][i] = 0;
1391         result[1][i] = 0;
1392         result[2][i] = 0;
1393         result[3][i] = 0;
1394     }
1395     final_candidate = 0xff;
1396     b_patha_ok = false;
1397     b_pathb_ok = false;
1398     is12simular = false;
1399     is23simular = false;
1400     is13simular = false;
1401     for (i = 0; i < 3; i++) {
1402         if (IS_92C_SERIAL(rtlhal->version))
1403             _rtl92c_phy_iq_calibrate(hw, result, i, true);
1404         else
1405             _rtl92c_phy_iq_calibrate(hw, result, i, false);
1406         if (i == 1) {
1407             is12simular = _rtl92c_phy_simularity_compare(hw,
1408                                      result, 0,
1409                                      1);
1410             if (is12simular) {
1411                 final_candidate = 0;
1412                 break;
1413             }
1414         }
1415         if (i == 2) {
1416             is13simular = _rtl92c_phy_simularity_compare(hw,
1417                                      result, 0,
1418                                      2);
1419             if (is13simular) {
1420                 final_candidate = 0;
1421                 break;
1422             }
1423             is23simular = _rtl92c_phy_simularity_compare(hw,
1424                                      result, 1,
1425                                      2);
1426             if (is23simular)
1427                 final_candidate = 1;
1428             else {
1429                 for (i = 0; i < 8; i++)
1430                     reg_tmp += result[3][i];
1431 
1432                 if (reg_tmp != 0)
1433                     final_candidate = 3;
1434                 else
1435                     final_candidate = 0xFF;
1436             }
1437         }
1438     }
1439     for (i = 0; i < 4; i++) {
1440         reg_e94 = result[i][0];
1441         reg_e9c = result[i][1];
1442         reg_ea4 = result[i][2];
1443         reg_eb4 = result[i][4];
1444         reg_ebc = result[i][5];
1445         reg_ec4 = result[i][6];
1446     }
1447     if (final_candidate != 0xff) {
1448         rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1449         rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1450         reg_ea4 = result[final_candidate][2];
1451         rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1452         rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1453         reg_ec4 = result[final_candidate][6];
1454         b_patha_ok = true;
1455         b_pathb_ok = true;
1456     } else {
1457         rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1458         rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1459     }
1460     if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1461         _rtl92c_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
1462                            final_candidate,
1463                            (reg_ea4 == 0));
1464     if (IS_92C_SERIAL(rtlhal->version)) {
1465         if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
1466             _rtl92c_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok,
1467                                result,
1468                                final_candidate,
1469                                (reg_ec4 == 0));
1470     }
1471     _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg,
1472                     rtlphy->iqk_bb_backup, 10);
1473 }
1474 EXPORT_SYMBOL(rtl92c_phy_iq_calibrate);
1475 
1476 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
1477 {
1478     struct rtl_priv *rtlpriv = rtl_priv(hw);
1479     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1480 
1481     if (IS_92C_SERIAL(rtlhal->version))
1482         rtlpriv->cfg->ops->phy_lc_calibrate(hw, true);
1483     else
1484         rtlpriv->cfg->ops->phy_lc_calibrate(hw, false);
1485 }
1486 EXPORT_SYMBOL(rtl92c_phy_lc_calibrate);
1487 
1488 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
1489 {
1490     struct rtl_priv *rtlpriv = rtl_priv(hw);
1491     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1492     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1493 
1494     if (rtlphy->apk_done)
1495         return;
1496     if (IS_92C_SERIAL(rtlhal->version))
1497         _rtl92c_phy_ap_calibrate(hw, delta, true);
1498     else
1499         _rtl92c_phy_ap_calibrate(hw, delta, false);
1500 }
1501 EXPORT_SYMBOL(rtl92c_phy_ap_calibrate);
1502 
1503 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1504 {
1505     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1506 
1507     if (IS_92C_SERIAL(rtlhal->version))
1508         _rtl92c_phy_set_rfpath_switch(hw, bmain, true);
1509     else
1510         _rtl92c_phy_set_rfpath_switch(hw, bmain, false);
1511 }
1512 EXPORT_SYMBOL(rtl92c_phy_set_rfpath_switch);
1513 
1514 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1515 {
1516     struct rtl_priv *rtlpriv = rtl_priv(hw);
1517     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1518     bool postprocessing = false;
1519 
1520     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1521         "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1522         iotype, rtlphy->set_io_inprogress);
1523     do {
1524         switch (iotype) {
1525         case IO_CMD_RESUME_DM_BY_SCAN:
1526             rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1527                 "[IO CMD] Resume DM after scan.\n");
1528             postprocessing = true;
1529             break;
1530         case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1531             rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1532                 "[IO CMD] Pause DM before scan.\n");
1533             postprocessing = true;
1534             break;
1535         default:
1536             rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1537                 "switch case %#x not processed\n", iotype);
1538             break;
1539         }
1540     } while (false);
1541     if (postprocessing && !rtlphy->set_io_inprogress) {
1542         rtlphy->set_io_inprogress = true;
1543         rtlphy->current_io_type = iotype;
1544     } else {
1545         return false;
1546     }
1547     rtl92c_phy_set_io(hw);
1548     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
1549     return true;
1550 }
1551 EXPORT_SYMBOL(rtl92c_phy_set_io_cmd);
1552 
1553 void rtl92c_phy_set_io(struct ieee80211_hw *hw)
1554 {
1555     struct rtl_priv *rtlpriv = rtl_priv(hw);
1556     struct rtl_phy *rtlphy = &(rtlpriv->phy);
1557     struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
1558 
1559     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1560         "--->Cmd(%#x), set_io_inprogress(%d)\n",
1561         rtlphy->current_io_type, rtlphy->set_io_inprogress);
1562     switch (rtlphy->current_io_type) {
1563     case IO_CMD_RESUME_DM_BY_SCAN:
1564         dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1565         rtl92c_dm_write_dig(hw);
1566         rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1567         break;
1568     case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1569         rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
1570         dm_digtable->cur_igvalue = 0x17;
1571         rtl92c_dm_write_dig(hw);
1572         break;
1573     default:
1574         rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1575             "switch case %#x not processed\n",
1576             rtlphy->current_io_type);
1577         break;
1578     }
1579     rtlphy->set_io_inprogress = false;
1580     rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1581         "(%#x)\n", rtlphy->current_io_type);
1582 }
1583 EXPORT_SYMBOL(rtl92c_phy_set_io);
1584 
1585 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw)
1586 {
1587     struct rtl_priv *rtlpriv = rtl_priv(hw);
1588 
1589     rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
1590     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1591     rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1592     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1593     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1594     rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1595 }
1596 EXPORT_SYMBOL(rtl92ce_phy_set_rf_on);
1597 
1598 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw)
1599 {
1600     u32 u4b_tmp;
1601     u8 delay = 5;
1602     struct rtl_priv *rtlpriv = rtl_priv(hw);
1603 
1604     rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1605     rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1606     rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1607     u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1608     while (u4b_tmp != 0 && delay > 0) {
1609         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
1610         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1611         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1612         u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1613         delay--;
1614     }
1615     if (delay == 0) {
1616         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1617         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1618         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1619         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1620         rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
1621             "Switch RF timeout !!!.\n");
1622         return;
1623     }
1624     rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1625     rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
1626 }
1627 EXPORT_SYMBOL(_rtl92c_phy_set_rf_sleep);
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