rtlwifi/rtl8188ee/pwrseq.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2013  Realtek Corporation.*/
0003
0004 #ifndef __RTL8723E_PWRSEQ_H__
0005 #define __RTL8723E_PWRSEQ_H__
0006
0007 #include "../pwrseqcmd.h"
0008 /* Check document WM-20110607-Paul-RTL8188EE_Power_Architecture-R02.vsd
0009  *  There are 6 HW Power States:
0010  *  0: POFF--Power Off
0011  *  1: PDN--Power Down
0012  *  2: CARDEMU--Card Emulation
0013  *  3: ACT--Active Mode
0014  *  4: LPS--Low Power State
0015  *  5: SUS--Suspend
0016  *
0017  *  The transision from different states are defined below
0018  *  TRANS_CARDEMU_TO_ACT
0019  *  TRANS_ACT_TO_CARDEMU
0020  *  TRANS_CARDEMU_TO_SUS
0021  *  TRANS_SUS_TO_CARDEMU
0022  *  TRANS_CARDEMU_TO_PDN
0023  *  TRANS_ACT_TO_LPS
0024  *  TRANS_LPS_TO_ACT
0025  *
0026  *  TRANS_END
0027  *  PWR SEQ Version: rtl8188ee_PwrSeq_V09.h
0028  */
0029
0030 #define RTL8188EE_TRANS_CARDEMU_TO_ACT_STEPS    10
0031 #define RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS    10
0032 #define RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS    10
0033 #define RTL8188EE_TRANS_SUS_TO_CARDEMU_STEPS    10
0034 #define RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS    10
0035 #define RTL8188EE_TRANS_PDN_TO_CARDEMU_STEPS    10
0036 #define RTL8188EE_TRANS_ACT_TO_LPS_STEPS        15
0037 #define RTL8188EE_TRANS_LPS_TO_ACT_STEPS        15
0038 #define RTL8188EE_TRANS_END_STEPS       1
0039
0040 /* The following macros have the following format:
0041  * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
0042  *   comments },
0043  */
0044 #define RTL8188EE_TRANS_CARDEMU_TO_ACT                  \
0045     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0046     PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)       \
0047     /* wait till 0x04[17] = 1    power ready*/},            \
0048     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0049     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0       \
0050     /* 0x02[1:0] = 0    reset BB*/},                \
0051     {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0052     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)         \
0053     /*0x24[23] = 2b'01 schmit trigger */},              \
0054     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0055     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0          \
0056     /* 0x04[15] = 0 disable HWPDN (control by DRV)*/},      \
0057     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0058     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0       \
0059     /*0x04[12:11] = 2b'00 disable WL suspend*/},            \
0060     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0061     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)         \
0062     /*0x04[8] = 1 polling until return 0*/},            \
0063     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0064     PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0            \
0065     /*wait till 0x04[8] = 0*/},                 \
0066     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0067     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0          \
0068     /*LDO normal mode*/},                       \
0069     {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0070     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)         \
0071     /*SDIO Driving*/},
0072
0073 #define RTL8188EE_TRANS_ACT_TO_CARDEMU                  \
0074     {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0075     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0            \
0076     /*0x1F[7:0] = 0 turn off RF*/},                 \
0077     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0078     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)         \
0079     /*LDO Sleep mode*/},                        \
0080     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0081     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)         \
0082     /*0x04[9] = 1 turn off MAC by HW state machine*/},      \
0083     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0084     PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0            \
0085     /*wait till 0x04[9] = 0 polling until return 0 to disable*/},
0086
0087 #define RTL8188EE_TRANS_CARDEMU_TO_SUS                  \
0088     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0089     PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,             \
0090     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)      \
0091     /*0x04[12:11] = 2b'01enable WL suspend*/},          \
0092     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0093     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)   \
0094     /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/},     \
0095     {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0096     PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,             \
0097     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7)           \
0098     /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */},\
0099     {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0100     PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,             \
0101     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0          \
0102     /*Clear SIC_EN register 0x40[12] = 1'b0 */},            \
0103     {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0104     PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,             \
0105     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)         \
0106     /*Set USB suspend enable local register  0xfe10[4]=1 */},   \
0107     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0108     PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)        \
0109     /*Set SDIO suspend local register*/},               \
0110     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0111     PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0           \
0112     /*wait power state to suspend*/},
0113
0114 #define RTL8188EE_TRANS_SUS_TO_CARDEMU                  \
0115     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0116     PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0         \
0117     /*Set SDIO suspend local register*/},               \
0118     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0119     PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)      \
0120     /*wait power state to suspend*/},               \
0121     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0122     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0     \
0123     /*0x04[12:11] = 2b'00 disable WL suspend*/},
0124
0125 #define RTL8188EE_TRANS_CARDEMU_TO_CARDDIS              \
0126     {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0127     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)         \
0128     /*0x24[23] = 2b'01 schmit trigger */},              \
0129     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0130     PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,             \
0131     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)    \
0132     /*0x04[12:11] = 2b'01 enable WL suspend*/},         \
0133     {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0134     PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,             \
0135     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0            \
0136     /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */},\
0137     {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0138     PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,             \
0139     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0          \
0140     /*Clear SIC_EN register 0x40[12] = 1'b0 */},            \
0141     {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
0142     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)         \
0143     /*Set USB suspend enable local register  0xfe10[4]=1 */},   \
0144     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0145     PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)        \
0146     /*Set SDIO suspend local register*/},               \
0147     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0148     PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0           \
0149     /*wait power state to suspend*/},
0150
0151 #define RTL8188EE_TRANS_CARDDIS_TO_CARDEMU              \
0152     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0153     PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0         \
0154     /*Set SDIO suspend local register*/},               \
0155     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0156     PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)      \
0157     /*wait power state to suspend*/},               \
0158     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0159     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0       \
0160     /*0x04[12:11] = 2b'00 disable WL suspend*/},
0161
0162 #define RTL8188EE_TRANS_CARDEMU_TO_PDN                  \
0163     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0164     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0/* 0x04[16] = 0*/},   \
0165     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0166     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)         \
0167     /* 0x04[15] = 1*/},
0168
0169 #define RTL8188EE_TRANS_PDN_TO_CARDEMU                  \
0170     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0171     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0/* 0x04[15] = 0*/},
0172
0173 #define RTL8188EE_TRANS_ACT_TO_LPS                  \
0174     {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0175     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F         \
0176     /*Tx Pause*/},                          \
0177     {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0178     PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0          \
0179     /*Should be zero if no packet is transmitting*/},       \
0180     {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0181     PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0          \
0182     /*Should be zero if no packet is transmitting*/},       \
0183     {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0184     PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0          \
0185     /*Should be zero if no packet is transmitting*/},       \
0186     {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0187     PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0          \
0188     /*Should be zero if no packet is transmitting*/},       \
0189     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0190     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0          \
0191     /*CCK and OFDM are disabled,and clock are gated*/},     \
0192     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0193     PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US     \
0194     /*Delay 1us*/},                         \
0195     {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0196     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F         \
0197     /*Reset MAC TRX*/},                     \
0198     {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0199     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0          \
0200     /*check if removed later*/},                    \
0201     {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0202     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)         \
0203     /*Respond TxOK to scheduler*/},
0204
0205
0206 #define RTL8188EE_TRANS_LPS_TO_ACT                  \
0207     {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
0208     PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84            \
0209     /*SDIO RPWM*/},                         \
0210     {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
0211     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84         \
0212     /*USB RPWM*/},                          \
0213     {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
0214     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84         \
0215     /*PCIe RPWM*/},                         \
0216     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0217     PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS     \
0218     /*Delay*/},                         \
0219     {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0220     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0          \
0221     /*. 0x08[4] = 0      switch TSF to 40M*/},      \
0222     {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0223     PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0            \
0224     /*Polling 0x109[7]=0  TSF in 40M*/},                \
0225     {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0226     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0       \
0227     /*. 0x29[7:6] = 2b'00    enable BB clock*/},        \
0228     {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0229     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)         \
0230     /*. 0x101[1] = 1*/},                    \
0231     {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0232     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF         \
0233     /*. 0x100[7:0] = 0xFF    enable WMAC TRX*/},        \
0234     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0235     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)   \
0236     /*. 0x02[1:0] = 2b'11    enable BB macro*/},        \
0237     {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
0238     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0            \
0239     /*. 0x522 = 0*/},
0240
0241 #define RTL8188EE_TRANS_END     \
0242     {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0243     0, PWR_CMD_END, 0, 0}
0244
0245 extern struct wlan_pwr_cfg rtl8188ee_power_on_flow
0246         [RTL8188EE_TRANS_CARDEMU_TO_ACT_STEPS +
0247          RTL8188EE_TRANS_END_STEPS];
0248 extern struct wlan_pwr_cfg rtl8188ee_radio_off_flow
0249         [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
0250          RTL8188EE_TRANS_END_STEPS];
0251 extern struct wlan_pwr_cfg rtl8188ee_card_disable_flow
0252         [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
0253          RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
0254          RTL8188EE_TRANS_END_STEPS];
0255 extern struct wlan_pwr_cfg rtl8188ee_card_enable_flow
0256         [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
0257          RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
0258          RTL8188EE_TRANS_END_STEPS];
0259 extern struct wlan_pwr_cfg rtl8188ee_suspend_flow
0260         [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
0261          RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS +
0262          RTL8188EE_TRANS_END_STEPS];
0263 extern struct wlan_pwr_cfg rtl8188ee_resume_flow
0264         [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
0265          RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS +
0266          RTL8188EE_TRANS_END_STEPS];
0267 extern struct wlan_pwr_cfg rtl8188ee_hwpdn_flow
0268         [RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
0269          RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
0270          RTL8188EE_TRANS_END_STEPS];
0271 extern struct wlan_pwr_cfg rtl8188ee_enter_lps_flow
0272         [RTL8188EE_TRANS_ACT_TO_LPS_STEPS +
0273          RTL8188EE_TRANS_END_STEPS];
0274 extern struct wlan_pwr_cfg rtl8188ee_leave_lps_flow
0275         [RTL8188EE_TRANS_LPS_TO_ACT_STEPS +
0276          RTL8188EE_TRANS_END_STEPS];
0277
0278 /* RTL8723 Power Configuration CMDs for PCIe interface */
0279 #define RTL8188EE_NIC_PWR_ON_FLOW   rtl8188ee_power_on_flow
0280 #define RTL8188EE_NIC_RF_OFF_FLOW   rtl8188ee_radio_off_flow
0281 #define RTL8188EE_NIC_DISABLE_FLOW  rtl8188ee_card_disable_flow
0282 #define RTL8188EE_NIC_ENABLE_FLOW   rtl8188ee_card_enable_flow
0283 #define RTL8188EE_NIC_SUSPEND_FLOW  rtl8188ee_suspend_flow
0284 #define RTL8188EE_NIC_RESUME_FLOW   rtl8188ee_resume_flow
0285 #define RTL8188EE_NIC_PDN_FLOW      rtl8188ee_hwpdn_flow
0286 #define RTL8188EE_NIC_LPS_ENTER_FLOW    rtl8188ee_enter_lps_flow
0287 #define RTL8188EE_NIC_LPS_LEAVE_FLOW    rtl8188ee_leave_lps_flow
0288
0289 #endif