rtlwifi/rtl8188ee/phy.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2013  Realtek Corporation.*/
0003
0004 #ifndef __RTL92C_PHY_H__
0005 #define __RTL92C_PHY_H__
0006
0007 /* MAX_TX_COUNT must always set to 4, otherwise read efuse
0008  * table secquence will be wrong.
0009  */
0010 #define     MAX_TX_COUNT                4
0011
0012 #define MAX_PRECMD_CNT              16
0013 #define MAX_RFDEPENDCMD_CNT     16
0014 #define MAX_POSTCMD_CNT             16
0015
0016 #define MAX_DOZE_WAITING_TIMES_9x   64
0017
0018 #define RT_CANNOT_IO(hw)            false
0019 #define HIGHPOWER_RADIOA_ARRAYLEN   22
0020
0021 #define IQK_ADDA_REG_NUM            16
0022 #define IQK_BB_REG_NUM              9
0023 #define MAX_TOLERANCE               5
0024 #define IQK_DELAY_TIME              10
0025 #define INDEX_MAPPING_NUM   15
0026
0027 #define APK_BB_REG_NUM              5
0028 #define APK_AFE_REG_NUM             16
0029 #define APK_CURVE_REG_NUM           4
0030 #define PATH_NUM                    2
0031
0032 #define LOOP_LIMIT                  5
0033 #define MAX_STALL_TIME              50
0034 #define ANTENNADIVERSITYVALUE       0x80
0035 #define MAX_TXPWR_IDX_NMODE_92S     63
0036 #define RESET_CNT_LIMIT             3
0037
0038 #define IQK_ADDA_REG_NUM            16
0039 #define IQK_MAC_REG_NUM             4
0040
0041 #define RF6052_MAX_PATH             2
0042
0043 #define CT_OFFSET_MAC_ADDR          0X16
0044
0045 #define CT_OFFSET_CCK_TX_PWR_IDX            0x5A
0046 #define CT_OFFSET_HT401S_TX_PWR_IDX         0x60
0047 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF    0x66
0048 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF      0x69
0049 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF      0x6C
0050
0051 #define CT_OFFSET_HT40_MAX_PWR_OFFSET       0x6F
0052 #define CT_OFFSET_HT20_MAX_PWR_OFFSET       0x72
0053
0054 #define CT_OFFSET_CHANNEL_PLAH              0x75
0055 #define CT_OFFSET_THERMAL_METER             0x78
0056 #define CT_OFFSET_RF_OPTION                 0x79
0057 #define CT_OFFSET_VERSION                   0x7E
0058 #define CT_OFFSET_CUSTOMER_ID               0x7F
0059
0060 #define RTL92C_MAX_PATH_NUM                 2
0061
0062 enum swchnlcmd_id {
0063     CMDID_END,
0064     CMDID_SET_TXPOWEROWER_LEVEL,
0065     CMDID_BBREGWRITE10,
0066     CMDID_WRITEPORT_ULONG,
0067     CMDID_WRITEPORT_USHORT,
0068     CMDID_WRITEPORT_UCHAR,
0069     CMDID_RF_WRITEREG,
0070 };
0071
0072 struct swchnlcmd {
0073     enum swchnlcmd_id cmdid;
0074     u32 para1;
0075     u32 para2;
0076     u32 msdelay;
0077 };
0078
0079 enum hw90_block_e {
0080     HW90_BLOCK_MAC = 0,
0081     HW90_BLOCK_PHY0 = 1,
0082     HW90_BLOCK_PHY1 = 2,
0083     HW90_BLOCK_RF = 3,
0084     HW90_BLOCK_MAXIMUM = 4,
0085 };
0086
0087 enum baseband_config_type {
0088     BASEBAND_CONFIG_PHY_REG = 0,
0089     BASEBAND_CONFIG_AGC_TAB = 1,
0090 };
0091
0092 enum ra_offset_area {
0093     RA_OFFSET_LEGACY_OFDM1,
0094     RA_OFFSET_LEGACY_OFDM2,
0095     RA_OFFSET_HT_OFDM1,
0096     RA_OFFSET_HT_OFDM2,
0097     RA_OFFSET_HT_OFDM3,
0098     RA_OFFSET_HT_OFDM4,
0099     RA_OFFSET_HT_CCK,
0100 };
0101
0102 enum antenna_path {
0103     ANTENNA_NONE,
0104     ANTENNA_D,
0105     ANTENNA_C,
0106     ANTENNA_CD,
0107     ANTENNA_B,
0108     ANTENNA_BD,
0109     ANTENNA_BC,
0110     ANTENNA_BCD,
0111     ANTENNA_A,
0112     ANTENNA_AD,
0113     ANTENNA_AC,
0114     ANTENNA_ACD,
0115     ANTENNA_AB,
0116     ANTENNA_ABD,
0117     ANTENNA_ABC,
0118     ANTENNA_ABCD
0119 };
0120
0121 struct r_antenna_select_ofdm {
0122     u32 r_tx_antenna:4;
0123     u32 r_ant_l:4;
0124     u32 r_ant_non_ht:4;
0125     u32 r_ant_ht1:4;
0126     u32 r_ant_ht2:4;
0127     u32 r_ant_ht_s1:4;
0128     u32 r_ant_non_ht_s1:4;
0129     u32 ofdm_txsc:2;
0130     u32 reserved:2;
0131 };
0132
0133 struct r_antenna_select_cck {
0134     u8 r_cckrx_enable_2:2;
0135     u8 r_cckrx_enable:2;
0136     u8 r_ccktx_enable:4;
0137 };
0138
0139 struct efuse_contents {
0140     u8 mac_addr[ETH_ALEN];
0141     u8 cck_tx_power_idx[6];
0142     u8 ht40_1s_tx_power_idx[6];
0143     u8 ht40_2s_tx_power_idx_diff[3];
0144     u8 ht20_tx_power_idx_diff[3];
0145     u8 ofdm_tx_power_idx_diff[3];
0146     u8 ht40_max_power_offset[3];
0147     u8 ht20_max_power_offset[3];
0148     u8 channel_plan;
0149     u8 thermal_meter;
0150     u8 rf_option[5];
0151     u8 version;
0152     u8 oem_id;
0153     u8 regulatory;
0154 };
0155
0156 struct tx_power_struct {
0157     u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0158     u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0159     u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0160     u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0161     u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0162     u8 legacy_ht_txpowerdiff;
0163     u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0164     u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
0165     u8 pwrgroup_cnt;
0166     u32 mcs_original_offset[4][16];
0167 };
0168
0169 enum _ANT_DIV_TYPE {
0170     NO_ANTDIV               = 0xFF,
0171     CG_TRX_HW_ANTDIV        = 0x01,
0172     CGCS_RX_HW_ANTDIV       = 0x02,
0173     FIXED_HW_ANTDIV         = 0x03,
0174     CG_TRX_SMART_ANTDIV     = 0x04,
0175     CGCS_RX_SW_ANTDIV       = 0x05,
0176 };
0177
0178 u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw,
0179                 u32 regaddr, u32 bitmask);
0180 void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw,
0181                u32 regaddr, u32 bitmask, u32 data);
0182 u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw,
0183                 enum radio_path rfpath, u32 regaddr,
0184                 u32 bitmask);
0185 void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw,
0186                enum radio_path rfpath, u32 regaddr,
0187                u32 bitmask, u32 data);
0188 bool rtl88e_phy_mac_config(struct ieee80211_hw *hw);
0189 bool rtl88e_phy_bb_config(struct ieee80211_hw *hw);
0190 bool rtl88e_phy_rf_config(struct ieee80211_hw *hw);
0191 void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
0192 void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw,
0193                   long *powerlevel);
0194 void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
0195 void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw,
0196                       u8 operation);
0197 void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
0198 void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
0199                 enum nl80211_channel_type ch_type);
0200 void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw);
0201 u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw);
0202 void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
0203 void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw);
0204 void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
0205 bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
0206                       enum radio_path rfpath);
0207 bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
0208 bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw,
0209                    enum rf_pwrstate rfpwr_state);
0210
0211 #endif