realtek/rtlwifi/pci.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003
0004 #ifndef __RTL_PCI_H__
0005 #define __RTL_PCI_H__
0006
0007 #include <linux/pci.h>
0008 /* 1: MSDU packet queue,
0009  * 2: Rx Command Queue
0010  */
0011 #define RTL_PCI_RX_MPDU_QUEUE           0
0012 #define RTL_PCI_RX_CMD_QUEUE            1
0013 #define RTL_PCI_MAX_RX_QUEUE            2
0014
0015 #define RTL_PCI_MAX_RX_COUNT            512/*64*/
0016 #define RTL_PCI_MAX_TX_QUEUE_COUNT      9
0017
0018 #define RT_TXDESC_NUM               128
0019 #define TX_DESC_NUM_92E             512
0020 #define TX_DESC_NUM_8822B           512
0021 #define RT_TXDESC_NUM_BE_QUEUE          256
0022
0023 #define BK_QUEUE                0
0024 #define BE_QUEUE                1
0025 #define VI_QUEUE                2
0026 #define VO_QUEUE                3
0027 #define BEACON_QUEUE                4
0028 #define TXCMD_QUEUE             5
0029 #define MGNT_QUEUE              6
0030 #define HIGH_QUEUE              7
0031 #define HCCA_QUEUE              8
0032 #define H2C_QUEUE               TXCMD_QUEUE /* In 8822B */
0033
0034 #define RTL_PCI_DEVICE(vend, dev, cfg)  \
0035     .vendor = (vend), \
0036     .device = (dev), \
0037     .subvendor = PCI_ANY_ID, \
0038     .subdevice = PCI_ANY_ID,\
0039     .driver_data = (kernel_ulong_t)&(cfg)
0040
0041 #define INTEL_VENDOR_ID             0x8086
0042 #define SIS_VENDOR_ID               0x1039
0043 #define ATI_VENDOR_ID               0x1002
0044 #define ATI_DEVICE_ID               0x7914
0045 #define AMD_VENDOR_ID               0x1022
0046
0047 #define PCI_MAX_BRIDGE_NUMBER           255
0048 #define PCI_MAX_DEVICES             32
0049 #define PCI_MAX_FUNCTION            8
0050
0051 #define PCI_CONF_ADDRESS    0x0CF8  /*PCI Configuration Space Address */
0052 #define PCI_CONF_DATA       0x0CFC  /*PCI Configuration Space Data */
0053
0054 #define PCI_CLASS_BRIDGE_DEV        0x06
0055 #define PCI_SUBCLASS_BR_PCI_TO_PCI  0x04
0056 #define PCI_CAPABILITY_ID_PCI_EXPRESS   0x10
0057 #define PCI_CAP_ID_EXP          0x10
0058
0059 #define U1DONTCARE          0xFF
0060 #define U2DONTCARE          0xFFFF
0061 #define U4DONTCARE          0xFFFFFFFF
0062
0063 #define RTL_PCI_8192_DID    0x8192  /*8192 PCI-E */
0064 #define RTL_PCI_8192SE_DID  0x8192  /*8192 SE */
0065 #define RTL_PCI_8174_DID    0x8174  /*8192 SE */
0066 #define RTL_PCI_8173_DID    0x8173  /*8191 SE Crab */
0067 #define RTL_PCI_8172_DID    0x8172  /*8191 SE RE */
0068 #define RTL_PCI_8171_DID    0x8171  /*8191 SE Unicron */
0069 #define RTL_PCI_8723AE_DID  0x8723  /*8723AE */
0070 #define RTL_PCI_0045_DID    0x0045  /*8190 PCI for Ceraga */
0071 #define RTL_PCI_0046_DID    0x0046  /*8190 Cardbus for Ceraga */
0072 #define RTL_PCI_0044_DID    0x0044  /*8192e PCIE for Ceraga */
0073 #define RTL_PCI_0047_DID    0x0047  /*8192e Express Card for Ceraga */
0074 #define RTL_PCI_700F_DID    0x700F
0075 #define RTL_PCI_701F_DID    0x701F
0076 #define RTL_PCI_DLINK_DID   0x3304
0077 #define RTL_PCI_8723AE_DID  0x8723  /*8723e */
0078 #define RTL_PCI_8192CET_DID 0x8191  /*8192ce */
0079 #define RTL_PCI_8192CE_DID  0x8178  /*8192ce */
0080 #define RTL_PCI_8191CE_DID  0x8177  /*8192ce */
0081 #define RTL_PCI_8188CE_DID  0x8176  /*8192ce */
0082 #define RTL_PCI_8192CU_DID  0x8191  /*8192ce */
0083 #define RTL_PCI_8192DE_DID  0x8193  /*8192de */
0084 #define RTL_PCI_8192DE_DID2 0x002B  /*92DE*/
0085 #define RTL_PCI_8188EE_DID  0x8179  /*8188ee*/
0086 #define RTL_PCI_8723BE_DID  0xB723  /*8723be*/
0087 #define RTL_PCI_8192EE_DID  0x818B  /*8192ee*/
0088 #define RTL_PCI_8821AE_DID  0x8821  /*8821ae*/
0089 #define RTL_PCI_8812AE_DID  0x8812  /*8812ae*/
0090 #define RTL_PCI_8822BE_DID  0xB822  /*8822be*/
0091
0092 /*8192 support 16 pages of IO registers*/
0093 #define RTL_MEM_MAPPED_IO_RANGE_8190PCI     0x1000
0094 #define RTL_MEM_MAPPED_IO_RANGE_8192PCIE    0x4000
0095 #define RTL_MEM_MAPPED_IO_RANGE_8192SE      0x4000
0096 #define RTL_MEM_MAPPED_IO_RANGE_8192CE      0x4000
0097 #define RTL_MEM_MAPPED_IO_RANGE_8192DE      0x4000
0098
0099 #define RTL_PCI_REVISION_ID_8190PCI     0x00
0100 #define RTL_PCI_REVISION_ID_8192PCIE        0x01
0101 #define RTL_PCI_REVISION_ID_8192SE      0x10
0102 #define RTL_PCI_REVISION_ID_8192CE      0x1
0103 #define RTL_PCI_REVISION_ID_8192DE      0x0
0104
0105 #define RTL_DEFAULT_HARDWARE_TYPE   HARDWARE_TYPE_RTL8192CE
0106
0107 enum pci_bridge_vendor {
0108     PCI_BRIDGE_VENDOR_INTEL = 0x0,  /*0b'0000,0001 */
0109     PCI_BRIDGE_VENDOR_ATI,      /*0b'0000,0010*/
0110     PCI_BRIDGE_VENDOR_AMD,      /*0b'0000,0100*/
0111     PCI_BRIDGE_VENDOR_SIS,      /*0b'0000,1000*/
0112     PCI_BRIDGE_VENDOR_UNKNOWN,  /*0b'0100,0000*/
0113     PCI_BRIDGE_VENDOR_MAX,
0114 };
0115
0116 struct rtl_pci_capabilities_header {
0117     u8 capability_id;
0118     u8 next;
0119 };
0120
0121 /* In new TRX flow, Buffer_desc is new concept
0122  * But TX wifi info == TX descriptor in old flow
0123  * RX wifi info == RX descriptor in old flow
0124  */
0125 struct rtl_tx_buffer_desc {
0126     u32 dword[4 * (1 << (BUFDESC_SEG_NUM + 1))];
0127 } __packed;
0128
0129 struct rtl_tx_desc {
0130     u32 dword[16];
0131 } __packed;
0132
0133 struct rtl_rx_buffer_desc { /*rx buffer desc*/
0134     u32 dword[4];
0135 } __packed;
0136
0137 struct rtl_rx_desc { /*old: rx desc new: rx wifi info*/
0138     u32 dword[8];
0139 } __packed;
0140
0141 struct rtl_tx_cmd_desc {
0142     u32 dword[16];
0143 } __packed;
0144
0145 struct rtl8192_tx_ring {
0146     struct rtl_tx_desc *desc;
0147     dma_addr_t dma;
0148     unsigned int idx;
0149     unsigned int entries;
0150     struct sk_buff_head queue;
0151     /*add for new trx flow*/
0152     struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
0153     dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/
0154     u16 cur_tx_wp; /* current_tx_write_point */
0155     u16 cur_tx_rp; /* current_tx_read_point */
0156 };
0157
0158 struct rtl8192_rx_ring {
0159     struct rtl_rx_desc *desc;
0160     dma_addr_t dma;
0161     unsigned int idx;
0162     struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
0163     /*add for new trx flow*/
0164     struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/
0165     u16 next_rx_rp; /* next_rx_read_point */
0166 };
0167
0168 struct rtl_pci {
0169     struct pci_dev *pdev;
0170     bool irq_enabled;
0171
0172     bool driver_is_goingto_unload;
0173     bool up_first_time;
0174     bool first_init;
0175     bool being_init_adapter;
0176     bool init_ready;
0177
0178     /*Tx */
0179     struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
0180     int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
0181     u32 transmit_config;
0182
0183     /*Rx */
0184     struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
0185     int rxringcount;
0186     u16 rxbuffersize;
0187     u32 receive_config;
0188
0189     /*irq */
0190     u8 irq_alloc;
0191     u32 irq_mask[4];    /* 0-1: normal, 2: unused, 3: h2c */
0192     u32 sys_irq_mask;
0193
0194     /*Bcn control register setting */
0195     u32 reg_bcn_ctrl_val;
0196
0197      /*ASPM*/ u8 const_pci_aspm;
0198     u8 const_amdpci_aspm;
0199     u8 const_hwsw_rfoff_d3;
0200     u8 const_support_pciaspm;
0201     /*pci-e bridge */
0202     u8 const_hostpci_aspm_setting;
0203     /*pci-e device */
0204     u8 const_devicepci_aspm_setting;
0205     /* If it supports ASPM, Offset[560h] = 0x40,
0206      * otherwise Offset[560h] = 0x00.
0207      */
0208     bool support_aspm;
0209     bool support_backdoor;
0210
0211     /*QOS & EDCA */
0212     enum acm_method acm_method;
0213
0214     u16 shortretry_limit;
0215     u16 longretry_limit;
0216
0217     /* MSI support */
0218     bool msi_support;
0219     bool using_msi;
0220     /* interrupt clear before set */
0221     bool int_clear;
0222 };
0223
0224 struct mp_adapter {
0225     u8 linkctrl_reg;
0226
0227     u8 busnumber;
0228     u8 devnumber;
0229     u8 funcnumber;
0230
0231     u8 pcibridge_busnum;
0232     u8 pcibridge_devnum;
0233     u8 pcibridge_funcnum;
0234
0235     u8 pcibridge_vendor;
0236     u16 pcibridge_vendorid;
0237     u16 pcibridge_deviceid;
0238
0239     u8 num4bytes;
0240
0241     u8 pcibridge_pciehdr_offset;
0242     u8 pcibridge_linkctrlreg;
0243
0244     bool amd_l1_patch;
0245 };
0246
0247 struct rtl_pci_priv {
0248     struct bt_coexist_info bt_coexist;
0249     struct rtl_led_ctl ledctl;
0250     struct rtl_pci dev;
0251     struct mp_adapter ndis_adapter;
0252 };
0253
0254 #define rtl_pcipriv(hw)     (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
0255 #define rtl_pcidev(pcipriv) (&((pcipriv)->dev))
0256
0257 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
0258
0259 extern const struct rtl_intf_ops rtl_pci_ops;
0260
0261 int rtl_pci_probe(struct pci_dev *pdev,
0262           const struct pci_device_id *id);
0263 void rtl_pci_disconnect(struct pci_dev *pdev);
0264 #ifdef CONFIG_PM_SLEEP
0265 int rtl_pci_suspend(struct device *dev);
0266 int rtl_pci_resume(struct device *dev);
0267 #endif /* CONFIG_PM_SLEEP */
0268 static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
0269 {
0270     return readb((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
0271 }
0272
0273 static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
0274 {
0275     return readw((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
0276 }
0277
0278 static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
0279 {
0280     return readl((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
0281 }
0282
0283 static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
0284 {
0285     writeb(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
0286 }
0287
0288 static inline void pci_write16_async(struct rtl_priv *rtlpriv,
0289                      u32 addr, u16 val)
0290 {
0291     writew(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
0292 }
0293
0294 static inline void pci_write32_async(struct rtl_priv *rtlpriv,
0295                      u32 addr, u32 val)
0296 {
0297     writel(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
0298 }
0299
0300 static inline u16 calc_fifo_space(u16 rp, u16 wp, u16 size)
0301 {
0302     if (rp <= wp)
0303         return size - 1 + rp - wp;
0304     return rp - wp - 1;
0305 }
0306
0307 #endif