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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003 
0004 #include "wifi.h"
0005 #include "core.h"
0006 #include "pci.h"
0007 #include "base.h"
0008 #include "ps.h"
0009 #include "efuse.h"
0010 #include <linux/interrupt.h>
0011 #include <linux/export.h>
0012 #include <linux/module.h>
0013 
0014 MODULE_AUTHOR("lizhaoming   <chaoming_li@realsil.com.cn>");
0015 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
0016 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
0017 MODULE_LICENSE("GPL");
0018 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
0019 
0020 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
0021     INTEL_VENDOR_ID,
0022     ATI_VENDOR_ID,
0023     AMD_VENDOR_ID,
0024     SIS_VENDOR_ID
0025 };
0026 
0027 static const u8 ac_to_hwq[] = {
0028     VO_QUEUE,
0029     VI_QUEUE,
0030     BE_QUEUE,
0031     BK_QUEUE
0032 };
0033 
0034 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
0035 {
0036     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0037     __le16 fc = rtl_get_fc(skb);
0038     u8 queue_index = skb_get_queue_mapping(skb);
0039     struct ieee80211_hdr *hdr;
0040 
0041     if (unlikely(ieee80211_is_beacon(fc)))
0042         return BEACON_QUEUE;
0043     if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
0044         return MGNT_QUEUE;
0045     if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
0046         if (ieee80211_is_nullfunc(fc))
0047             return HIGH_QUEUE;
0048     if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
0049         hdr = rtl_get_hdr(skb);
0050 
0051         if (is_multicast_ether_addr(hdr->addr1) ||
0052             is_broadcast_ether_addr(hdr->addr1))
0053             return HIGH_QUEUE;
0054     }
0055 
0056     return ac_to_hwq[queue_index];
0057 }
0058 
0059 /* Update PCI dependent default settings*/
0060 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
0061 {
0062     struct rtl_priv *rtlpriv = rtl_priv(hw);
0063     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
0064     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
0065     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0066     u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0067     u8 init_aspm;
0068 
0069     ppsc->reg_rfps_level = 0;
0070     ppsc->support_aspm = false;
0071 
0072     /*Update PCI ASPM setting */
0073     ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
0074     switch (rtlpci->const_pci_aspm) {
0075     case 0:
0076         /*No ASPM */
0077         break;
0078 
0079     case 1:
0080         /*ASPM dynamically enabled/disable. */
0081         ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
0082         break;
0083 
0084     case 2:
0085         /*ASPM with Clock Req dynamically enabled/disable. */
0086         ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
0087                      RT_RF_OFF_LEVL_CLK_REQ);
0088         break;
0089 
0090     case 3:
0091         /* Always enable ASPM and Clock Req
0092          * from initialization to halt.
0093          */
0094         ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
0095         ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
0096                      RT_RF_OFF_LEVL_CLK_REQ);
0097         break;
0098 
0099     case 4:
0100         /* Always enable ASPM without Clock Req
0101          * from initialization to halt.
0102          */
0103         ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
0104                       RT_RF_OFF_LEVL_CLK_REQ);
0105         ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
0106         break;
0107     }
0108 
0109     ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
0110 
0111     /*Update Radio OFF setting */
0112     switch (rtlpci->const_hwsw_rfoff_d3) {
0113     case 1:
0114         if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
0115             ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
0116         break;
0117 
0118     case 2:
0119         if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
0120             ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
0121         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
0122         break;
0123 
0124     case 3:
0125         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
0126         break;
0127     }
0128 
0129     /*Set HW definition to determine if it supports ASPM. */
0130     switch (rtlpci->const_support_pciaspm) {
0131     case 0:
0132         /*Not support ASPM. */
0133         ppsc->support_aspm = false;
0134         break;
0135     case 1:
0136         /*Support ASPM. */
0137         ppsc->support_aspm = true;
0138         ppsc->support_backdoor = true;
0139         break;
0140     case 2:
0141         /*ASPM value set by chipset. */
0142         if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
0143             ppsc->support_aspm = true;
0144         break;
0145     default:
0146         pr_err("switch case %#x not processed\n",
0147                rtlpci->const_support_pciaspm);
0148         break;
0149     }
0150 
0151     /* toshiba aspm issue, toshiba will set aspm selfly
0152      * so we should not set aspm in driver
0153      */
0154     pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
0155     if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
0156         init_aspm == 0x43)
0157         ppsc->support_aspm = false;
0158 }
0159 
0160 static bool _rtl_pci_platform_switch_device_pci_aspm(
0161             struct ieee80211_hw *hw,
0162             u8 value)
0163 {
0164     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0165     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0166 
0167     if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
0168         value |= 0x40;
0169 
0170     pci_write_config_byte(rtlpci->pdev, 0x80, value);
0171 
0172     return false;
0173 }
0174 
0175 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
0176 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
0177 {
0178     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0179     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0180 
0181     pci_write_config_byte(rtlpci->pdev, 0x81, value);
0182 
0183     if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
0184         udelay(100);
0185 }
0186 
0187 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
0188 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
0189 {
0190     struct rtl_priv *rtlpriv = rtl_priv(hw);
0191     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
0192     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
0193     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0194     u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0195     u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
0196     /*Retrieve original configuration settings. */
0197     u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
0198     u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
0199                 pcibridge_linkctrlreg;
0200     u16 aspmlevel = 0;
0201     u8 tmp_u1b = 0;
0202 
0203     if (!ppsc->support_aspm)
0204         return;
0205 
0206     if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
0207         rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
0208             "PCI(Bridge) UNKNOWN\n");
0209 
0210         return;
0211     }
0212 
0213     if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
0214         RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
0215         _rtl_pci_switch_clk_req(hw, 0x0);
0216     }
0217 
0218     /*for promising device will in L0 state after an I/O. */
0219     pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
0220 
0221     /*Set corresponding value. */
0222     aspmlevel |= BIT(0) | BIT(1);
0223     linkctrl_reg &= ~aspmlevel;
0224     pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
0225 
0226     _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
0227     udelay(50);
0228 
0229     /*4 Disable Pci Bridge ASPM */
0230     pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
0231                   pcibridge_linkctrlreg);
0232 
0233     udelay(50);
0234 }
0235 
0236 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
0237  *power saving We should follow the sequence to enable
0238  *RTL8192SE first then enable Pci Bridge ASPM
0239  *or the system will show bluescreen.
0240  */
0241 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
0242 {
0243     struct rtl_priv *rtlpriv = rtl_priv(hw);
0244     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
0245     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
0246     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0247     u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0248     u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
0249     u16 aspmlevel;
0250     u8 u_pcibridge_aspmsetting;
0251     u8 u_device_aspmsetting;
0252 
0253     if (!ppsc->support_aspm)
0254         return;
0255 
0256     if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
0257         rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
0258             "PCI(Bridge) UNKNOWN\n");
0259         return;
0260     }
0261 
0262     /*4 Enable Pci Bridge ASPM */
0263 
0264     u_pcibridge_aspmsetting =
0265         pcipriv->ndis_adapter.pcibridge_linkctrlreg |
0266         rtlpci->const_hostpci_aspm_setting;
0267 
0268     if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
0269         u_pcibridge_aspmsetting &= ~BIT(0);
0270 
0271     pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
0272                   u_pcibridge_aspmsetting);
0273 
0274     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0275         "PlatformEnableASPM(): Write reg[%x] = %x\n",
0276         (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
0277         u_pcibridge_aspmsetting);
0278 
0279     udelay(50);
0280 
0281     /*Get ASPM level (with/without Clock Req) */
0282     aspmlevel = rtlpci->const_devicepci_aspm_setting;
0283     u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
0284 
0285     /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
0286     /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
0287 
0288     u_device_aspmsetting |= aspmlevel;
0289 
0290     _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
0291 
0292     if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
0293         _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
0294                          RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
0295         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
0296     }
0297     udelay(100);
0298 }
0299 
0300 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
0301 {
0302     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0303 
0304     bool status = false;
0305     u8 offset_e0;
0306     unsigned int offset_e4;
0307 
0308     pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
0309 
0310     pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
0311 
0312     if (offset_e0 == 0xA0) {
0313         pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
0314         if (offset_e4 & BIT(23))
0315             status = true;
0316     }
0317 
0318     return status;
0319 }
0320 
0321 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
0322                      struct rtl_priv **buddy_priv)
0323 {
0324     struct rtl_priv *rtlpriv = rtl_priv(hw);
0325     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
0326     struct rtl_priv *tpriv = NULL, *iter;
0327     struct rtl_pci_priv *tpcipriv = NULL;
0328 
0329     if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
0330         list_for_each_entry(iter, &rtlpriv->glb_var->glb_priv_list,
0331                     list) {
0332             tpcipriv = (struct rtl_pci_priv *)iter->priv;
0333             rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0334                 "pcipriv->ndis_adapter.funcnumber %x\n",
0335                 pcipriv->ndis_adapter.funcnumber);
0336             rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0337                 "tpcipriv->ndis_adapter.funcnumber %x\n",
0338                 tpcipriv->ndis_adapter.funcnumber);
0339 
0340             if (pcipriv->ndis_adapter.busnumber ==
0341                 tpcipriv->ndis_adapter.busnumber &&
0342                 pcipriv->ndis_adapter.devnumber ==
0343                 tpcipriv->ndis_adapter.devnumber &&
0344                 pcipriv->ndis_adapter.funcnumber !=
0345                 tpcipriv->ndis_adapter.funcnumber) {
0346                 tpriv = iter;
0347                 break;
0348             }
0349         }
0350     }
0351 
0352     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
0353         "find_buddy_priv %d\n", tpriv != NULL);
0354 
0355     if (tpriv)
0356         *buddy_priv = tpriv;
0357 
0358     return tpriv != NULL;
0359 }
0360 
0361 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
0362 {
0363     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
0364     struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
0365     u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
0366     u8 linkctrl_reg;
0367     u8 num4bbytes;
0368 
0369     num4bbytes = (capabilityoffset + 0x10) / 4;
0370 
0371     /*Read  Link Control Register */
0372     pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
0373 
0374     pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
0375 }
0376 
0377 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
0378                     struct ieee80211_hw *hw)
0379 {
0380     struct rtl_priv *rtlpriv = rtl_priv(hw);
0381     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
0382 
0383     u8 tmp;
0384     u16 linkctrl_reg;
0385 
0386     /*Link Control Register */
0387     pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
0388     pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
0389 
0390     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
0391         pcipriv->ndis_adapter.linkctrl_reg);
0392 
0393     pci_read_config_byte(pdev, 0x98, &tmp);
0394     tmp |= BIT(4);
0395     pci_write_config_byte(pdev, 0x98, tmp);
0396 
0397     tmp = 0x17;
0398     pci_write_config_byte(pdev, 0x70f, tmp);
0399 }
0400 
0401 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
0402 {
0403     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
0404 
0405     _rtl_pci_update_default_setting(hw);
0406 
0407     if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
0408         /*Always enable ASPM & Clock Req. */
0409         rtl_pci_enable_aspm(hw);
0410         RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
0411     }
0412 }
0413 
0414 static void _rtl_pci_io_handler_init(struct device *dev,
0415                      struct ieee80211_hw *hw)
0416 {
0417     struct rtl_priv *rtlpriv = rtl_priv(hw);
0418 
0419     rtlpriv->io.dev = dev;
0420 
0421     rtlpriv->io.write8_async = pci_write8_async;
0422     rtlpriv->io.write16_async = pci_write16_async;
0423     rtlpriv->io.write32_async = pci_write32_async;
0424 
0425     rtlpriv->io.read8_sync = pci_read8_sync;
0426     rtlpriv->io.read16_sync = pci_read16_sync;
0427     rtlpriv->io.read32_sync = pci_read32_sync;
0428 }
0429 
0430 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
0431                        struct sk_buff *skb,
0432                        struct rtl_tcb_desc *tcb_desc, u8 tid)
0433 {
0434     struct rtl_priv *rtlpriv = rtl_priv(hw);
0435     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
0436     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0437     struct sk_buff *next_skb;
0438     u8 additionlen = FCS_LEN;
0439 
0440     /* here open is 4, wep/tkip is 8, aes is 12*/
0441     if (info->control.hw_key)
0442         additionlen += info->control.hw_key->icv_len;
0443 
0444     /* The most skb num is 6 */
0445     tcb_desc->empkt_num = 0;
0446     spin_lock_bh(&rtlpriv->locks.waitq_lock);
0447     skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
0448         struct ieee80211_tx_info *next_info;
0449 
0450         next_info = IEEE80211_SKB_CB(next_skb);
0451         if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
0452             tcb_desc->empkt_len[tcb_desc->empkt_num] =
0453                 next_skb->len + additionlen;
0454             tcb_desc->empkt_num++;
0455         } else {
0456             break;
0457         }
0458 
0459         if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
0460                       next_skb))
0461             break;
0462 
0463         if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
0464             break;
0465     }
0466     spin_unlock_bh(&rtlpriv->locks.waitq_lock);
0467 
0468     return true;
0469 }
0470 
0471 /* just for early mode now */
0472 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
0473 {
0474     struct rtl_priv *rtlpriv = rtl_priv(hw);
0475     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
0476     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0477     struct sk_buff *skb = NULL;
0478     struct ieee80211_tx_info *info = NULL;
0479     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0480     int tid;
0481 
0482     if (!rtlpriv->rtlhal.earlymode_enable)
0483         return;
0484 
0485     if (rtlpriv->dm.supp_phymode_switch &&
0486         (rtlpriv->easy_concurrent_ctl.switch_in_process ||
0487         (rtlpriv->buddy_priv &&
0488         rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
0489         return;
0490     /* we just use em for BE/BK/VI/VO */
0491     for (tid = 7; tid >= 0; tid--) {
0492         u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
0493         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
0494 
0495         while (!mac->act_scanning &&
0496                rtlpriv->psc.rfpwr_state == ERFON) {
0497             struct rtl_tcb_desc tcb_desc;
0498 
0499             memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
0500 
0501             spin_lock(&rtlpriv->locks.waitq_lock);
0502             if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
0503                 (ring->entries - skb_queue_len(&ring->queue) >
0504                  rtlhal->max_earlymode_num)) {
0505                 skb = skb_dequeue(&mac->skb_waitq[tid]);
0506             } else {
0507                 spin_unlock(&rtlpriv->locks.waitq_lock);
0508                 break;
0509             }
0510             spin_unlock(&rtlpriv->locks.waitq_lock);
0511 
0512             /* Some macaddr can't do early mode. like
0513              * multicast/broadcast/no_qos data
0514              */
0515             info = IEEE80211_SKB_CB(skb);
0516             if (info->flags & IEEE80211_TX_CTL_AMPDU)
0517                 _rtl_update_earlymode_info(hw, skb,
0518                                &tcb_desc, tid);
0519 
0520             rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
0521         }
0522     }
0523 }
0524 
0525 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
0526 {
0527     struct rtl_priv *rtlpriv = rtl_priv(hw);
0528     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0529 
0530     struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
0531 
0532     while (skb_queue_len(&ring->queue)) {
0533         struct sk_buff *skb;
0534         struct ieee80211_tx_info *info;
0535         __le16 fc;
0536         u8 tid;
0537         u8 *entry;
0538 
0539         if (rtlpriv->use_new_trx_flow)
0540             entry = (u8 *)(&ring->buffer_desc[ring->idx]);
0541         else
0542             entry = (u8 *)(&ring->desc[ring->idx]);
0543 
0544         if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
0545             return;
0546         ring->idx = (ring->idx + 1) % ring->entries;
0547 
0548         skb = __skb_dequeue(&ring->queue);
0549         dma_unmap_single(&rtlpci->pdev->dev,
0550                  rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
0551                         true, HW_DESC_TXBUFF_ADDR),
0552                  skb->len, DMA_TO_DEVICE);
0553 
0554         /* remove early mode header */
0555         if (rtlpriv->rtlhal.earlymode_enable)
0556             skb_pull(skb, EM_HDR_LEN);
0557 
0558         rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
0559             "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
0560             ring->idx,
0561             skb_queue_len(&ring->queue),
0562             *(u16 *)(skb->data + 22));
0563 
0564         if (prio == TXCMD_QUEUE) {
0565             dev_kfree_skb(skb);
0566             goto tx_status_ok;
0567         }
0568 
0569         /* for sw LPS, just after NULL skb send out, we can
0570          * sure AP knows we are sleeping, we should not let
0571          * rf sleep
0572          */
0573         fc = rtl_get_fc(skb);
0574         if (ieee80211_is_nullfunc(fc)) {
0575             if (ieee80211_has_pm(fc)) {
0576                 rtlpriv->mac80211.offchan_delay = true;
0577                 rtlpriv->psc.state_inap = true;
0578             } else {
0579                 rtlpriv->psc.state_inap = false;
0580             }
0581         }
0582         if (ieee80211_is_action(fc)) {
0583             struct ieee80211_mgmt *action_frame =
0584                 (struct ieee80211_mgmt *)skb->data;
0585             if (action_frame->u.action.u.ht_smps.action ==
0586                 WLAN_HT_ACTION_SMPS) {
0587                 dev_kfree_skb(skb);
0588                 goto tx_status_ok;
0589             }
0590         }
0591 
0592         /* update tid tx pkt num */
0593         tid = rtl_get_tid(skb);
0594         if (tid <= 7)
0595             rtlpriv->link_info.tidtx_inperiod[tid]++;
0596 
0597         info = IEEE80211_SKB_CB(skb);
0598 
0599         if (likely(!ieee80211_is_nullfunc(fc))) {
0600             ieee80211_tx_info_clear_status(info);
0601             info->flags |= IEEE80211_TX_STAT_ACK;
0602             /*info->status.rates[0].count = 1; */
0603             ieee80211_tx_status_irqsafe(hw, skb);
0604         } else {
0605             rtl_tx_ackqueue(hw, skb);
0606         }
0607 
0608         if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
0609             rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
0610                 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
0611                 prio, ring->idx,
0612                 skb_queue_len(&ring->queue));
0613 
0614             ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
0615         }
0616 tx_status_ok:
0617         skb = NULL;
0618     }
0619 
0620     if (((rtlpriv->link_info.num_rx_inperiod +
0621           rtlpriv->link_info.num_tx_inperiod) > 8) ||
0622           rtlpriv->link_info.num_rx_inperiod > 2)
0623         rtl_lps_leave(hw, false);
0624 }
0625 
0626 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
0627                     struct sk_buff *new_skb, u8 *entry,
0628                     int rxring_idx, int desc_idx)
0629 {
0630     struct rtl_priv *rtlpriv = rtl_priv(hw);
0631     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0632     u32 bufferaddress;
0633     u8 tmp_one = 1;
0634     struct sk_buff *skb;
0635 
0636     if (likely(new_skb)) {
0637         skb = new_skb;
0638         goto remap;
0639     }
0640     skb = dev_alloc_skb(rtlpci->rxbuffersize);
0641     if (!skb)
0642         return 0;
0643 
0644 remap:
0645     /* just set skb->cb to mapping addr for pci_unmap_single use */
0646     *((dma_addr_t *)skb->cb) =
0647         dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb),
0648                    rtlpci->rxbuffersize, DMA_FROM_DEVICE);
0649     bufferaddress = *((dma_addr_t *)skb->cb);
0650     if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress))
0651         return 0;
0652     rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
0653     if (rtlpriv->use_new_trx_flow) {
0654         /* skb->cb may be 64 bit address */
0655         rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
0656                         HW_DESC_RX_PREPARE,
0657                         (u8 *)(dma_addr_t *)skb->cb);
0658     } else {
0659         rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
0660                         HW_DESC_RXBUFF_ADDR,
0661                         (u8 *)&bufferaddress);
0662         rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
0663                         HW_DESC_RXPKT_LEN,
0664                         (u8 *)&rtlpci->rxbuffersize);
0665         rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
0666                         HW_DESC_RXOWN,
0667                         (u8 *)&tmp_one);
0668     }
0669     return 1;
0670 }
0671 
0672 /* inorder to receive 8K AMSDU we have set skb to
0673  * 9100bytes in init rx ring, but if this packet is
0674  * not a AMSDU, this large packet will be sent to
0675  * TCP/IP directly, this cause big packet ping fail
0676  * like: "ping -s 65507", so here we will realloc skb
0677  * based on the true size of packet, Mac80211
0678  * Probably will do it better, but does not yet.
0679  *
0680  * Some platform will fail when alloc skb sometimes.
0681  * in this condition, we will send the old skb to
0682  * mac80211 directly, this will not cause any other
0683  * issues, but only this packet will be lost by TCP/IP
0684  */
0685 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
0686                     struct sk_buff *skb,
0687                     struct ieee80211_rx_status rx_status)
0688 {
0689     if (unlikely(!rtl_action_proc(hw, skb, false))) {
0690         dev_kfree_skb_any(skb);
0691     } else {
0692         struct sk_buff *uskb = NULL;
0693 
0694         uskb = dev_alloc_skb(skb->len + 128);
0695         if (likely(uskb)) {
0696             memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
0697                    sizeof(rx_status));
0698             skb_put_data(uskb, skb->data, skb->len);
0699             dev_kfree_skb_any(skb);
0700             ieee80211_rx_irqsafe(hw, uskb);
0701         } else {
0702             ieee80211_rx_irqsafe(hw, skb);
0703         }
0704     }
0705 }
0706 
0707 /*hsisr interrupt handler*/
0708 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
0709 {
0710     struct rtl_priv *rtlpriv = rtl_priv(hw);
0711     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0712 
0713     rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
0714                rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
0715                rtlpci->sys_irq_mask);
0716 }
0717 
0718 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
0719 {
0720     struct rtl_priv *rtlpriv = rtl_priv(hw);
0721     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0722     int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
0723     struct ieee80211_rx_status rx_status = { 0 };
0724     unsigned int count = rtlpci->rxringcount;
0725     u8 own;
0726     u8 tmp_one;
0727     bool unicast = false;
0728     u8 hw_queue = 0;
0729     unsigned int rx_remained_cnt = 0;
0730     struct rtl_stats stats = {
0731         .signal = 0,
0732         .rate = 0,
0733     };
0734 
0735     /*RX NORMAL PKT */
0736     while (count--) {
0737         struct ieee80211_hdr *hdr;
0738         __le16 fc;
0739         u16 len;
0740         /*rx buffer descriptor */
0741         struct rtl_rx_buffer_desc *buffer_desc = NULL;
0742         /*if use new trx flow, it means wifi info */
0743         struct rtl_rx_desc *pdesc = NULL;
0744         /*rx pkt */
0745         struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
0746                       rtlpci->rx_ring[rxring_idx].idx];
0747         struct sk_buff *new_skb;
0748 
0749         if (rtlpriv->use_new_trx_flow) {
0750             if (rx_remained_cnt == 0)
0751                 rx_remained_cnt =
0752                 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
0753                                       hw_queue);
0754             if (rx_remained_cnt == 0)
0755                 return;
0756             buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
0757                 rtlpci->rx_ring[rxring_idx].idx];
0758             pdesc = (struct rtl_rx_desc *)skb->data;
0759         } else {    /* rx descriptor */
0760             pdesc = &rtlpci->rx_ring[rxring_idx].desc[
0761                 rtlpci->rx_ring[rxring_idx].idx];
0762 
0763             own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
0764                                   false,
0765                                   HW_DESC_OWN);
0766             if (own) /* wait data to be filled by hardware */
0767                 return;
0768         }
0769 
0770         /* Reaching this point means: data is filled already
0771          * AAAAAAttention !!!
0772          * We can NOT access 'skb' before 'pci_unmap_single'
0773          */
0774         dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
0775                  rtlpci->rxbuffersize, DMA_FROM_DEVICE);
0776 
0777         /* get a new skb - if fail, old one will be reused */
0778         new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
0779         if (unlikely(!new_skb))
0780             goto no_new;
0781         memset(&rx_status, 0, sizeof(rx_status));
0782         rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
0783                          &rx_status, (u8 *)pdesc, skb);
0784 
0785         if (rtlpriv->use_new_trx_flow)
0786             rtlpriv->cfg->ops->rx_check_dma_ok(hw,
0787                                (u8 *)buffer_desc,
0788                                hw_queue);
0789 
0790         len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
0791                           HW_DESC_RXPKT_LEN);
0792 
0793         if (skb->end - skb->tail > len) {
0794             skb_put(skb, len);
0795             if (rtlpriv->use_new_trx_flow)
0796                 skb_reserve(skb, stats.rx_drvinfo_size +
0797                         stats.rx_bufshift + 24);
0798             else
0799                 skb_reserve(skb, stats.rx_drvinfo_size +
0800                         stats.rx_bufshift);
0801         } else {
0802             rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
0803                 "skb->end - skb->tail = %d, len is %d\n",
0804                 skb->end - skb->tail, len);
0805             dev_kfree_skb_any(skb);
0806             goto new_trx_end;
0807         }
0808         /* handle command packet here */
0809         if (stats.packet_report_type == C2H_PACKET) {
0810             rtl_c2hcmd_enqueue(hw, skb);
0811             goto new_trx_end;
0812         }
0813 
0814         /* NOTICE This can not be use for mac80211,
0815          * this is done in mac80211 code,
0816          * if done here sec DHCP will fail
0817          * skb_trim(skb, skb->len - 4);
0818          */
0819 
0820         hdr = rtl_get_hdr(skb);
0821         fc = rtl_get_fc(skb);
0822 
0823         if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) {
0824             memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
0825                    sizeof(rx_status));
0826 
0827             if (is_broadcast_ether_addr(hdr->addr1)) {
0828                 ;/*TODO*/
0829             } else if (is_multicast_ether_addr(hdr->addr1)) {
0830                 ;/*TODO*/
0831             } else {
0832                 unicast = true;
0833                 rtlpriv->stats.rxbytesunicast += skb->len;
0834             }
0835             rtl_is_special_data(hw, skb, false, true);
0836 
0837             if (ieee80211_is_data(fc)) {
0838                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
0839                 if (unicast)
0840                     rtlpriv->link_info.num_rx_inperiod++;
0841             }
0842 
0843             rtl_collect_scan_list(hw, skb);
0844 
0845             /* static bcn for roaming */
0846             rtl_beacon_statistic(hw, skb);
0847             rtl_p2p_info(hw, (void *)skb->data, skb->len);
0848             /* for sw lps */
0849             rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
0850             rtl_recognize_peer(hw, (void *)skb->data, skb->len);
0851             if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
0852                 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
0853                 (ieee80211_is_beacon(fc) ||
0854                  ieee80211_is_probe_resp(fc))) {
0855                 dev_kfree_skb_any(skb);
0856             } else {
0857                 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
0858             }
0859         } else {
0860             /* drop packets with errors or those too short */
0861             dev_kfree_skb_any(skb);
0862         }
0863 new_trx_end:
0864         if (rtlpriv->use_new_trx_flow) {
0865             rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
0866             rtlpci->rx_ring[hw_queue].next_rx_rp %=
0867                     RTL_PCI_MAX_RX_COUNT;
0868 
0869             rx_remained_cnt--;
0870             rtl_write_word(rtlpriv, 0x3B4,
0871                        rtlpci->rx_ring[hw_queue].next_rx_rp);
0872         }
0873         if (((rtlpriv->link_info.num_rx_inperiod +
0874               rtlpriv->link_info.num_tx_inperiod) > 8) ||
0875               rtlpriv->link_info.num_rx_inperiod > 2)
0876             rtl_lps_leave(hw, false);
0877         skb = new_skb;
0878 no_new:
0879         if (rtlpriv->use_new_trx_flow) {
0880             _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
0881                          rxring_idx,
0882                          rtlpci->rx_ring[rxring_idx].idx);
0883         } else {
0884             _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
0885                          rxring_idx,
0886                          rtlpci->rx_ring[rxring_idx].idx);
0887             if (rtlpci->rx_ring[rxring_idx].idx ==
0888                 rtlpci->rxringcount - 1)
0889                 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
0890                                 false,
0891                                 HW_DESC_RXERO,
0892                                 (u8 *)&tmp_one);
0893         }
0894         rtlpci->rx_ring[rxring_idx].idx =
0895                 (rtlpci->rx_ring[rxring_idx].idx + 1) %
0896                 rtlpci->rxringcount;
0897     }
0898 }
0899 
0900 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
0901 {
0902     struct ieee80211_hw *hw = dev_id;
0903     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0904     struct rtl_priv *rtlpriv = rtl_priv(hw);
0905     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0906     unsigned long flags;
0907     struct rtl_int intvec = {0};
0908 
0909     irqreturn_t ret = IRQ_HANDLED;
0910 
0911     if (rtlpci->irq_enabled == 0)
0912         return ret;
0913 
0914     spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0915     rtlpriv->cfg->ops->disable_interrupt(hw);
0916 
0917     /*read ISR: 4/8bytes */
0918     rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
0919 
0920     /*Shared IRQ or HW disappeared */
0921     if (!intvec.inta || intvec.inta == 0xffff)
0922         goto done;
0923 
0924     /*<1> beacon related */
0925     if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
0926         rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
0927             "beacon ok interrupt!\n");
0928 
0929     if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
0930         rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
0931             "beacon err interrupt!\n");
0932 
0933     if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
0934         rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
0935 
0936     if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
0937         rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
0938             "prepare beacon for interrupt!\n");
0939         tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
0940     }
0941 
0942     /*<2> Tx related */
0943     if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
0944         rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
0945 
0946     if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
0947         rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
0948             "Manage ok interrupt!\n");
0949         _rtl_pci_tx_isr(hw, MGNT_QUEUE);
0950     }
0951 
0952     if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
0953         rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
0954             "HIGH_QUEUE ok interrupt!\n");
0955         _rtl_pci_tx_isr(hw, HIGH_QUEUE);
0956     }
0957 
0958     if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
0959         rtlpriv->link_info.num_tx_inperiod++;
0960 
0961         rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
0962             "BK Tx OK interrupt!\n");
0963         _rtl_pci_tx_isr(hw, BK_QUEUE);
0964     }
0965 
0966     if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
0967         rtlpriv->link_info.num_tx_inperiod++;
0968 
0969         rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
0970             "BE TX OK interrupt!\n");
0971         _rtl_pci_tx_isr(hw, BE_QUEUE);
0972     }
0973 
0974     if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
0975         rtlpriv->link_info.num_tx_inperiod++;
0976 
0977         rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
0978             "VI TX OK interrupt!\n");
0979         _rtl_pci_tx_isr(hw, VI_QUEUE);
0980     }
0981 
0982     if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
0983         rtlpriv->link_info.num_tx_inperiod++;
0984 
0985         rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
0986             "Vo TX OK interrupt!\n");
0987         _rtl_pci_tx_isr(hw, VO_QUEUE);
0988     }
0989 
0990     if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
0991         if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
0992             rtlpriv->link_info.num_tx_inperiod++;
0993 
0994             rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
0995                 "H2C TX OK interrupt!\n");
0996             _rtl_pci_tx_isr(hw, H2C_QUEUE);
0997         }
0998     }
0999 
1000     if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1001         if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1002             rtlpriv->link_info.num_tx_inperiod++;
1003 
1004             rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1005                 "CMD TX OK interrupt!\n");
1006             _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1007         }
1008     }
1009 
1010     /*<3> Rx related */
1011     if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1012         rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
1013         _rtl_pci_rx_interrupt(hw);
1014     }
1015 
1016     if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1017         rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1018             "rx descriptor unavailable!\n");
1019         _rtl_pci_rx_interrupt(hw);
1020     }
1021 
1022     if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1023         rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
1024         _rtl_pci_rx_interrupt(hw);
1025     }
1026 
1027     /*<4> fw related*/
1028     if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1029         if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1030             rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1031                 "firmware interrupt!\n");
1032             queue_delayed_work(rtlpriv->works.rtl_wq,
1033                        &rtlpriv->works.fwevt_wq, 0);
1034         }
1035     }
1036 
1037     /*<5> hsisr related*/
1038     /* Only 8188EE & 8723BE Supported.
1039      * If Other ICs Come in, System will corrupt,
1040      * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1041      * are not initialized
1042      */
1043     if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1044         rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1045         if (unlikely(intvec.inta &
1046             rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1047             rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1048                 "hsisr interrupt!\n");
1049             _rtl_pci_hs_interrupt(hw);
1050         }
1051     }
1052 
1053     if (rtlpriv->rtlhal.earlymode_enable)
1054         tasklet_schedule(&rtlpriv->works.irq_tasklet);
1055 
1056 done:
1057     rtlpriv->cfg->ops->enable_interrupt(hw);
1058     spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1059     return ret;
1060 }
1061 
1062 static void _rtl_pci_irq_tasklet(struct tasklet_struct *t)
1063 {
1064     struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet);
1065     struct ieee80211_hw *hw = rtlpriv->hw;
1066     _rtl_pci_tx_chk_waitq(hw);
1067 }
1068 
1069 static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t)
1070 {
1071     struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t,
1072                         works.irq_prepare_bcn_tasklet);
1073     struct ieee80211_hw *hw = rtlpriv->hw;
1074     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1075     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1076     struct rtl8192_tx_ring *ring = NULL;
1077     struct ieee80211_hdr *hdr = NULL;
1078     struct ieee80211_tx_info *info = NULL;
1079     struct sk_buff *pskb = NULL;
1080     struct rtl_tx_desc *pdesc = NULL;
1081     struct rtl_tcb_desc tcb_desc;
1082     /*This is for new trx flow*/
1083     struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1084     u8 temp_one = 1;
1085     u8 *entry;
1086 
1087     memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1088     ring = &rtlpci->tx_ring[BEACON_QUEUE];
1089     pskb = __skb_dequeue(&ring->queue);
1090     if (rtlpriv->use_new_trx_flow)
1091         entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1092     else
1093         entry = (u8 *)(&ring->desc[ring->idx]);
1094     if (pskb) {
1095         dma_unmap_single(&rtlpci->pdev->dev,
1096                  rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1097                         true, HW_DESC_TXBUFF_ADDR),
1098                  pskb->len, DMA_TO_DEVICE);
1099         kfree_skb(pskb);
1100     }
1101 
1102     /*NB: the beacon data buffer must be 32-bit aligned. */
1103     pskb = ieee80211_beacon_get(hw, mac->vif, 0);
1104     if (!pskb)
1105         return;
1106     hdr = rtl_get_hdr(pskb);
1107     info = IEEE80211_SKB_CB(pskb);
1108     pdesc = &ring->desc[0];
1109     if (rtlpriv->use_new_trx_flow)
1110         pbuffer_desc = &ring->buffer_desc[0];
1111 
1112     rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1113                     (u8 *)pbuffer_desc, info, NULL, pskb,
1114                     BEACON_QUEUE, &tcb_desc);
1115 
1116     __skb_queue_tail(&ring->queue, pskb);
1117 
1118     if (rtlpriv->use_new_trx_flow) {
1119         temp_one = 4;
1120         rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1121                         HW_DESC_OWN, (u8 *)&temp_one);
1122     } else {
1123         rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1124                         &temp_one);
1125     }
1126 }
1127 
1128 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1129 {
1130     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1131     struct rtl_priv *rtlpriv = rtl_priv(hw);
1132     struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1133     u8 i;
1134     u16 desc_num;
1135 
1136     if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1137         desc_num = TX_DESC_NUM_92E;
1138     else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1139         desc_num = TX_DESC_NUM_8822B;
1140     else
1141         desc_num = RT_TXDESC_NUM;
1142 
1143     for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1144         rtlpci->txringcount[i] = desc_num;
1145 
1146     /*we just alloc 2 desc for beacon queue,
1147      *because we just need first desc in hw beacon.
1148      */
1149     rtlpci->txringcount[BEACON_QUEUE] = 2;
1150 
1151     /*BE queue need more descriptor for performance
1152      *consideration or, No more tx desc will happen,
1153      *and may cause mac80211 mem leakage.
1154      */
1155     if (!rtl_priv(hw)->use_new_trx_flow)
1156         rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1157 
1158     rtlpci->rxbuffersize = 9100;    /*2048/1024; */
1159     rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1160 }
1161 
1162 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1163                  struct pci_dev *pdev)
1164 {
1165     struct rtl_priv *rtlpriv = rtl_priv(hw);
1166     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1167     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1168     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1169 
1170     rtlpci->up_first_time = true;
1171     rtlpci->being_init_adapter = false;
1172 
1173     rtlhal->hw = hw;
1174     rtlpci->pdev = pdev;
1175 
1176     /*Tx/Rx related var */
1177     _rtl_pci_init_trx_var(hw);
1178 
1179     /*IBSS*/
1180     mac->beacon_interval = 100;
1181 
1182     /*AMPDU*/
1183     mac->min_space_cfg = 0;
1184     mac->max_mss_density = 0;
1185     /*set sane AMPDU defaults */
1186     mac->current_ampdu_density = 7;
1187     mac->current_ampdu_factor = 3;
1188 
1189     /*Retry Limit*/
1190     mac->retry_short = 7;
1191     mac->retry_long = 7;
1192 
1193     /*QOS*/
1194     rtlpci->acm_method = EACMWAY2_SW;
1195 
1196     /*task */
1197     tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet);
1198     tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet,
1199              _rtl_pci_prepare_bcn_tasklet);
1200     INIT_WORK(&rtlpriv->works.lps_change_work,
1201           rtl_lps_change_work_callback);
1202 }
1203 
1204 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1205                  unsigned int prio, unsigned int entries)
1206 {
1207     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1208     struct rtl_priv *rtlpriv = rtl_priv(hw);
1209     struct rtl_tx_buffer_desc *buffer_desc;
1210     struct rtl_tx_desc *desc;
1211     dma_addr_t buffer_desc_dma, desc_dma;
1212     u32 nextdescaddress;
1213     int i;
1214 
1215     /* alloc tx buffer desc for new trx flow*/
1216     if (rtlpriv->use_new_trx_flow) {
1217         buffer_desc =
1218            dma_alloc_coherent(&rtlpci->pdev->dev,
1219                       sizeof(*buffer_desc) * entries,
1220                       &buffer_desc_dma, GFP_KERNEL);
1221 
1222         if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1223             pr_err("Cannot allocate TX ring (prio = %d)\n",
1224                    prio);
1225             return -ENOMEM;
1226         }
1227 
1228         rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1229         rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1230 
1231         rtlpci->tx_ring[prio].cur_tx_rp = 0;
1232         rtlpci->tx_ring[prio].cur_tx_wp = 0;
1233     }
1234 
1235     /* alloc dma for this ring */
1236     desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries,
1237                   &desc_dma, GFP_KERNEL);
1238 
1239     if (!desc || (unsigned long)desc & 0xFF) {
1240         pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1241         return -ENOMEM;
1242     }
1243 
1244     rtlpci->tx_ring[prio].desc = desc;
1245     rtlpci->tx_ring[prio].dma = desc_dma;
1246 
1247     rtlpci->tx_ring[prio].idx = 0;
1248     rtlpci->tx_ring[prio].entries = entries;
1249     skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1250 
1251     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1252         prio, desc);
1253 
1254     /* init every desc in this ring */
1255     if (!rtlpriv->use_new_trx_flow) {
1256         for (i = 0; i < entries; i++) {
1257             nextdescaddress = (u32)desc_dma +
1258                       ((i + 1) % entries) *
1259                       sizeof(*desc);
1260 
1261             rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1262                             true,
1263                             HW_DESC_TX_NEXTDESC_ADDR,
1264                             (u8 *)&nextdescaddress);
1265         }
1266     }
1267     return 0;
1268 }
1269 
1270 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1271 {
1272     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1273     struct rtl_priv *rtlpriv = rtl_priv(hw);
1274     int i;
1275 
1276     if (rtlpriv->use_new_trx_flow) {
1277         struct rtl_rx_buffer_desc *entry = NULL;
1278         /* alloc dma for this ring */
1279         rtlpci->rx_ring[rxring_idx].buffer_desc =
1280             dma_alloc_coherent(&rtlpci->pdev->dev,
1281                        sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1282                        rtlpci->rxringcount,
1283                        &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1284         if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1285             (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1286             pr_err("Cannot allocate RX ring\n");
1287             return -ENOMEM;
1288         }
1289 
1290         /* init every desc in this ring */
1291         rtlpci->rx_ring[rxring_idx].idx = 0;
1292         for (i = 0; i < rtlpci->rxringcount; i++) {
1293             entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1294             if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1295                               rxring_idx, i))
1296                 return -ENOMEM;
1297         }
1298     } else {
1299         struct rtl_rx_desc *entry = NULL;
1300         u8 tmp_one = 1;
1301         /* alloc dma for this ring */
1302         rtlpci->rx_ring[rxring_idx].desc =
1303             dma_alloc_coherent(&rtlpci->pdev->dev,
1304                        sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1305                        rtlpci->rxringcount,
1306                        &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1307         if (!rtlpci->rx_ring[rxring_idx].desc ||
1308             (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1309             pr_err("Cannot allocate RX ring\n");
1310             return -ENOMEM;
1311         }
1312 
1313         /* init every desc in this ring */
1314         rtlpci->rx_ring[rxring_idx].idx = 0;
1315 
1316         for (i = 0; i < rtlpci->rxringcount; i++) {
1317             entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1318             if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1319                               rxring_idx, i))
1320                 return -ENOMEM;
1321         }
1322 
1323         rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1324                         HW_DESC_RXERO, &tmp_one);
1325     }
1326     return 0;
1327 }
1328 
1329 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1330                   unsigned int prio)
1331 {
1332     struct rtl_priv *rtlpriv = rtl_priv(hw);
1333     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1334     struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1335 
1336     /* free every desc in this ring */
1337     while (skb_queue_len(&ring->queue)) {
1338         u8 *entry;
1339         struct sk_buff *skb = __skb_dequeue(&ring->queue);
1340 
1341         if (rtlpriv->use_new_trx_flow)
1342             entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1343         else
1344             entry = (u8 *)(&ring->desc[ring->idx]);
1345 
1346         dma_unmap_single(&rtlpci->pdev->dev,
1347                  rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1348                         true, HW_DESC_TXBUFF_ADDR),
1349                  skb->len, DMA_TO_DEVICE);
1350         kfree_skb(skb);
1351         ring->idx = (ring->idx + 1) % ring->entries;
1352     }
1353 
1354     /* free dma of this ring */
1355     dma_free_coherent(&rtlpci->pdev->dev,
1356               sizeof(*ring->desc) * ring->entries, ring->desc,
1357               ring->dma);
1358     ring->desc = NULL;
1359     if (rtlpriv->use_new_trx_flow) {
1360         dma_free_coherent(&rtlpci->pdev->dev,
1361                   sizeof(*ring->buffer_desc) * ring->entries,
1362                   ring->buffer_desc, ring->buffer_desc_dma);
1363         ring->buffer_desc = NULL;
1364     }
1365 }
1366 
1367 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1368 {
1369     struct rtl_priv *rtlpriv = rtl_priv(hw);
1370     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1371     int i;
1372 
1373     /* free every desc in this ring */
1374     for (i = 0; i < rtlpci->rxringcount; i++) {
1375         struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1376 
1377         if (!skb)
1378             continue;
1379         dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
1380                  rtlpci->rxbuffersize, DMA_FROM_DEVICE);
1381         kfree_skb(skb);
1382     }
1383 
1384     /* free dma of this ring */
1385     if (rtlpriv->use_new_trx_flow) {
1386         dma_free_coherent(&rtlpci->pdev->dev,
1387                   sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1388                   rtlpci->rxringcount,
1389                   rtlpci->rx_ring[rxring_idx].buffer_desc,
1390                   rtlpci->rx_ring[rxring_idx].dma);
1391         rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1392     } else {
1393         dma_free_coherent(&rtlpci->pdev->dev,
1394                   sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1395                   rtlpci->rxringcount,
1396                   rtlpci->rx_ring[rxring_idx].desc,
1397                   rtlpci->rx_ring[rxring_idx].dma);
1398         rtlpci->rx_ring[rxring_idx].desc = NULL;
1399     }
1400 }
1401 
1402 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1403 {
1404     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1405     int ret;
1406     int i, rxring_idx;
1407 
1408     /* rxring_idx 0:RX_MPDU_QUEUE
1409      * rxring_idx 1:RX_CMD_QUEUE
1410      */
1411     for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1412         ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1413         if (ret)
1414             return ret;
1415     }
1416 
1417     for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1418         ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1419         if (ret)
1420             goto err_free_rings;
1421     }
1422 
1423     return 0;
1424 
1425 err_free_rings:
1426     for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1427         _rtl_pci_free_rx_ring(hw, rxring_idx);
1428 
1429     for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1430         if (rtlpci->tx_ring[i].desc ||
1431             rtlpci->tx_ring[i].buffer_desc)
1432             _rtl_pci_free_tx_ring(hw, i);
1433 
1434     return 1;
1435 }
1436 
1437 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1438 {
1439     u32 i, rxring_idx;
1440 
1441     /*free rx rings */
1442     for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1443         _rtl_pci_free_rx_ring(hw, rxring_idx);
1444 
1445     /*free tx rings */
1446     for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1447         _rtl_pci_free_tx_ring(hw, i);
1448 
1449     return 0;
1450 }
1451 
1452 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1453 {
1454     struct rtl_priv *rtlpriv = rtl_priv(hw);
1455     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1456     int i, rxring_idx;
1457     unsigned long flags;
1458     u8 tmp_one = 1;
1459     u32 bufferaddress;
1460     /* rxring_idx 0:RX_MPDU_QUEUE */
1461     /* rxring_idx 1:RX_CMD_QUEUE */
1462     for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1463         /* force the rx_ring[RX_MPDU_QUEUE/
1464          * RX_CMD_QUEUE].idx to the first one
1465          *new trx flow, do nothing
1466          */
1467         if (!rtlpriv->use_new_trx_flow &&
1468             rtlpci->rx_ring[rxring_idx].desc) {
1469             struct rtl_rx_desc *entry = NULL;
1470 
1471             rtlpci->rx_ring[rxring_idx].idx = 0;
1472             for (i = 0; i < rtlpci->rxringcount; i++) {
1473                 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1474                 bufferaddress =
1475                   rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1476                   false, HW_DESC_RXBUFF_ADDR);
1477                 memset((u8 *)entry, 0,
1478                        sizeof(*rtlpci->rx_ring
1479                        [rxring_idx].desc));/*clear one entry*/
1480                 if (rtlpriv->use_new_trx_flow) {
1481                     rtlpriv->cfg->ops->set_desc(hw,
1482                         (u8 *)entry, false,
1483                         HW_DESC_RX_PREPARE,
1484                         (u8 *)&bufferaddress);
1485                 } else {
1486                     rtlpriv->cfg->ops->set_desc(hw,
1487                         (u8 *)entry, false,
1488                         HW_DESC_RXBUFF_ADDR,
1489                         (u8 *)&bufferaddress);
1490                     rtlpriv->cfg->ops->set_desc(hw,
1491                         (u8 *)entry, false,
1492                         HW_DESC_RXPKT_LEN,
1493                         (u8 *)&rtlpci->rxbuffersize);
1494                     rtlpriv->cfg->ops->set_desc(hw,
1495                         (u8 *)entry, false,
1496                         HW_DESC_RXOWN,
1497                         (u8 *)&tmp_one);
1498                 }
1499             }
1500             rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1501                         HW_DESC_RXERO, (u8 *)&tmp_one);
1502         }
1503         rtlpci->rx_ring[rxring_idx].idx = 0;
1504     }
1505 
1506     /*after reset, release previous pending packet,
1507      *and force the  tx idx to the first one
1508      */
1509     spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1510     for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1511         if (rtlpci->tx_ring[i].desc ||
1512             rtlpci->tx_ring[i].buffer_desc) {
1513             struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1514 
1515             while (skb_queue_len(&ring->queue)) {
1516                 u8 *entry;
1517                 struct sk_buff *skb =
1518                     __skb_dequeue(&ring->queue);
1519                 if (rtlpriv->use_new_trx_flow)
1520                     entry = (u8 *)(&ring->buffer_desc
1521                                 [ring->idx]);
1522                 else
1523                     entry = (u8 *)(&ring->desc[ring->idx]);
1524 
1525                 dma_unmap_single(&rtlpci->pdev->dev,
1526                          rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1527                                 true, HW_DESC_TXBUFF_ADDR),
1528                          skb->len, DMA_TO_DEVICE);
1529                 dev_kfree_skb_irq(skb);
1530                 ring->idx = (ring->idx + 1) % ring->entries;
1531             }
1532 
1533             if (rtlpriv->use_new_trx_flow) {
1534                 rtlpci->tx_ring[i].cur_tx_rp = 0;
1535                 rtlpci->tx_ring[i].cur_tx_wp = 0;
1536             }
1537 
1538             ring->idx = 0;
1539             ring->entries = rtlpci->txringcount[i];
1540         }
1541     }
1542     spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1543 
1544     return 0;
1545 }
1546 
1547 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1548                     struct ieee80211_sta *sta,
1549                     struct sk_buff *skb)
1550 {
1551     struct rtl_priv *rtlpriv = rtl_priv(hw);
1552     struct rtl_sta_info *sta_entry = NULL;
1553     u8 tid = rtl_get_tid(skb);
1554     __le16 fc = rtl_get_fc(skb);
1555 
1556     if (!sta)
1557         return false;
1558     sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1559 
1560     if (!rtlpriv->rtlhal.earlymode_enable)
1561         return false;
1562     if (ieee80211_is_nullfunc(fc))
1563         return false;
1564     if (ieee80211_is_qos_nullfunc(fc))
1565         return false;
1566     if (ieee80211_is_pspoll(fc))
1567         return false;
1568     if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1569         return false;
1570     if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1571         return false;
1572     if (tid > 7)
1573         return false;
1574 
1575     /* maybe every tid should be checked */
1576     if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1577         return false;
1578 
1579     spin_lock_bh(&rtlpriv->locks.waitq_lock);
1580     skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1581     spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1582 
1583     return true;
1584 }
1585 
1586 static int rtl_pci_tx(struct ieee80211_hw *hw,
1587               struct ieee80211_sta *sta,
1588               struct sk_buff *skb,
1589               struct rtl_tcb_desc *ptcb_desc)
1590 {
1591     struct rtl_priv *rtlpriv = rtl_priv(hw);
1592     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1593     struct rtl8192_tx_ring *ring;
1594     struct rtl_tx_desc *pdesc;
1595     struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1596     u16 idx;
1597     u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1598     unsigned long flags;
1599     struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1600     __le16 fc = rtl_get_fc(skb);
1601     u8 *pda_addr = hdr->addr1;
1602     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1603     u8 own;
1604     u8 temp_one = 1;
1605 
1606     if (ieee80211_is_mgmt(fc))
1607         rtl_tx_mgmt_proc(hw, skb);
1608 
1609     if (rtlpriv->psc.sw_ps_enabled) {
1610         if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1611             !ieee80211_has_pm(fc))
1612             hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1613     }
1614 
1615     rtl_action_proc(hw, skb, true);
1616 
1617     if (is_multicast_ether_addr(pda_addr))
1618         rtlpriv->stats.txbytesmulticast += skb->len;
1619     else if (is_broadcast_ether_addr(pda_addr))
1620         rtlpriv->stats.txbytesbroadcast += skb->len;
1621     else
1622         rtlpriv->stats.txbytesunicast += skb->len;
1623 
1624     spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1625     ring = &rtlpci->tx_ring[hw_queue];
1626     if (hw_queue != BEACON_QUEUE) {
1627         if (rtlpriv->use_new_trx_flow)
1628             idx = ring->cur_tx_wp;
1629         else
1630             idx = (ring->idx + skb_queue_len(&ring->queue)) %
1631                   ring->entries;
1632     } else {
1633         idx = 0;
1634     }
1635 
1636     pdesc = &ring->desc[idx];
1637     if (rtlpriv->use_new_trx_flow) {
1638         ptx_bd_desc = &ring->buffer_desc[idx];
1639     } else {
1640         own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1641                 true, HW_DESC_OWN);
1642 
1643         if (own == 1 && hw_queue != BEACON_QUEUE) {
1644             rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1645                 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1646                 hw_queue, ring->idx, idx,
1647                 skb_queue_len(&ring->queue));
1648 
1649             spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1650                            flags);
1651             return skb->len;
1652         }
1653     }
1654 
1655     if (rtlpriv->cfg->ops->get_available_desc &&
1656         rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1657         rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1658             "get_available_desc fail\n");
1659         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1660         return skb->len;
1661     }
1662 
1663     if (ieee80211_is_data(fc))
1664         rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1665 
1666     rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1667             (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1668 
1669     __skb_queue_tail(&ring->queue, skb);
1670 
1671     if (rtlpriv->use_new_trx_flow) {
1672         rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1673                         HW_DESC_OWN, &hw_queue);
1674     } else {
1675         rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1676                         HW_DESC_OWN, &temp_one);
1677     }
1678 
1679     if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1680         hw_queue != BEACON_QUEUE) {
1681         rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1682             "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1683              hw_queue, ring->idx, idx,
1684              skb_queue_len(&ring->queue));
1685 
1686         ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1687     }
1688 
1689     spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1690 
1691     rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1692 
1693     return 0;
1694 }
1695 
1696 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1697 {
1698     struct rtl_priv *rtlpriv = rtl_priv(hw);
1699     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1700     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1701     struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1702     u16 i = 0;
1703     int queue_id;
1704     struct rtl8192_tx_ring *ring;
1705 
1706     if (mac->skip_scan)
1707         return;
1708 
1709     for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1710         u32 queue_len;
1711 
1712         if (((queues >> queue_id) & 0x1) == 0) {
1713             queue_id--;
1714             continue;
1715         }
1716         ring = &pcipriv->dev.tx_ring[queue_id];
1717         queue_len = skb_queue_len(&ring->queue);
1718         if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1719             queue_id == TXCMD_QUEUE) {
1720             queue_id--;
1721             continue;
1722         } else {
1723             msleep(20);
1724             i++;
1725         }
1726 
1727         /* we just wait 1s for all queues */
1728         if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1729             is_hal_stop(rtlhal) || i >= 200)
1730             return;
1731     }
1732 }
1733 
1734 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1735 {
1736     struct rtl_priv *rtlpriv = rtl_priv(hw);
1737     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1738 
1739     _rtl_pci_deinit_trx_ring(hw);
1740 
1741     synchronize_irq(rtlpci->pdev->irq);
1742     tasklet_kill(&rtlpriv->works.irq_tasklet);
1743     cancel_work_sync(&rtlpriv->works.lps_change_work);
1744 
1745     destroy_workqueue(rtlpriv->works.rtl_wq);
1746 }
1747 
1748 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1749 {
1750     int err;
1751 
1752     _rtl_pci_init_struct(hw, pdev);
1753 
1754     err = _rtl_pci_init_trx_ring(hw);
1755     if (err) {
1756         pr_err("tx ring initialization failed\n");
1757         return err;
1758     }
1759 
1760     return 0;
1761 }
1762 
1763 static int rtl_pci_start(struct ieee80211_hw *hw)
1764 {
1765     struct rtl_priv *rtlpriv = rtl_priv(hw);
1766     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1767     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1768     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1769     struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1770     struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
1771 
1772     int err;
1773 
1774     rtl_pci_reset_trx_ring(hw);
1775 
1776     rtlpci->driver_is_goingto_unload = false;
1777     if (rtlpriv->cfg->ops->get_btc_status &&
1778         rtlpriv->cfg->ops->get_btc_status()) {
1779         rtlpriv->btcoexist.btc_info.ap_num = 36;
1780         btc_ops->btc_init_variables(rtlpriv);
1781         btc_ops->btc_init_hal_vars(rtlpriv);
1782     } else if (btc_ops) {
1783         btc_ops->btc_init_variables_wifi_only(rtlpriv);
1784     }
1785 
1786     err = rtlpriv->cfg->ops->hw_init(hw);
1787     if (err) {
1788         rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1789             "Failed to config hardware!\n");
1790         kfree(rtlpriv->btcoexist.btc_context);
1791         kfree(rtlpriv->btcoexist.wifi_only_context);
1792         return err;
1793     }
1794     rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1795             &rtlmac->retry_long);
1796 
1797     rtlpriv->cfg->ops->enable_interrupt(hw);
1798     rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1799 
1800     rtl_init_rx_config(hw);
1801 
1802     /*should be after adapter start and interrupt enable. */
1803     set_hal_start(rtlhal);
1804 
1805     RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1806 
1807     rtlpci->up_first_time = false;
1808 
1809     rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1810     return 0;
1811 }
1812 
1813 static void rtl_pci_stop(struct ieee80211_hw *hw)
1814 {
1815     struct rtl_priv *rtlpriv = rtl_priv(hw);
1816     struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1817     struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1818     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1819     unsigned long flags;
1820     u8 rf_timeout = 0;
1821 
1822     if (rtlpriv->cfg->ops->get_btc_status())
1823         rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1824 
1825     if (rtlpriv->btcoexist.btc_ops)
1826         rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1827 
1828     /*should be before disable interrupt&adapter
1829      *and will do it immediately.
1830      */
1831     set_hal_stop(rtlhal);
1832 
1833     rtlpci->driver_is_goingto_unload = true;
1834     rtlpriv->cfg->ops->disable_interrupt(hw);
1835     cancel_work_sync(&rtlpriv->works.lps_change_work);
1836 
1837     spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1838     while (ppsc->rfchange_inprogress) {
1839         spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1840         if (rf_timeout > 100) {
1841             spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1842             break;
1843         }
1844         mdelay(1);
1845         rf_timeout++;
1846         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1847     }
1848     ppsc->rfchange_inprogress = true;
1849     spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1850 
1851     rtlpriv->cfg->ops->hw_disable(hw);
1852     /* some things are not needed if firmware not available */
1853     if (!rtlpriv->max_fw_size)
1854         return;
1855     rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1856 
1857     spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1858     ppsc->rfchange_inprogress = false;
1859     spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1860 
1861     rtl_pci_enable_aspm(hw);
1862 }
1863 
1864 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1865                   struct ieee80211_hw *hw)
1866 {
1867     struct rtl_priv *rtlpriv = rtl_priv(hw);
1868     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1869     struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1870     struct pci_dev *bridge_pdev = pdev->bus->self;
1871     u16 venderid;
1872     u16 deviceid;
1873     u8 revisionid;
1874     u16 irqline;
1875     u8 tmp;
1876 
1877     pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1878     venderid = pdev->vendor;
1879     deviceid = pdev->device;
1880     pci_read_config_byte(pdev, 0x8, &revisionid);
1881     pci_read_config_word(pdev, 0x3C, &irqline);
1882 
1883     /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1884      * r8192e_pci, and RTL8192SE, which uses this driver. If the
1885      * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1886      * the correct driver is r8192e_pci, thus this routine should
1887      * return false.
1888      */
1889     if (deviceid == RTL_PCI_8192SE_DID &&
1890         revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1891         return false;
1892 
1893     if (deviceid == RTL_PCI_8192_DID ||
1894         deviceid == RTL_PCI_0044_DID ||
1895         deviceid == RTL_PCI_0047_DID ||
1896         deviceid == RTL_PCI_8192SE_DID ||
1897         deviceid == RTL_PCI_8174_DID ||
1898         deviceid == RTL_PCI_8173_DID ||
1899         deviceid == RTL_PCI_8172_DID ||
1900         deviceid == RTL_PCI_8171_DID) {
1901         switch (revisionid) {
1902         case RTL_PCI_REVISION_ID_8192PCIE:
1903             rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1904                 "8192 PCI-E is found - vid/did=%x/%x\n",
1905                 venderid, deviceid);
1906             rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1907             return false;
1908         case RTL_PCI_REVISION_ID_8192SE:
1909             rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1910                 "8192SE is found - vid/did=%x/%x\n",
1911                 venderid, deviceid);
1912             rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1913             break;
1914         default:
1915             rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1916                 "Err: Unknown device - vid/did=%x/%x\n",
1917                 venderid, deviceid);
1918             rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1919             break;
1920         }
1921     } else if (deviceid == RTL_PCI_8723AE_DID) {
1922         rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1923         rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1924             "8723AE PCI-E is found - vid/did=%x/%x\n",
1925             venderid, deviceid);
1926     } else if (deviceid == RTL_PCI_8192CET_DID ||
1927            deviceid == RTL_PCI_8192CE_DID ||
1928            deviceid == RTL_PCI_8191CE_DID ||
1929            deviceid == RTL_PCI_8188CE_DID) {
1930         rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1931         rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1932             "8192C PCI-E is found - vid/did=%x/%x\n",
1933             venderid, deviceid);
1934     } else if (deviceid == RTL_PCI_8192DE_DID ||
1935            deviceid == RTL_PCI_8192DE_DID2) {
1936         rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1937         rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1938             "8192D PCI-E is found - vid/did=%x/%x\n",
1939             venderid, deviceid);
1940     } else if (deviceid == RTL_PCI_8188EE_DID) {
1941         rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1942         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1943             "Find adapter, Hardware type is 8188EE\n");
1944     } else if (deviceid == RTL_PCI_8723BE_DID) {
1945         rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1946         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1947             "Find adapter, Hardware type is 8723BE\n");
1948     } else if (deviceid == RTL_PCI_8192EE_DID) {
1949         rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1950         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1951             "Find adapter, Hardware type is 8192EE\n");
1952     } else if (deviceid == RTL_PCI_8821AE_DID) {
1953         rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1954         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1955             "Find adapter, Hardware type is 8821AE\n");
1956     } else if (deviceid == RTL_PCI_8812AE_DID) {
1957         rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1958         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1959             "Find adapter, Hardware type is 8812AE\n");
1960     } else if (deviceid == RTL_PCI_8822BE_DID) {
1961         rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1962         rtlhal->bandset = BAND_ON_BOTH;
1963         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1964             "Find adapter, Hardware type is 8822BE\n");
1965     } else {
1966         rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1967             "Err: Unknown device - vid/did=%x/%x\n",
1968              venderid, deviceid);
1969 
1970         rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1971     }
1972 
1973     if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1974         if (revisionid == 0 || revisionid == 1) {
1975             if (revisionid == 0) {
1976                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1977                     "Find 92DE MAC0\n");
1978                 rtlhal->interfaceindex = 0;
1979             } else if (revisionid == 1) {
1980                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1981                     "Find 92DE MAC1\n");
1982                 rtlhal->interfaceindex = 1;
1983             }
1984         } else {
1985             rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1986                 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1987                  venderid, deviceid, revisionid);
1988             rtlhal->interfaceindex = 0;
1989         }
1990     }
1991 
1992     switch (rtlhal->hw_type) {
1993     case HARDWARE_TYPE_RTL8192EE:
1994     case HARDWARE_TYPE_RTL8822BE:
1995         /* use new trx flow */
1996         rtlpriv->use_new_trx_flow = true;
1997         break;
1998 
1999     default:
2000         rtlpriv->use_new_trx_flow = false;
2001         break;
2002     }
2003 
2004     /*find bus info */
2005     pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2006     pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2007     pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2008 
2009     /*find bridge info */
2010     pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2011     /* some ARM have no bridge_pdev and will crash here
2012      * so we should check if bridge_pdev is NULL
2013      */
2014     if (bridge_pdev) {
2015         /*find bridge info if available */
2016         pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2017         for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2018             if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2019                 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2020                 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2021                     "Pci Bridge Vendor is found index: %d\n",
2022                     tmp);
2023                 break;
2024             }
2025         }
2026     }
2027 
2028     if (pcipriv->ndis_adapter.pcibridge_vendor !=
2029         PCI_BRIDGE_VENDOR_UNKNOWN) {
2030         pcipriv->ndis_adapter.pcibridge_busnum =
2031             bridge_pdev->bus->number;
2032         pcipriv->ndis_adapter.pcibridge_devnum =
2033             PCI_SLOT(bridge_pdev->devfn);
2034         pcipriv->ndis_adapter.pcibridge_funcnum =
2035             PCI_FUNC(bridge_pdev->devfn);
2036         pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2037             pci_pcie_cap(bridge_pdev);
2038         pcipriv->ndis_adapter.num4bytes =
2039             (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2040 
2041         rtl_pci_get_linkcontrol_field(hw);
2042 
2043         if (pcipriv->ndis_adapter.pcibridge_vendor ==
2044             PCI_BRIDGE_VENDOR_AMD) {
2045             pcipriv->ndis_adapter.amd_l1_patch =
2046                 rtl_pci_get_amd_l1_patch(hw);
2047         }
2048     }
2049 
2050     rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2051         "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2052         pcipriv->ndis_adapter.busnumber,
2053         pcipriv->ndis_adapter.devnumber,
2054         pcipriv->ndis_adapter.funcnumber,
2055         pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2056 
2057     rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2058         "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2059         pcipriv->ndis_adapter.pcibridge_busnum,
2060         pcipriv->ndis_adapter.pcibridge_devnum,
2061         pcipriv->ndis_adapter.pcibridge_funcnum,
2062         pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2063         pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2064         pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2065         pcipriv->ndis_adapter.amd_l1_patch);
2066 
2067     rtl_pci_parse_configuration(pdev, hw);
2068     list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2069 
2070     return true;
2071 }
2072 
2073 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2074 {
2075     struct rtl_priv *rtlpriv = rtl_priv(hw);
2076     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2077     struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2078     int ret;
2079 
2080     ret = pci_enable_msi(rtlpci->pdev);
2081     if (ret < 0)
2082         return ret;
2083 
2084     ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2085               IRQF_SHARED, KBUILD_MODNAME, hw);
2086     if (ret < 0) {
2087         pci_disable_msi(rtlpci->pdev);
2088         return ret;
2089     }
2090 
2091     rtlpci->using_msi = true;
2092 
2093     rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2094         "MSI Interrupt Mode!\n");
2095     return 0;
2096 }
2097 
2098 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2099 {
2100     struct rtl_priv *rtlpriv = rtl_priv(hw);
2101     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2102     struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2103     int ret;
2104 
2105     ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2106               IRQF_SHARED, KBUILD_MODNAME, hw);
2107     if (ret < 0)
2108         return ret;
2109 
2110     rtlpci->using_msi = false;
2111     rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2112         "Pin-based Interrupt Mode!\n");
2113     return 0;
2114 }
2115 
2116 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2117 {
2118     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2119     struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2120     int ret;
2121 
2122     if (rtlpci->msi_support) {
2123         ret = rtl_pci_intr_mode_msi(hw);
2124         if (ret < 0)
2125             ret = rtl_pci_intr_mode_legacy(hw);
2126     } else {
2127         ret = rtl_pci_intr_mode_legacy(hw);
2128     }
2129     return ret;
2130 }
2131 
2132 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2133 {
2134     u8  value;
2135 
2136     pci_read_config_byte(pdev, 0x719, &value);
2137 
2138     /* 0x719 Bit5 is DMA64 bit fetch. */
2139     if (dma64)
2140         value |= BIT(5);
2141     else
2142         value &= ~BIT(5);
2143 
2144     pci_write_config_byte(pdev, 0x719, value);
2145 }
2146 
2147 int rtl_pci_probe(struct pci_dev *pdev,
2148           const struct pci_device_id *id)
2149 {
2150     struct ieee80211_hw *hw = NULL;
2151 
2152     struct rtl_priv *rtlpriv = NULL;
2153     struct rtl_pci_priv *pcipriv = NULL;
2154     struct rtl_pci *rtlpci;
2155     unsigned long pmem_start, pmem_len, pmem_flags;
2156     int err;
2157 
2158     err = pci_enable_device(pdev);
2159     if (err) {
2160         WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2161               pci_name(pdev));
2162         return err;
2163     }
2164 
2165     if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
2166         !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2167         if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2168             WARN_ONCE(true,
2169                   "Unable to obtain 64bit DMA for consistent allocations\n");
2170             err = -ENOMEM;
2171             goto fail1;
2172         }
2173 
2174         platform_enable_dma64(pdev, true);
2175     } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2176         if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2177             WARN_ONCE(true,
2178                   "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2179             err = -ENOMEM;
2180             goto fail1;
2181         }
2182 
2183         platform_enable_dma64(pdev, false);
2184     }
2185 
2186     pci_set_master(pdev);
2187 
2188     hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2189                 sizeof(struct rtl_priv), &rtl_ops);
2190     if (!hw) {
2191         WARN_ONCE(true,
2192               "%s : ieee80211 alloc failed\n", pci_name(pdev));
2193         err = -ENOMEM;
2194         goto fail1;
2195     }
2196 
2197     SET_IEEE80211_DEV(hw, &pdev->dev);
2198     pci_set_drvdata(pdev, hw);
2199 
2200     rtlpriv = hw->priv;
2201     rtlpriv->hw = hw;
2202     pcipriv = (void *)rtlpriv->priv;
2203     pcipriv->dev.pdev = pdev;
2204     init_completion(&rtlpriv->firmware_loading_complete);
2205     /*proximity init here*/
2206     rtlpriv->proximity.proxim_on = false;
2207 
2208     pcipriv = (void *)rtlpriv->priv;
2209     pcipriv->dev.pdev = pdev;
2210 
2211     /* init cfg & intf_ops */
2212     rtlpriv->rtlhal.interface = INTF_PCI;
2213     rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2214     rtlpriv->intf_ops = &rtl_pci_ops;
2215     rtlpriv->glb_var = &rtl_global_var;
2216     rtl_efuse_ops_init(hw);
2217 
2218     /* MEM map */
2219     err = pci_request_regions(pdev, KBUILD_MODNAME);
2220     if (err) {
2221         WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2222         goto fail1;
2223     }
2224 
2225     pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2226     pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2227     pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2228 
2229     /*shared mem start */
2230     rtlpriv->io.pci_mem_start =
2231             (unsigned long)pci_iomap(pdev,
2232             rtlpriv->cfg->bar_id, pmem_len);
2233     if (rtlpriv->io.pci_mem_start == 0) {
2234         WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2235         err = -ENOMEM;
2236         goto fail2;
2237     }
2238 
2239     rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2240         "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2241         pmem_start, pmem_len, pmem_flags,
2242         rtlpriv->io.pci_mem_start);
2243 
2244     /* Disable Clk Request */
2245     pci_write_config_byte(pdev, 0x81, 0);
2246     /* leave D3 mode */
2247     pci_write_config_byte(pdev, 0x44, 0);
2248     pci_write_config_byte(pdev, 0x04, 0x06);
2249     pci_write_config_byte(pdev, 0x04, 0x07);
2250 
2251     /* find adapter */
2252     if (!_rtl_pci_find_adapter(pdev, hw)) {
2253         err = -ENODEV;
2254         goto fail2;
2255     }
2256 
2257     /* Init IO handler */
2258     _rtl_pci_io_handler_init(&pdev->dev, hw);
2259 
2260     /*like read eeprom and so on */
2261     rtlpriv->cfg->ops->read_eeprom_info(hw);
2262 
2263     if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2264         pr_err("Can't init_sw_vars\n");
2265         err = -ENODEV;
2266         goto fail3;
2267     }
2268     rtlpriv->cfg->ops->init_sw_leds(hw);
2269 
2270     /*aspm */
2271     rtl_pci_init_aspm(hw);
2272 
2273     /* Init mac80211 sw */
2274     err = rtl_init_core(hw);
2275     if (err) {
2276         pr_err("Can't allocate sw for mac80211\n");
2277         goto fail3;
2278     }
2279 
2280     /* Init PCI sw */
2281     err = rtl_pci_init(hw, pdev);
2282     if (err) {
2283         pr_err("Failed to init PCI\n");
2284         goto fail3;
2285     }
2286 
2287     err = ieee80211_register_hw(hw);
2288     if (err) {
2289         pr_err("Can't register mac80211 hw.\n");
2290         err = -ENODEV;
2291         goto fail3;
2292     }
2293     rtlpriv->mac80211.mac80211_registered = 1;
2294 
2295     /* add for debug */
2296     rtl_debug_add_one(hw);
2297 
2298     /*init rfkill */
2299     rtl_init_rfkill(hw);    /* Init PCI sw */
2300 
2301     rtlpci = rtl_pcidev(pcipriv);
2302     err = rtl_pci_intr_mode_decide(hw);
2303     if (err) {
2304         rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2305             "%s: failed to register IRQ handler\n",
2306             wiphy_name(hw->wiphy));
2307         goto fail3;
2308     }
2309     rtlpci->irq_alloc = 1;
2310 
2311     set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2312     return 0;
2313 
2314 fail3:
2315     pci_set_drvdata(pdev, NULL);
2316     rtl_deinit_core(hw);
2317 
2318 fail2:
2319     if (rtlpriv->io.pci_mem_start != 0)
2320         pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2321 
2322     pci_release_regions(pdev);
2323     complete(&rtlpriv->firmware_loading_complete);
2324 
2325 fail1:
2326     if (hw)
2327         ieee80211_free_hw(hw);
2328     pci_disable_device(pdev);
2329 
2330     return err;
2331 }
2332 EXPORT_SYMBOL(rtl_pci_probe);
2333 
2334 void rtl_pci_disconnect(struct pci_dev *pdev)
2335 {
2336     struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2337     struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2338     struct rtl_priv *rtlpriv = rtl_priv(hw);
2339     struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2340     struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2341 
2342     /* just in case driver is removed before firmware callback */
2343     wait_for_completion(&rtlpriv->firmware_loading_complete);
2344     clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2345 
2346     /* remove form debug */
2347     rtl_debug_remove_one(hw);
2348 
2349     /*ieee80211_unregister_hw will call ops_stop */
2350     if (rtlmac->mac80211_registered == 1) {
2351         ieee80211_unregister_hw(hw);
2352         rtlmac->mac80211_registered = 0;
2353     } else {
2354         rtl_deinit_deferred_work(hw, false);
2355         rtlpriv->intf_ops->adapter_stop(hw);
2356     }
2357     rtlpriv->cfg->ops->disable_interrupt(hw);
2358 
2359     /*deinit rfkill */
2360     rtl_deinit_rfkill(hw);
2361 
2362     rtl_pci_deinit(hw);
2363     rtl_deinit_core(hw);
2364     rtlpriv->cfg->ops->deinit_sw_vars(hw);
2365 
2366     if (rtlpci->irq_alloc) {
2367         free_irq(rtlpci->pdev->irq, hw);
2368         rtlpci->irq_alloc = 0;
2369     }
2370 
2371     if (rtlpci->using_msi)
2372         pci_disable_msi(rtlpci->pdev);
2373 
2374     list_del(&rtlpriv->list);
2375     if (rtlpriv->io.pci_mem_start != 0) {
2376         pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2377         pci_release_regions(pdev);
2378     }
2379 
2380     pci_disable_device(pdev);
2381 
2382     rtl_pci_disable_aspm(hw);
2383 
2384     pci_set_drvdata(pdev, NULL);
2385 
2386     ieee80211_free_hw(hw);
2387 }
2388 EXPORT_SYMBOL(rtl_pci_disconnect);
2389 
2390 #ifdef CONFIG_PM_SLEEP
2391 /***************************************
2392  * kernel pci power state define:
2393  * PCI_D0         ((pci_power_t __force) 0)
2394  * PCI_D1         ((pci_power_t __force) 1)
2395  * PCI_D2         ((pci_power_t __force) 2)
2396  * PCI_D3hot      ((pci_power_t __force) 3)
2397  * PCI_D3cold     ((pci_power_t __force) 4)
2398  * PCI_UNKNOWN    ((pci_power_t __force) 5)
2399 
2400  * This function is called when system
2401  * goes into suspend state mac80211 will
2402  * call rtl_mac_stop() from the mac80211
2403  * suspend function first, So there is
2404  * no need to call hw_disable here.
2405  ****************************************/
2406 int rtl_pci_suspend(struct device *dev)
2407 {
2408     struct ieee80211_hw *hw = dev_get_drvdata(dev);
2409     struct rtl_priv *rtlpriv = rtl_priv(hw);
2410 
2411     rtlpriv->cfg->ops->hw_suspend(hw);
2412     rtl_deinit_rfkill(hw);
2413 
2414     return 0;
2415 }
2416 EXPORT_SYMBOL(rtl_pci_suspend);
2417 
2418 int rtl_pci_resume(struct device *dev)
2419 {
2420     struct ieee80211_hw *hw = dev_get_drvdata(dev);
2421     struct rtl_priv *rtlpriv = rtl_priv(hw);
2422 
2423     rtlpriv->cfg->ops->hw_resume(hw);
2424     rtl_init_rfkill(hw);
2425     return 0;
2426 }
2427 EXPORT_SYMBOL(rtl_pci_resume);
2428 #endif /* CONFIG_PM_SLEEP */
2429 
2430 const struct rtl_intf_ops rtl_pci_ops = {
2431     .read_efuse_byte = read_efuse_byte,
2432     .adapter_start = rtl_pci_start,
2433     .adapter_stop = rtl_pci_stop,
2434     .check_buddy_priv = rtl_pci_check_buddy_priv,
2435     .adapter_tx = rtl_pci_tx,
2436     .flush = rtl_pci_flush,
2437     .reset_trx_ring = rtl_pci_reset_trx_ring,
2438     .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2439 
2440     .disable_aspm = rtl_pci_disable_aspm,
2441     .enable_aspm = rtl_pci_enable_aspm,
2442 };
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