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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2012  Realtek Corporation.*/
0003 
0004 #ifndef __RTL_EFUSE_H_
0005 #define __RTL_EFUSE_H_
0006 
0007 #define EFUSE_IC_ID_OFFSET      506
0008 
0009 #define EFUSE_MAX_WORD_UNIT     4
0010 
0011 #define EFUSE_INIT_MAP          0
0012 #define EFUSE_MODIFY_MAP        1
0013 
0014 #define PG_STATE_HEADER         0x01
0015 #define PG_STATE_WORD_0         0x02
0016 #define PG_STATE_WORD_1         0x04
0017 #define PG_STATE_WORD_2         0x08
0018 #define PG_STATE_WORD_3         0x10
0019 #define PG_STATE_DATA           0x20
0020 
0021 #define EFUSE_REPEAT_THRESHOLD_     3
0022 #define EFUSE_ERROE_HANDLE      1
0023 
0024 struct efuse_map {
0025     u8 offset;
0026     u8 word_start;
0027     u8 byte_start;
0028     u8 byte_cnts;
0029 };
0030 
0031 struct pgpkt_struct {
0032     u8 offset;
0033     u8 word_en;
0034     u8 data[8];
0035 };
0036 
0037 enum efuse_data_item {
0038     EFUSE_CHIP_ID = 0,
0039     EFUSE_LDO_SETTING,
0040     EFUSE_CLK_SETTING,
0041     EFUSE_SDIO_SETTING,
0042     EFUSE_CCCR,
0043     EFUSE_SDIO_MODE,
0044     EFUSE_OCR,
0045     EFUSE_F0CIS,
0046     EFUSE_F1CIS,
0047     EFUSE_MAC_ADDR,
0048     EFUSE_EEPROM_VER,
0049     EFUSE_CHAN_PLAN,
0050     EFUSE_TXPW_TAB
0051 };
0052 
0053 enum {
0054     VOLTAGE_V25 = 0x03,
0055     LDOE25_SHIFT = 28,
0056 };
0057 
0058 struct efuse_priv {
0059     u8 id[2];
0060     u8 ldo_setting[2];
0061     u8 clk_setting[2];
0062     u8 cccr;
0063     u8 sdio_mode;
0064     u8 ocr[3];
0065     u8 cis0[17];
0066     u8 cis1[48];
0067     u8 mac_addr[6];
0068     u8 eeprom_verno;
0069     u8 channel_plan;
0070     u8 tx_power_b[14];
0071     u8 tx_power_g[14];
0072 };
0073 
0074 void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
0075 void efuse_initialize(struct ieee80211_hw *hw);
0076 u8 efuse_read_1byte(struct ieee80211_hw *hw, u16 address);
0077 int efuse_one_byte_read(struct ieee80211_hw *hw, u16 addr, u8 *data);
0078 void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value);
0079 void read_efuse(struct ieee80211_hw *hw, u16 _offset,
0080         u16 _size_byte, u8 *pbuf);
0081 void efuse_shadow_read(struct ieee80211_hw *hw, u8 type,
0082                u16 offset, u32 *value);
0083 void efuse_shadow_write(struct ieee80211_hw *hw, u8 type,
0084             u16 offset, u32 value);
0085 bool efuse_shadow_update(struct ieee80211_hw *hw);
0086 bool efuse_shadow_update_chk(struct ieee80211_hw *hw);
0087 void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw);
0088 void efuse_force_write_vendor_id(struct ieee80211_hw *hw);
0089 void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx);
0090 void efuse_power_switch(struct ieee80211_hw *hw, u8 write, u8 pwrstate);
0091 int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv,
0092            int max_size, u8 *hwinfo, int *params);
0093 void rtl_fill_dummy(u8 *pfwbuf, u32 *pfwlen);
0094 void rtl_fw_page_write(struct ieee80211_hw *hw, u32 page, const u8 *buffer,
0095                u32 size);
0096 void rtl_fw_block_write(struct ieee80211_hw *hw, const u8 *buffer, u32 size);
0097 void rtl_efuse_ops_init(struct ieee80211_hw *hw);
0098 #endif