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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * RTL8XXXU mac80211 USB driver
0004  *
0005  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
0006  *
0007  * Portions, notably calibration code:
0008  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
0009  *
0010  * This driver was written as a replacement for the vendor provided
0011  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
0012  * their programming interface, I have started adding support for
0013  * additional 8xxx chips like the 8192cu, 8188cus, etc.
0014  */
0015 
0016 #include <linux/init.h>
0017 #include <linux/kernel.h>
0018 #include <linux/sched.h>
0019 #include <linux/errno.h>
0020 #include <linux/slab.h>
0021 #include <linux/module.h>
0022 #include <linux/spinlock.h>
0023 #include <linux/list.h>
0024 #include <linux/usb.h>
0025 #include <linux/netdevice.h>
0026 #include <linux/etherdevice.h>
0027 #include <linux/ethtool.h>
0028 #include <linux/wireless.h>
0029 #include <linux/firmware.h>
0030 #include <linux/moduleparam.h>
0031 #include <net/mac80211.h>
0032 #include "rtl8xxxu.h"
0033 #include "rtl8xxxu_regs.h"
0034 
0035 #define DRIVER_NAME "rtl8xxxu"
0036 
0037 int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
0038 static bool rtl8xxxu_ht40_2g;
0039 static bool rtl8xxxu_dma_aggregation;
0040 static int rtl8xxxu_dma_agg_timeout = -1;
0041 static int rtl8xxxu_dma_agg_pages = -1;
0042 
0043 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>");
0044 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
0045 MODULE_LICENSE("GPL");
0046 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
0047 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
0048 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
0049 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
0050 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
0051 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
0052 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
0053 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
0054 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
0055 
0056 module_param_named(debug, rtl8xxxu_debug, int, 0600);
0057 MODULE_PARM_DESC(debug, "Set debug mask");
0058 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
0059 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
0060 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600);
0061 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation");
0062 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600);
0063 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)");
0064 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600);
0065 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)");
0066 
0067 #define USB_VENDOR_ID_REALTEK       0x0bda
0068 #define RTL8XXXU_RX_URBS        32
0069 #define RTL8XXXU_RX_URB_PENDING_WATER   8
0070 #define RTL8XXXU_TX_URBS        64
0071 #define RTL8XXXU_TX_URB_LOW_WATER   25
0072 #define RTL8XXXU_TX_URB_HIGH_WATER  32
0073 
0074 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
0075                   struct rtl8xxxu_rx_urb *rx_urb);
0076 
0077 static struct ieee80211_rate rtl8xxxu_rates[] = {
0078     { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
0079     { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
0080     { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
0081     { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
0082     { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
0083     { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
0084     { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
0085     { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
0086     { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
0087     { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
0088     { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
0089     { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
0090 };
0091 
0092 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
0093     { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
0094       .hw_value = 1, .max_power = 30 },
0095     { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
0096       .hw_value = 2, .max_power = 30 },
0097     { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
0098       .hw_value = 3, .max_power = 30 },
0099     { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
0100       .hw_value = 4, .max_power = 30 },
0101     { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
0102       .hw_value = 5, .max_power = 30 },
0103     { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
0104       .hw_value = 6, .max_power = 30 },
0105     { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
0106       .hw_value = 7, .max_power = 30 },
0107     { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
0108       .hw_value = 8, .max_power = 30 },
0109     { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
0110       .hw_value = 9, .max_power = 30 },
0111     { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
0112       .hw_value = 10, .max_power = 30 },
0113     { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
0114       .hw_value = 11, .max_power = 30 },
0115     { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
0116       .hw_value = 12, .max_power = 30 },
0117     { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
0118       .hw_value = 13, .max_power = 30 },
0119     { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
0120       .hw_value = 14, .max_power = 30 }
0121 };
0122 
0123 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
0124     .channels = rtl8xxxu_channels_2g,
0125     .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
0126     .bitrates = rtl8xxxu_rates,
0127     .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
0128 };
0129 
0130 struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = {
0131     {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
0132     {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
0133     {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
0134     {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
0135     {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
0136     {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
0137     {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
0138     {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
0139     {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
0140     {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
0141     {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
0142     {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
0143     {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
0144     {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
0145     {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
0146     {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
0147     {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
0148     {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
0149     {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
0150     {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
0151     {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
0152     {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
0153 };
0154 
0155 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
0156     {0x800, 0x80040000}, {0x804, 0x00000003},
0157     {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
0158     {0x810, 0x10001331}, {0x814, 0x020c3d10},
0159     {0x818, 0x02200385}, {0x81c, 0x00000000},
0160     {0x820, 0x01000100}, {0x824, 0x00390004},
0161     {0x828, 0x00000000}, {0x82c, 0x00000000},
0162     {0x830, 0x00000000}, {0x834, 0x00000000},
0163     {0x838, 0x00000000}, {0x83c, 0x00000000},
0164     {0x840, 0x00010000}, {0x844, 0x00000000},
0165     {0x848, 0x00000000}, {0x84c, 0x00000000},
0166     {0x850, 0x00000000}, {0x854, 0x00000000},
0167     {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
0168     {0x860, 0x66f60110}, {0x864, 0x061f0130},
0169     {0x868, 0x00000000}, {0x86c, 0x32323200},
0170     {0x870, 0x07000760}, {0x874, 0x22004000},
0171     {0x878, 0x00000808}, {0x87c, 0x00000000},
0172     {0x880, 0xc0083070}, {0x884, 0x000004d5},
0173     {0x888, 0x00000000}, {0x88c, 0xccc000c0},
0174     {0x890, 0x00000800}, {0x894, 0xfffffffe},
0175     {0x898, 0x40302010}, {0x89c, 0x00706050},
0176     {0x900, 0x00000000}, {0x904, 0x00000023},
0177     {0x908, 0x00000000}, {0x90c, 0x81121111},
0178     {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
0179     {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
0180     {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
0181     {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
0182     {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
0183     {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
0184     {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
0185     {0xa78, 0x00000900},
0186     {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
0187     {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
0188     {0xc10, 0x08800000}, {0xc14, 0x40000100},
0189     {0xc18, 0x08800000}, {0xc1c, 0x40000100},
0190     {0xc20, 0x00000000}, {0xc24, 0x00000000},
0191     {0xc28, 0x00000000}, {0xc2c, 0x00000000},
0192     {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
0193     {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
0194     {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
0195     {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
0196     {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
0197     {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
0198     {0xc60, 0x00000000}, {0xc64, 0x7112848b},
0199     {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
0200     {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
0201     {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
0202     {0xc80, 0x40000100}, {0xc84, 0x20f60000},
0203     {0xc88, 0x40000100}, {0xc8c, 0x20200000},
0204     {0xc90, 0x00121820}, {0xc94, 0x00000000},
0205     {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
0206     {0xca0, 0x00000000}, {0xca4, 0x00000080},
0207     {0xca8, 0x00000000}, {0xcac, 0x00000000},
0208     {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
0209     {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
0210     {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
0211     {0xcc8, 0x00000000}, {0xccc, 0x00000000},
0212     {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
0213     {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
0214     {0xce0, 0x00222222}, {0xce4, 0x00000000},
0215     {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
0216     {0xd00, 0x00080740}, {0xd04, 0x00020401},
0217     {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
0218     {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
0219     {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
0220     {0xd30, 0x00000000}, {0xd34, 0x80608000},
0221     {0xd38, 0x00000000}, {0xd3c, 0x00027293},
0222     {0xd40, 0x00000000}, {0xd44, 0x00000000},
0223     {0xd48, 0x00000000}, {0xd4c, 0x00000000},
0224     {0xd50, 0x6437140a}, {0xd54, 0x00000000},
0225     {0xd58, 0x00000000}, {0xd5c, 0x30032064},
0226     {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
0227     {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
0228     {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
0229     {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
0230     {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
0231     {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
0232     {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
0233     {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
0234     {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
0235     {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
0236     {0xe44, 0x01004800}, {0xe48, 0xfb000000},
0237     {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
0238     {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
0239     {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
0240     {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
0241     {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
0242     {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
0243     {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
0244     {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
0245     {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
0246     {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
0247     {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
0248     {0xf14, 0x00000003}, {0xf4c, 0x00000000},
0249     {0xf00, 0x00000300},
0250     {0xffff, 0xffffffff},
0251 };
0252 
0253 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
0254     {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
0255     {0x800, 0x80040002}, {0x804, 0x00000003},
0256     {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
0257     {0x810, 0x10000330}, {0x814, 0x020c3d10},
0258     {0x818, 0x02200385}, {0x81c, 0x00000000},
0259     {0x820, 0x01000100}, {0x824, 0x00390004},
0260     {0x828, 0x01000100}, {0x82c, 0x00390004},
0261     {0x830, 0x27272727}, {0x834, 0x27272727},
0262     {0x838, 0x27272727}, {0x83c, 0x27272727},
0263     {0x840, 0x00010000}, {0x844, 0x00010000},
0264     {0x848, 0x27272727}, {0x84c, 0x27272727},
0265     {0x850, 0x00000000}, {0x854, 0x00000000},
0266     {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
0267     {0x860, 0x66e60230}, {0x864, 0x061f0130},
0268     {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
0269     {0x870, 0x07000700}, {0x874, 0x22184000},
0270     {0x878, 0x08080808}, {0x87c, 0x00000000},
0271     {0x880, 0xc0083070}, {0x884, 0x000004d5},
0272     {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
0273     {0x890, 0x00000800}, {0x894, 0xfffffffe},
0274     {0x898, 0x40302010}, {0x89c, 0x00706050},
0275     {0x900, 0x00000000}, {0x904, 0x00000023},
0276     {0x908, 0x00000000}, {0x90c, 0x81121313},
0277     {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
0278     {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
0279     {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
0280     {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
0281     {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
0282     {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
0283     {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
0284     {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
0285     {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
0286     {0xc10, 0x08800000}, {0xc14, 0x40000100},
0287     {0xc18, 0x08800000}, {0xc1c, 0x40000100},
0288     {0xc20, 0x00000000}, {0xc24, 0x00000000},
0289     {0xc28, 0x00000000}, {0xc2c, 0x00000000},
0290     {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
0291     {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
0292     {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
0293     {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
0294     {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
0295     {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
0296     {0xc60, 0x00000000}, {0xc64, 0x5116848b},
0297     {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
0298     {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
0299     {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
0300     {0xc80, 0x40000100}, {0xc84, 0x20f60000},
0301     {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
0302     {0xc90, 0x00121820}, {0xc94, 0x00000000},
0303     {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
0304     {0xca0, 0x00000000}, {0xca4, 0x00000080},
0305     {0xca8, 0x00000000}, {0xcac, 0x00000000},
0306     {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
0307     {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
0308     {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
0309     {0xcc8, 0x00000000}, {0xccc, 0x00000000},
0310     {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
0311     {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
0312     {0xce0, 0x00222222}, {0xce4, 0x00000000},
0313     {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
0314     {0xd00, 0x00080740}, {0xd04, 0x00020403},
0315     {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
0316     {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
0317     {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
0318     {0xd30, 0x00000000}, {0xd34, 0x80608000},
0319     {0xd38, 0x00000000}, {0xd3c, 0x00027293},
0320     {0xd40, 0x00000000}, {0xd44, 0x00000000},
0321     {0xd48, 0x00000000}, {0xd4c, 0x00000000},
0322     {0xd50, 0x6437140a}, {0xd54, 0x00000000},
0323     {0xd58, 0x00000000}, {0xd5c, 0x30032064},
0324     {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
0325     {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
0326     {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
0327     {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
0328     {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
0329     {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
0330     {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
0331     {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
0332     {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
0333     {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
0334     {0xe44, 0x01004800}, {0xe48, 0xfb000000},
0335     {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
0336     {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
0337     {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
0338     {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
0339     {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
0340     {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
0341     {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
0342     {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
0343     {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
0344     {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
0345     {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
0346     {0xf14, 0x00000003}, {0xf4c, 0x00000000},
0347     {0xf00, 0x00000300},
0348     {0xffff, 0xffffffff},
0349 };
0350 
0351 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
0352     {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
0353     {0x040, 0x000c0004}, {0x800, 0x80040000},
0354     {0x804, 0x00000001}, {0x808, 0x0000fc00},
0355     {0x80c, 0x0000000a}, {0x810, 0x10005388},
0356     {0x814, 0x020c3d10}, {0x818, 0x02200385},
0357     {0x81c, 0x00000000}, {0x820, 0x01000100},
0358     {0x824, 0x00390204}, {0x828, 0x00000000},
0359     {0x82c, 0x00000000}, {0x830, 0x00000000},
0360     {0x834, 0x00000000}, {0x838, 0x00000000},
0361     {0x83c, 0x00000000}, {0x840, 0x00010000},
0362     {0x844, 0x00000000}, {0x848, 0x00000000},
0363     {0x84c, 0x00000000}, {0x850, 0x00000000},
0364     {0x854, 0x00000000}, {0x858, 0x569a569a},
0365     {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
0366     {0x864, 0x061f0130}, {0x868, 0x00000000},
0367     {0x86c, 0x20202000}, {0x870, 0x03000300},
0368     {0x874, 0x22004000}, {0x878, 0x00000808},
0369     {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
0370     {0x884, 0x000004d5}, {0x888, 0x00000000},
0371     {0x88c, 0xccc000c0}, {0x890, 0x00000800},
0372     {0x894, 0xfffffffe}, {0x898, 0x40302010},
0373     {0x89c, 0x00706050}, {0x900, 0x00000000},
0374     {0x904, 0x00000023}, {0x908, 0x00000000},
0375     {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
0376     {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
0377     {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
0378     {0xa14, 0x11144028}, {0xa18, 0x00881117},
0379     {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
0380     {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
0381     {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
0382     {0xa74, 0x00000007}, {0xc00, 0x48071d40},
0383     {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
0384     {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
0385     {0xc14, 0x40000100}, {0xc18, 0x08800000},
0386     {0xc1c, 0x40000100}, {0xc20, 0x00000000},
0387     {0xc24, 0x00000000}, {0xc28, 0x00000000},
0388     {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
0389     {0xc34, 0x469652cf}, {0xc38, 0x49795994},
0390     {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
0391     {0xc44, 0x000100b7}, {0xc48, 0xec020107},
0392     {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
0393     {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
0394     {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
0395     {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
0396     {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
0397     {0xc74, 0x018610db}, {0xc78, 0x0000001f},
0398     {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
0399     {0xc84, 0x20f60000}, {0xc88, 0x24000090},
0400     {0xc8c, 0x20200000}, {0xc90, 0x00121820},
0401     {0xc94, 0x00000000}, {0xc98, 0x00121820},
0402     {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
0403     {0xca4, 0x00000080}, {0xca8, 0x00000000},
0404     {0xcac, 0x00000000}, {0xcb0, 0x00000000},
0405     {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
0406     {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
0407     {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
0408     {0xccc, 0x00000000}, {0xcd0, 0x00000000},
0409     {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
0410     {0xcdc, 0x00766932}, {0xce0, 0x00222222},
0411     {0xce4, 0x00000000}, {0xce8, 0x37644302},
0412     {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
0413     {0xd04, 0x00020401}, {0xd08, 0x0000907f},
0414     {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
0415     {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
0416     {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
0417     {0xd34, 0x80608000}, {0xd38, 0x00000000},
0418     {0xd3c, 0x00027293}, {0xd40, 0x00000000},
0419     {0xd44, 0x00000000}, {0xd48, 0x00000000},
0420     {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
0421     {0xd54, 0x00000000}, {0xd58, 0x00000000},
0422     {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
0423     {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
0424     {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
0425     {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
0426     {0xe00, 0x24242424}, {0xe04, 0x24242424},
0427     {0xe08, 0x03902024}, {0xe10, 0x24242424},
0428     {0xe14, 0x24242424}, {0xe18, 0x24242424},
0429     {0xe1c, 0x24242424}, {0xe28, 0x00000000},
0430     {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
0431     {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
0432     {0xe40, 0x01007c00}, {0xe44, 0x01004800},
0433     {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
0434     {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
0435     {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
0436     {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
0437     {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
0438     {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
0439     {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
0440     {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
0441     {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
0442     {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
0443     {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
0444     {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
0445     {0xf14, 0x00000003}, {0xf4c, 0x00000000},
0446     {0xf00, 0x00000300},
0447     {0xffff, 0xffffffff},
0448 };
0449 
0450 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
0451     {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
0452     {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
0453     {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
0454     {0xc78, 0x7a060001}, {0xc78, 0x79070001},
0455     {0xc78, 0x78080001}, {0xc78, 0x77090001},
0456     {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
0457     {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
0458     {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
0459     {0xc78, 0x70100001}, {0xc78, 0x6f110001},
0460     {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
0461     {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
0462     {0xc78, 0x6a160001}, {0xc78, 0x69170001},
0463     {0xc78, 0x68180001}, {0xc78, 0x67190001},
0464     {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
0465     {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
0466     {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
0467     {0xc78, 0x60200001}, {0xc78, 0x49210001},
0468     {0xc78, 0x48220001}, {0xc78, 0x47230001},
0469     {0xc78, 0x46240001}, {0xc78, 0x45250001},
0470     {0xc78, 0x44260001}, {0xc78, 0x43270001},
0471     {0xc78, 0x42280001}, {0xc78, 0x41290001},
0472     {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
0473     {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
0474     {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
0475     {0xc78, 0x21300001}, {0xc78, 0x20310001},
0476     {0xc78, 0x06320001}, {0xc78, 0x05330001},
0477     {0xc78, 0x04340001}, {0xc78, 0x03350001},
0478     {0xc78, 0x02360001}, {0xc78, 0x01370001},
0479     {0xc78, 0x00380001}, {0xc78, 0x00390001},
0480     {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
0481     {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
0482     {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
0483     {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
0484     {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
0485     {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
0486     {0xc78, 0x7a460001}, {0xc78, 0x79470001},
0487     {0xc78, 0x78480001}, {0xc78, 0x77490001},
0488     {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
0489     {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
0490     {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
0491     {0xc78, 0x70500001}, {0xc78, 0x6f510001},
0492     {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
0493     {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
0494     {0xc78, 0x6a560001}, {0xc78, 0x69570001},
0495     {0xc78, 0x68580001}, {0xc78, 0x67590001},
0496     {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
0497     {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
0498     {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
0499     {0xc78, 0x60600001}, {0xc78, 0x49610001},
0500     {0xc78, 0x48620001}, {0xc78, 0x47630001},
0501     {0xc78, 0x46640001}, {0xc78, 0x45650001},
0502     {0xc78, 0x44660001}, {0xc78, 0x43670001},
0503     {0xc78, 0x42680001}, {0xc78, 0x41690001},
0504     {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
0505     {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
0506     {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
0507     {0xc78, 0x21700001}, {0xc78, 0x20710001},
0508     {0xc78, 0x06720001}, {0xc78, 0x05730001},
0509     {0xc78, 0x04740001}, {0xc78, 0x03750001},
0510     {0xc78, 0x02760001}, {0xc78, 0x01770001},
0511     {0xc78, 0x00780001}, {0xc78, 0x00790001},
0512     {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
0513     {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
0514     {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
0515     {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
0516     {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
0517     {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
0518     {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
0519     {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
0520     {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
0521     {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
0522     {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
0523     {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
0524     {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
0525     {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
0526     {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
0527     {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
0528     {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
0529     {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
0530     {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
0531     {0xffff, 0xffffffff}
0532 };
0533 
0534 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
0535     {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
0536     {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
0537     {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
0538     {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
0539     {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
0540     {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
0541     {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
0542     {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
0543     {0xc78, 0x73100001}, {0xc78, 0x72110001},
0544     {0xc78, 0x71120001}, {0xc78, 0x70130001},
0545     {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
0546     {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
0547     {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
0548     {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
0549     {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
0550     {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
0551     {0xc78, 0x63200001}, {0xc78, 0x62210001},
0552     {0xc78, 0x61220001}, {0xc78, 0x60230001},
0553     {0xc78, 0x46240001}, {0xc78, 0x45250001},
0554     {0xc78, 0x44260001}, {0xc78, 0x43270001},
0555     {0xc78, 0x42280001}, {0xc78, 0x41290001},
0556     {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
0557     {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
0558     {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
0559     {0xc78, 0x21300001}, {0xc78, 0x20310001},
0560     {0xc78, 0x06320001}, {0xc78, 0x05330001},
0561     {0xc78, 0x04340001}, {0xc78, 0x03350001},
0562     {0xc78, 0x02360001}, {0xc78, 0x01370001},
0563     {0xc78, 0x00380001}, {0xc78, 0x00390001},
0564     {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
0565     {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
0566     {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
0567     {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
0568     {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
0569     {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
0570     {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
0571     {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
0572     {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
0573     {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
0574     {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
0575     {0xc78, 0x73500001}, {0xc78, 0x72510001},
0576     {0xc78, 0x71520001}, {0xc78, 0x70530001},
0577     {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
0578     {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
0579     {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
0580     {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
0581     {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
0582     {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
0583     {0xc78, 0x63600001}, {0xc78, 0x62610001},
0584     {0xc78, 0x61620001}, {0xc78, 0x60630001},
0585     {0xc78, 0x46640001}, {0xc78, 0x45650001},
0586     {0xc78, 0x44660001}, {0xc78, 0x43670001},
0587     {0xc78, 0x42680001}, {0xc78, 0x41690001},
0588     {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
0589     {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
0590     {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
0591     {0xc78, 0x21700001}, {0xc78, 0x20710001},
0592     {0xc78, 0x06720001}, {0xc78, 0x05730001},
0593     {0xc78, 0x04740001}, {0xc78, 0x03750001},
0594     {0xc78, 0x02760001}, {0xc78, 0x01770001},
0595     {0xc78, 0x00780001}, {0xc78, 0x00790001},
0596     {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
0597     {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
0598     {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
0599     {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
0600     {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
0601     {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
0602     {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
0603     {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
0604     {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
0605     {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
0606     {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
0607     {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
0608     {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
0609     {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
0610     {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
0611     {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
0612     {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
0613     {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
0614     {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
0615     {0xffff, 0xffffffff}
0616 };
0617 
0618 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
0619     {   /* RF_A */
0620         .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
0621         .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
0622         .lssiparm = REG_FPGA0_XA_LSSI_PARM,
0623         .hspiread = REG_HSPI_XA_READBACK,
0624         .lssiread = REG_FPGA0_XA_LSSI_READBACK,
0625         .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
0626     },
0627     {   /* RF_B */
0628         .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
0629         .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
0630         .lssiparm = REG_FPGA0_XB_LSSI_PARM,
0631         .hspiread = REG_HSPI_XB_READBACK,
0632         .lssiread = REG_FPGA0_XB_LSSI_READBACK,
0633         .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
0634     },
0635 };
0636 
0637 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
0638     REG_OFDM0_XA_RX_IQ_IMBALANCE,
0639     REG_OFDM0_XB_RX_IQ_IMBALANCE,
0640     REG_OFDM0_ENERGY_CCA_THRES,
0641     REG_OFDM0_AGCR_SSI_TABLE,
0642     REG_OFDM0_XA_TX_IQ_IMBALANCE,
0643     REG_OFDM0_XB_TX_IQ_IMBALANCE,
0644     REG_OFDM0_XC_TX_AFE,
0645     REG_OFDM0_XD_TX_AFE,
0646     REG_OFDM0_RX_IQ_EXT_ANTA
0647 };
0648 
0649 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
0650 {
0651     struct usb_device *udev = priv->udev;
0652     int len;
0653     u8 data;
0654 
0655     mutex_lock(&priv->usb_buf_mutex);
0656     len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
0657                   REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
0658                   addr, 0, &priv->usb_buf.val8, sizeof(u8),
0659                   RTW_USB_CONTROL_MSG_TIMEOUT);
0660     data = priv->usb_buf.val8;
0661     mutex_unlock(&priv->usb_buf_mutex);
0662 
0663     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
0664         dev_info(&udev->dev, "%s(%04x)   = 0x%02x, len %i\n",
0665              __func__, addr, data, len);
0666     return data;
0667 }
0668 
0669 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
0670 {
0671     struct usb_device *udev = priv->udev;
0672     int len;
0673     u16 data;
0674 
0675     mutex_lock(&priv->usb_buf_mutex);
0676     len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
0677                   REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
0678                   addr, 0, &priv->usb_buf.val16, sizeof(u16),
0679                   RTW_USB_CONTROL_MSG_TIMEOUT);
0680     data = le16_to_cpu(priv->usb_buf.val16);
0681     mutex_unlock(&priv->usb_buf_mutex);
0682 
0683     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
0684         dev_info(&udev->dev, "%s(%04x)  = 0x%04x, len %i\n",
0685              __func__, addr, data, len);
0686     return data;
0687 }
0688 
0689 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
0690 {
0691     struct usb_device *udev = priv->udev;
0692     int len;
0693     u32 data;
0694 
0695     mutex_lock(&priv->usb_buf_mutex);
0696     len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
0697                   REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
0698                   addr, 0, &priv->usb_buf.val32, sizeof(u32),
0699                   RTW_USB_CONTROL_MSG_TIMEOUT);
0700     data = le32_to_cpu(priv->usb_buf.val32);
0701     mutex_unlock(&priv->usb_buf_mutex);
0702 
0703     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
0704         dev_info(&udev->dev, "%s(%04x)  = 0x%08x, len %i\n",
0705              __func__, addr, data, len);
0706     return data;
0707 }
0708 
0709 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
0710 {
0711     struct usb_device *udev = priv->udev;
0712     int ret;
0713 
0714     mutex_lock(&priv->usb_buf_mutex);
0715     priv->usb_buf.val8 = val;
0716     ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
0717                   REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
0718                   addr, 0, &priv->usb_buf.val8, sizeof(u8),
0719                   RTW_USB_CONTROL_MSG_TIMEOUT);
0720 
0721     mutex_unlock(&priv->usb_buf_mutex);
0722 
0723     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
0724         dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
0725              __func__, addr, val);
0726     return ret;
0727 }
0728 
0729 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
0730 {
0731     struct usb_device *udev = priv->udev;
0732     int ret;
0733 
0734     mutex_lock(&priv->usb_buf_mutex);
0735     priv->usb_buf.val16 = cpu_to_le16(val);
0736     ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
0737                   REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
0738                   addr, 0, &priv->usb_buf.val16, sizeof(u16),
0739                   RTW_USB_CONTROL_MSG_TIMEOUT);
0740     mutex_unlock(&priv->usb_buf_mutex);
0741 
0742     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
0743         dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
0744              __func__, addr, val);
0745     return ret;
0746 }
0747 
0748 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
0749 {
0750     struct usb_device *udev = priv->udev;
0751     int ret;
0752 
0753     mutex_lock(&priv->usb_buf_mutex);
0754     priv->usb_buf.val32 = cpu_to_le32(val);
0755     ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
0756                   REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
0757                   addr, 0, &priv->usb_buf.val32, sizeof(u32),
0758                   RTW_USB_CONTROL_MSG_TIMEOUT);
0759     mutex_unlock(&priv->usb_buf_mutex);
0760 
0761     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
0762         dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
0763              __func__, addr, val);
0764     return ret;
0765 }
0766 
0767 static int
0768 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
0769 {
0770     struct usb_device *udev = priv->udev;
0771     int blocksize = priv->fops->writeN_block_size;
0772     int ret, i, count, remainder;
0773 
0774     count = len / blocksize;
0775     remainder = len % blocksize;
0776 
0777     for (i = 0; i < count; i++) {
0778         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
0779                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
0780                       addr, 0, buf, blocksize,
0781                       RTW_USB_CONTROL_MSG_TIMEOUT);
0782         if (ret != blocksize)
0783             goto write_error;
0784 
0785         addr += blocksize;
0786         buf += blocksize;
0787     }
0788 
0789     if (remainder) {
0790         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
0791                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
0792                       addr, 0, buf, remainder,
0793                       RTW_USB_CONTROL_MSG_TIMEOUT);
0794         if (ret != remainder)
0795             goto write_error;
0796     }
0797 
0798     return len;
0799 
0800 write_error:
0801     dev_info(&udev->dev,
0802          "%s: Failed to write block at addr: %04x size: %04x\n",
0803          __func__, addr, blocksize);
0804     return -EAGAIN;
0805 }
0806 
0807 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
0808             enum rtl8xxxu_rfpath path, u8 reg)
0809 {
0810     u32 hssia, val32, retval;
0811 
0812     hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
0813     if (path != RF_A)
0814         val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
0815     else
0816         val32 = hssia;
0817 
0818     val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
0819     val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
0820     val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
0821     hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
0822     rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
0823 
0824     udelay(10);
0825 
0826     rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
0827     udelay(100);
0828 
0829     hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
0830     rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
0831     udelay(10);
0832 
0833     val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
0834     if (val32 & FPGA0_HSSI_PARM1_PI)
0835         retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
0836     else
0837         retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
0838 
0839     retval &= 0xfffff;
0840 
0841     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
0842         dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
0843              __func__, reg, retval);
0844     return retval;
0845 }
0846 
0847 /*
0848  * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
0849  * have write issues in high temperature conditions. We may have to
0850  * retry writing them.
0851  */
0852 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
0853              enum rtl8xxxu_rfpath path, u8 reg, u32 data)
0854 {
0855     int ret, retval;
0856     u32 dataaddr, val32;
0857 
0858     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
0859         dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
0860              __func__, reg, data);
0861 
0862     data &= FPGA0_LSSI_PARM_DATA_MASK;
0863     dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
0864 
0865     if (priv->rtl_chip == RTL8192E) {
0866         val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
0867         val32 &= ~0x20000;
0868         rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
0869     }
0870 
0871     /* Use XB for path B */
0872     ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
0873     if (ret != sizeof(dataaddr))
0874         retval = -EIO;
0875     else
0876         retval = 0;
0877 
0878     udelay(1);
0879 
0880     if (priv->rtl_chip == RTL8192E) {
0881         val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
0882         val32 |= 0x20000;
0883         rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
0884     }
0885 
0886     return retval;
0887 }
0888 
0889 static int
0890 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
0891 {
0892     struct device *dev = &priv->udev->dev;
0893     int mbox_nr, retry, retval = 0;
0894     int mbox_reg, mbox_ext_reg;
0895     u8 val8;
0896 
0897     mutex_lock(&priv->h2c_mutex);
0898 
0899     mbox_nr = priv->next_mbox;
0900     mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
0901     mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
0902 
0903     /*
0904      * MBOX ready?
0905      */
0906     retry = 100;
0907     do {
0908         val8 = rtl8xxxu_read8(priv, REG_HMTFR);
0909         if (!(val8 & BIT(mbox_nr)))
0910             break;
0911     } while (retry--);
0912 
0913     if (!retry) {
0914         dev_info(dev, "%s: Mailbox busy\n", __func__);
0915         retval = -EBUSY;
0916         goto error;
0917     }
0918 
0919     /*
0920      * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
0921      */
0922     if (len > sizeof(u32)) {
0923         rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext));
0924         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
0925             dev_info(dev, "H2C_EXT %04x\n",
0926                  le16_to_cpu(h2c->raw.ext));
0927     }
0928     rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
0929     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
0930         dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
0931 
0932     priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
0933 
0934 error:
0935     mutex_unlock(&priv->h2c_mutex);
0936     return retval;
0937 }
0938 
0939 int
0940 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
0941 {
0942     struct device *dev = &priv->udev->dev;
0943     int mbox_nr, retry, retval = 0;
0944     int mbox_reg, mbox_ext_reg;
0945     u8 val8;
0946 
0947     mutex_lock(&priv->h2c_mutex);
0948 
0949     mbox_nr = priv->next_mbox;
0950     mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
0951     mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4);
0952 
0953     /*
0954      * MBOX ready?
0955      */
0956     retry = 100;
0957     do {
0958         val8 = rtl8xxxu_read8(priv, REG_HMTFR);
0959         if (!(val8 & BIT(mbox_nr)))
0960             break;
0961     } while (retry--);
0962 
0963     if (!retry) {
0964         dev_info(dev, "%s: Mailbox busy\n", __func__);
0965         retval = -EBUSY;
0966         goto error;
0967     }
0968 
0969     /*
0970      * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
0971      */
0972     if (len > sizeof(u32)) {
0973         rtl8xxxu_write32(priv, mbox_ext_reg,
0974                  le32_to_cpu(h2c->raw_wide.ext));
0975         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
0976             dev_info(dev, "H2C_EXT %08x\n",
0977                  le32_to_cpu(h2c->raw_wide.ext));
0978     }
0979     rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
0980     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
0981         dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
0982 
0983     priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
0984 
0985 error:
0986     mutex_unlock(&priv->h2c_mutex);
0987     return retval;
0988 }
0989 
0990 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv)
0991 {
0992     u8 val8;
0993     u32 val32;
0994 
0995     val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
0996     val8 |= BIT(0) | BIT(3);
0997     rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
0998 
0999     val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1000     val32 &= ~(BIT(4) | BIT(5));
1001     val32 |= BIT(3);
1002     if (priv->rf_paths == 2) {
1003         val32 &= ~(BIT(20) | BIT(21));
1004         val32 |= BIT(19);
1005     }
1006     rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1007 
1008     val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1009     val32 &= ~OFDM_RF_PATH_TX_MASK;
1010     if (priv->tx_paths == 2)
1011         val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1012     else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
1013         val32 |= OFDM_RF_PATH_TX_B;
1014     else
1015         val32 |= OFDM_RF_PATH_TX_A;
1016     rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1017 
1018     val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1019     val32 &= ~FPGA_RF_MODE_JAPAN;
1020     rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1021 
1022     if (priv->rf_paths == 2)
1023         rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1024     else
1025         rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1026 
1027     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1028     if (priv->rf_paths == 2)
1029         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1030 
1031     rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1032 }
1033 
1034 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv)
1035 {
1036     u8 sps0;
1037     u32 val32;
1038 
1039     sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1040 
1041     /* RF RX code for preamble power saving */
1042     val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1043     val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1044     if (priv->rf_paths == 2)
1045         val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1046     rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1047 
1048     /* Disable TX for four paths */
1049     val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1050     val32 &= ~OFDM_RF_PATH_TX_MASK;
1051     rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1052 
1053     /* Enable power saving */
1054     val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1055     val32 |= FPGA_RF_MODE_JAPAN;
1056     rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1057 
1058     /* AFE control register to power down bits [30:22] */
1059     if (priv->rf_paths == 2)
1060         rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1061     else
1062         rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1063 
1064     /* Power down RF module */
1065     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1066     if (priv->rf_paths == 2)
1067         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1068 
1069     sps0 &= ~(BIT(0) | BIT(3));
1070     rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1071 }
1072 
1073 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1074 {
1075     u8 val8;
1076 
1077     val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1078     val8 &= ~BIT(6);
1079     rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1080 
1081     rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1082     val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1083     val8 &= ~BIT(0);
1084     rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1085 }
1086 
1087 
1088 /*
1089  * The rtl8723a has 3 channel groups for it's efuse settings. It only
1090  * supports the 2.4GHz band, so channels 1 - 14:
1091  *  group 0: channels 1 - 3
1092  *  group 1: channels 4 - 9
1093  *  group 2: channels 10 - 14
1094  *
1095  * Note: We index from 0 in the code
1096  */
1097 static int rtl8xxxu_gen1_channel_to_group(int channel)
1098 {
1099     int group;
1100 
1101     if (channel < 4)
1102         group = 0;
1103     else if (channel < 10)
1104         group = 1;
1105     else
1106         group = 2;
1107 
1108     return group;
1109 }
1110 
1111 /*
1112  * Valid for rtl8723bu and rtl8192eu
1113  */
1114 int rtl8xxxu_gen2_channel_to_group(int channel)
1115 {
1116     int group;
1117 
1118     if (channel < 3)
1119         group = 0;
1120     else if (channel < 6)
1121         group = 1;
1122     else if (channel < 9)
1123         group = 2;
1124     else if (channel < 12)
1125         group = 3;
1126     else
1127         group = 4;
1128 
1129     return group;
1130 }
1131 
1132 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw)
1133 {
1134     struct rtl8xxxu_priv *priv = hw->priv;
1135     u32 val32, rsr;
1136     u8 val8, opmode;
1137     bool ht = true;
1138     int sec_ch_above, channel;
1139     int i;
1140 
1141     opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1142     rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1143     channel = hw->conf.chandef.chan->hw_value;
1144 
1145     switch (hw->conf.chandef.width) {
1146     case NL80211_CHAN_WIDTH_20_NOHT:
1147         ht = false;
1148         fallthrough;
1149     case NL80211_CHAN_WIDTH_20:
1150         opmode |= BW_OPMODE_20MHZ;
1151         rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1152 
1153         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1154         val32 &= ~FPGA_RF_MODE;
1155         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1156 
1157         val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1158         val32 &= ~FPGA_RF_MODE;
1159         rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1160 
1161         val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1162         val32 |= FPGA0_ANALOG2_20MHZ;
1163         rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1164         break;
1165     case NL80211_CHAN_WIDTH_40:
1166         if (hw->conf.chandef.center_freq1 >
1167             hw->conf.chandef.chan->center_freq) {
1168             sec_ch_above = 1;
1169             channel += 2;
1170         } else {
1171             sec_ch_above = 0;
1172             channel -= 2;
1173         }
1174 
1175         opmode &= ~BW_OPMODE_20MHZ;
1176         rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1177         rsr &= ~RSR_RSC_BANDWIDTH_40M;
1178         if (sec_ch_above)
1179             rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1180         else
1181             rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1182         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1183 
1184         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1185         val32 |= FPGA_RF_MODE;
1186         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1187 
1188         val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1189         val32 |= FPGA_RF_MODE;
1190         rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1191 
1192         /*
1193          * Set Control channel to upper or lower. These settings
1194          * are required only for 40MHz
1195          */
1196         val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1197         val32 &= ~CCK0_SIDEBAND;
1198         if (!sec_ch_above)
1199             val32 |= CCK0_SIDEBAND;
1200         rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1201 
1202         val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1203         val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1204         if (sec_ch_above)
1205             val32 |= OFDM_LSTF_PRIME_CH_LOW;
1206         else
1207             val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1208         rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1209 
1210         val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1211         val32 &= ~FPGA0_ANALOG2_20MHZ;
1212         rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1213 
1214         val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1215         val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1216         if (sec_ch_above)
1217             val32 |= FPGA0_PS_UPPER_CHANNEL;
1218         else
1219             val32 |= FPGA0_PS_LOWER_CHANNEL;
1220         rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1221         break;
1222 
1223     default:
1224         break;
1225     }
1226 
1227     for (i = RF_A; i < priv->rf_paths; i++) {
1228         val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1229         val32 &= ~MODE_AG_CHANNEL_MASK;
1230         val32 |= channel;
1231         rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1232     }
1233 
1234     if (ht)
1235         val8 = 0x0e;
1236     else
1237         val8 = 0x0a;
1238 
1239     rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1240     rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1241 
1242     rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1243     rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1244 
1245     for (i = RF_A; i < priv->rf_paths; i++) {
1246         val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1247         if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1248             val32 &= ~MODE_AG_CHANNEL_20MHZ;
1249         else
1250             val32 |= MODE_AG_CHANNEL_20MHZ;
1251         rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1252     }
1253 }
1254 
1255 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw)
1256 {
1257     struct rtl8xxxu_priv *priv = hw->priv;
1258     u32 val32;
1259     u8 val8, subchannel;
1260     u16 rf_mode_bw;
1261     bool ht = true;
1262     int sec_ch_above, channel;
1263     int i;
1264 
1265     rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1266     rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1267     channel = hw->conf.chandef.chan->hw_value;
1268 
1269 /* Hack */
1270     subchannel = 0;
1271 
1272     switch (hw->conf.chandef.width) {
1273     case NL80211_CHAN_WIDTH_20_NOHT:
1274         ht = false;
1275         fallthrough;
1276     case NL80211_CHAN_WIDTH_20:
1277         rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1278         subchannel = 0;
1279 
1280         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1281         val32 &= ~FPGA_RF_MODE;
1282         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1283 
1284         val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1285         val32 &= ~FPGA_RF_MODE;
1286         rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1287 
1288         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1289         val32 &= ~(BIT(30) | BIT(31));
1290         rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1291 
1292         break;
1293     case NL80211_CHAN_WIDTH_40:
1294         rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1295 
1296         if (hw->conf.chandef.center_freq1 >
1297             hw->conf.chandef.chan->center_freq) {
1298             sec_ch_above = 1;
1299             channel += 2;
1300         } else {
1301             sec_ch_above = 0;
1302             channel -= 2;
1303         }
1304 
1305         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1306         val32 |= FPGA_RF_MODE;
1307         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1308 
1309         val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1310         val32 |= FPGA_RF_MODE;
1311         rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1312 
1313         /*
1314          * Set Control channel to upper or lower. These settings
1315          * are required only for 40MHz
1316          */
1317         val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1318         val32 &= ~CCK0_SIDEBAND;
1319         if (!sec_ch_above)
1320             val32 |= CCK0_SIDEBAND;
1321         rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1322 
1323         val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1324         val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1325         if (sec_ch_above)
1326             val32 |= OFDM_LSTF_PRIME_CH_LOW;
1327         else
1328             val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1329         rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1330 
1331         val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1332         val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1333         if (sec_ch_above)
1334             val32 |= FPGA0_PS_UPPER_CHANNEL;
1335         else
1336             val32 |= FPGA0_PS_LOWER_CHANNEL;
1337         rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1338         break;
1339     case NL80211_CHAN_WIDTH_80:
1340         rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1341         break;
1342     default:
1343         break;
1344     }
1345 
1346     for (i = RF_A; i < priv->rf_paths; i++) {
1347         val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1348         val32 &= ~MODE_AG_CHANNEL_MASK;
1349         val32 |= channel;
1350         rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1351     }
1352 
1353     rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1354     rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1355 
1356     if (ht)
1357         val8 = 0x0e;
1358     else
1359         val8 = 0x0a;
1360 
1361     rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1362     rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1363 
1364     rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1365     rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1366 
1367     for (i = RF_A; i < priv->rf_paths; i++) {
1368         val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1369         val32 &= ~MODE_AG_BW_MASK;
1370         switch(hw->conf.chandef.width) {
1371         case NL80211_CHAN_WIDTH_80:
1372             val32 |= MODE_AG_BW_80MHZ_8723B;
1373             break;
1374         case NL80211_CHAN_WIDTH_40:
1375             val32 |= MODE_AG_BW_40MHZ_8723B;
1376             break;
1377         default:
1378             val32 |= MODE_AG_BW_20MHZ_8723B;
1379             break;
1380         }
1381         rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1382     }
1383 }
1384 
1385 void
1386 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1387 {
1388     struct rtl8xxxu_power_base *power_base = priv->power_base;
1389     u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1390     u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1391     u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1392     u8 val8;
1393     int group, i;
1394 
1395     group = rtl8xxxu_gen1_channel_to_group(channel);
1396 
1397     cck[0] = priv->cck_tx_power_index_A[group] - 1;
1398     cck[1] = priv->cck_tx_power_index_B[group] - 1;
1399 
1400     if (priv->hi_pa) {
1401         if (cck[0] > 0x20)
1402             cck[0] = 0x20;
1403         if (cck[1] > 0x20)
1404             cck[1] = 0x20;
1405     }
1406 
1407     ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1408     ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1409     if (ofdm[0])
1410         ofdm[0] -= 1;
1411     if (ofdm[1])
1412         ofdm[1] -= 1;
1413 
1414     ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1415     ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1416 
1417     mcsbase[0] = ofdm[0];
1418     mcsbase[1] = ofdm[1];
1419     if (!ht40) {
1420         mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1421         mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1422     }
1423 
1424     if (priv->tx_paths > 1) {
1425         if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1426             ofdm[0] -=  priv->ht40_2s_tx_power_index_diff[group].a;
1427         if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1428             ofdm[1] -=  priv->ht40_2s_tx_power_index_diff[group].b;
1429     }
1430 
1431     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1432         dev_info(&priv->udev->dev,
1433              "%s: Setting TX power CCK A: %02x, "
1434              "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1435              __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1436 
1437     for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1438         if (cck[i] > RF6052_MAX_TX_PWR)
1439             cck[i] = RF6052_MAX_TX_PWR;
1440         if (ofdm[i] > RF6052_MAX_TX_PWR)
1441             ofdm[i] = RF6052_MAX_TX_PWR;
1442     }
1443 
1444     val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1445     val32 &= 0xffff00ff;
1446     val32 |= (cck[0] << 8);
1447     rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1448 
1449     val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1450     val32 &= 0xff;
1451     val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1452     rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1453 
1454     val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1455     val32 &= 0xffffff00;
1456     val32 |= cck[1];
1457     rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1458 
1459     val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1460     val32 &= 0xff;
1461     val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1462     rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1463 
1464     ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1465         ofdmbase[0] << 16 | ofdmbase[0] << 24;
1466     ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1467         ofdmbase[1] << 16 | ofdmbase[1] << 24;
1468 
1469     rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06,
1470              ofdm_a + power_base->reg_0e00);
1471     rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06,
1472              ofdm_b + power_base->reg_0830);
1473 
1474     rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24,
1475              ofdm_a + power_base->reg_0e04);
1476     rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24,
1477              ofdm_b + power_base->reg_0834);
1478 
1479     mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1480         mcsbase[0] << 16 | mcsbase[0] << 24;
1481     mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1482         mcsbase[1] << 16 | mcsbase[1] << 24;
1483 
1484     rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00,
1485              mcs_a + power_base->reg_0e10);
1486     rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00,
1487              mcs_b + power_base->reg_083c);
1488 
1489     rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04,
1490              mcs_a + power_base->reg_0e14);
1491     rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04,
1492              mcs_b + power_base->reg_0848);
1493 
1494     rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08,
1495              mcs_a + power_base->reg_0e18);
1496     rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08,
1497              mcs_b + power_base->reg_084c);
1498 
1499     rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12,
1500              mcs_a + power_base->reg_0e1c);
1501     for (i = 0; i < 3; i++) {
1502         if (i != 2)
1503             val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1504         else
1505             val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1506         rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1507     }
1508     rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12,
1509              mcs_b + power_base->reg_0868);
1510     for (i = 0; i < 3; i++) {
1511         if (i != 2)
1512             val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1513         else
1514             val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1515         rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1516     }
1517 }
1518 
1519 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1520                   enum nl80211_iftype linktype)
1521 {
1522     u8 val8;
1523 
1524     val8 = rtl8xxxu_read8(priv, REG_MSR);
1525     val8 &= ~MSR_LINKTYPE_MASK;
1526 
1527     switch (linktype) {
1528     case NL80211_IFTYPE_UNSPECIFIED:
1529         val8 |= MSR_LINKTYPE_NONE;
1530         break;
1531     case NL80211_IFTYPE_ADHOC:
1532         val8 |= MSR_LINKTYPE_ADHOC;
1533         break;
1534     case NL80211_IFTYPE_STATION:
1535         val8 |= MSR_LINKTYPE_STATION;
1536         break;
1537     case NL80211_IFTYPE_AP:
1538         val8 |= MSR_LINKTYPE_AP;
1539         break;
1540     default:
1541         goto out;
1542     }
1543 
1544     rtl8xxxu_write8(priv, REG_MSR, val8);
1545 out:
1546     return;
1547 }
1548 
1549 static void
1550 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1551 {
1552     u16 val16;
1553 
1554     val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1555          RETRY_LIMIT_SHORT_MASK) |
1556         ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1557          RETRY_LIMIT_LONG_MASK);
1558 
1559     rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1560 }
1561 
1562 static void
1563 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1564 {
1565     u16 val16;
1566 
1567     val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1568         ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1569 
1570     rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1571 }
1572 
1573 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1574 {
1575     struct device *dev = &priv->udev->dev;
1576     char *cut;
1577 
1578     switch (priv->chip_cut) {
1579     case 0:
1580         cut = "A";
1581         break;
1582     case 1:
1583         cut = "B";
1584         break;
1585     case 2:
1586         cut = "C";
1587         break;
1588     case 3:
1589         cut = "D";
1590         break;
1591     case 4:
1592         cut = "E";
1593         break;
1594     default:
1595         cut = "unknown";
1596     }
1597 
1598     dev_info(dev,
1599          "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1600          priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1601          priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1602          priv->has_bluetooth, priv->has_gps, priv->hi_pa);
1603 
1604     dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1605 }
1606 
1607 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1608 {
1609     struct device *dev = &priv->udev->dev;
1610     struct ieee80211_hw *hw = priv->hw;
1611     u32 val32, bonding;
1612     u16 val16;
1613 
1614     val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1615     priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1616         SYS_CFG_CHIP_VERSION_SHIFT;
1617     if (val32 & SYS_CFG_TRP_VAUX_EN) {
1618         dev_info(dev, "Unsupported test chip\n");
1619         return -ENOTSUPP;
1620     }
1621 
1622     if (val32 & SYS_CFG_BT_FUNC) {
1623         if (priv->chip_cut >= 3) {
1624             sprintf(priv->chip_name, "8723BU");
1625             priv->rtl_chip = RTL8723B;
1626         } else {
1627             sprintf(priv->chip_name, "8723AU");
1628             priv->usb_interrupts = 1;
1629             priv->rtl_chip = RTL8723A;
1630         }
1631 
1632         priv->rf_paths = 1;
1633         priv->rx_paths = 1;
1634         priv->tx_paths = 1;
1635 
1636         val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1637         if (val32 & MULTI_WIFI_FUNC_EN)
1638             priv->has_wifi = 1;
1639         if (val32 & MULTI_BT_FUNC_EN)
1640             priv->has_bluetooth = 1;
1641         if (val32 & MULTI_GPS_FUNC_EN)
1642             priv->has_gps = 1;
1643         priv->is_multi_func = 1;
1644     } else if (val32 & SYS_CFG_TYPE_ID) {
1645         bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1646         bonding &= HPON_FSM_BONDING_MASK;
1647         if (priv->fops->tx_desc_size ==
1648             sizeof(struct rtl8xxxu_txdesc40)) {
1649             if (bonding == HPON_FSM_BONDING_1T2R) {
1650                 sprintf(priv->chip_name, "8191EU");
1651                 priv->rf_paths = 2;
1652                 priv->rx_paths = 2;
1653                 priv->tx_paths = 1;
1654                 priv->rtl_chip = RTL8191E;
1655             } else {
1656                 sprintf(priv->chip_name, "8192EU");
1657                 priv->rf_paths = 2;
1658                 priv->rx_paths = 2;
1659                 priv->tx_paths = 2;
1660                 priv->rtl_chip = RTL8192E;
1661             }
1662         } else if (bonding == HPON_FSM_BONDING_1T2R) {
1663             sprintf(priv->chip_name, "8191CU");
1664             priv->rf_paths = 2;
1665             priv->rx_paths = 2;
1666             priv->tx_paths = 1;
1667             priv->usb_interrupts = 1;
1668             priv->rtl_chip = RTL8191C;
1669         } else {
1670             sprintf(priv->chip_name, "8192CU");
1671             priv->rf_paths = 2;
1672             priv->rx_paths = 2;
1673             priv->tx_paths = 2;
1674             priv->usb_interrupts = 0;
1675             priv->rtl_chip = RTL8192C;
1676         }
1677         priv->has_wifi = 1;
1678     } else {
1679         sprintf(priv->chip_name, "8188CU");
1680         priv->rf_paths = 1;
1681         priv->rx_paths = 1;
1682         priv->tx_paths = 1;
1683         priv->rtl_chip = RTL8188C;
1684         priv->usb_interrupts = 0;
1685         priv->has_wifi = 1;
1686     }
1687 
1688     hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1;
1689     hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1;
1690 
1691     switch (priv->rtl_chip) {
1692     case RTL8188E:
1693     case RTL8192E:
1694     case RTL8723B:
1695         switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
1696         case SYS_CFG_VENDOR_ID_TSMC:
1697             sprintf(priv->chip_vendor, "TSMC");
1698             break;
1699         case SYS_CFG_VENDOR_ID_SMIC:
1700             sprintf(priv->chip_vendor, "SMIC");
1701             priv->vendor_smic = 1;
1702             break;
1703         case SYS_CFG_VENDOR_ID_UMC:
1704             sprintf(priv->chip_vendor, "UMC");
1705             priv->vendor_umc = 1;
1706             break;
1707         default:
1708             sprintf(priv->chip_vendor, "unknown");
1709         }
1710         break;
1711     default:
1712         if (val32 & SYS_CFG_VENDOR_ID) {
1713             sprintf(priv->chip_vendor, "UMC");
1714             priv->vendor_umc = 1;
1715         } else {
1716             sprintf(priv->chip_vendor, "TSMC");
1717         }
1718     }
1719 
1720     val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1721     priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1722 
1723     val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1724     if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1725         priv->ep_tx_high_queue = 1;
1726         priv->ep_tx_count++;
1727     }
1728 
1729     if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1730         priv->ep_tx_normal_queue = 1;
1731         priv->ep_tx_count++;
1732     }
1733 
1734     if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1735         priv->ep_tx_low_queue = 1;
1736         priv->ep_tx_count++;
1737     }
1738 
1739     /*
1740      * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1741      */
1742     if (!priv->ep_tx_count) {
1743         switch (priv->nr_out_eps) {
1744         case 4:
1745         case 3:
1746             priv->ep_tx_low_queue = 1;
1747             priv->ep_tx_count++;
1748             fallthrough;
1749         case 2:
1750             priv->ep_tx_normal_queue = 1;
1751             priv->ep_tx_count++;
1752             fallthrough;
1753         case 1:
1754             priv->ep_tx_high_queue = 1;
1755             priv->ep_tx_count++;
1756             break;
1757         default:
1758             dev_info(dev, "Unsupported USB TX end-points\n");
1759             return -ENOTSUPP;
1760         }
1761     }
1762 
1763     return 0;
1764 }
1765 
1766 static int
1767 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1768 {
1769     int i;
1770     u8 val8;
1771     u32 val32;
1772 
1773     /* Write Address */
1774     rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1775     val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1776     val8 &= 0xfc;
1777     val8 |= (offset >> 8) & 0x03;
1778     rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1779 
1780     val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1781     rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1782 
1783     /* Poll for data read */
1784     val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1785     for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1786         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1787         if (val32 & BIT(31))
1788             break;
1789     }
1790 
1791     if (i == RTL8XXXU_MAX_REG_POLL)
1792         return -EIO;
1793 
1794     udelay(50);
1795     val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1796 
1797     *data = val32 & 0xff;
1798     return 0;
1799 }
1800 
1801 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1802 {
1803     struct device *dev = &priv->udev->dev;
1804     int i, ret = 0;
1805     u8 val8, word_mask, header, extheader;
1806     u16 val16, efuse_addr, offset;
1807     u32 val32;
1808 
1809     val16 = rtl8xxxu_read16(priv, REG_9346CR);
1810     if (val16 & EEPROM_ENABLE)
1811         priv->has_eeprom = 1;
1812     if (val16 & EEPROM_BOOT)
1813         priv->boot_eeprom = 1;
1814 
1815     if (priv->is_multi_func) {
1816         val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1817         val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1818         rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1819     }
1820 
1821     dev_dbg(dev, "Booting from %s\n",
1822         priv->boot_eeprom ? "EEPROM" : "EFUSE");
1823 
1824     rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1825 
1826     /*  1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1827     val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1828     if (!(val16 & SYS_ISO_PWC_EV12V)) {
1829         val16 |= SYS_ISO_PWC_EV12V;
1830         rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1831     }
1832     /*  Reset: 0x0000[28], default valid */
1833     val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1834     if (!(val16 & SYS_FUNC_ELDR)) {
1835         val16 |= SYS_FUNC_ELDR;
1836         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1837     }
1838 
1839     /*
1840      * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1841      */
1842     val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1843     if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1844         val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1845         rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1846     }
1847 
1848     /* Default value is 0xff */
1849     memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
1850 
1851     efuse_addr = 0;
1852     while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1853         u16 map_addr;
1854 
1855         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1856         if (ret || header == 0xff)
1857             goto exit;
1858 
1859         if ((header & 0x1f) == 0x0f) {  /* extended header */
1860             offset = (header & 0xe0) >> 5;
1861 
1862             ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1863                            &extheader);
1864             if (ret)
1865                 goto exit;
1866             /* All words disabled */
1867             if ((extheader & 0x0f) == 0x0f)
1868                 continue;
1869 
1870             offset |= ((extheader & 0xf0) >> 1);
1871             word_mask = extheader & 0x0f;
1872         } else {
1873             offset = (header >> 4) & 0x0f;
1874             word_mask = header & 0x0f;
1875         }
1876 
1877         /* Get word enable value from PG header */
1878 
1879         /* We have 8 bits to indicate validity */
1880         map_addr = offset * 8;
1881         if (map_addr >= EFUSE_MAP_LEN) {
1882             dev_warn(dev, "%s: Illegal map_addr (%04x), "
1883                  "efuse corrupt!\n",
1884                  __func__, map_addr);
1885             ret = -EINVAL;
1886             goto exit;
1887         }
1888         for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1889             /* Check word enable condition in the section */
1890             if (word_mask & BIT(i)) {
1891                 map_addr += 2;
1892                 continue;
1893             }
1894 
1895             ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1896             if (ret)
1897                 goto exit;
1898             priv->efuse_wifi.raw[map_addr++] = val8;
1899 
1900             ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1901             if (ret)
1902                 goto exit;
1903             priv->efuse_wifi.raw[map_addr++] = val8;
1904         }
1905     }
1906 
1907 exit:
1908     rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
1909 
1910     return ret;
1911 }
1912 
1913 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
1914 {
1915     u8 val8;
1916     u16 sys_func;
1917 
1918     val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1919     val8 &= ~BIT(0);
1920     rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1921 
1922     sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1923     sys_func &= ~SYS_FUNC_CPU_ENABLE;
1924     rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1925 
1926     val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1927     val8 |= BIT(0);
1928     rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1929 
1930     sys_func |= SYS_FUNC_CPU_ENABLE;
1931     rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1932 }
1933 
1934 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
1935 {
1936     struct device *dev = &priv->udev->dev;
1937     int ret = 0, i;
1938     u32 val32;
1939 
1940     /* Poll checksum report */
1941     for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1942         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1943         if (val32 & MCU_FW_DL_CSUM_REPORT)
1944             break;
1945     }
1946 
1947     if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1948         dev_warn(dev, "Firmware checksum poll timed out\n");
1949         ret = -EAGAIN;
1950         goto exit;
1951     }
1952 
1953     val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1954     val32 |= MCU_FW_DL_READY;
1955     val32 &= ~MCU_WINT_INIT_READY;
1956     rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
1957 
1958     /*
1959      * Reset the 8051 in order for the firmware to start running,
1960      * otherwise it won't come up on the 8192eu
1961      */
1962     priv->fops->reset_8051(priv);
1963 
1964     /* Wait for firmware to become ready */
1965     for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1966         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1967         if (val32 & MCU_WINT_INIT_READY)
1968             break;
1969 
1970         udelay(100);
1971     }
1972 
1973     if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1974         dev_warn(dev, "Firmware failed to start\n");
1975         ret = -EAGAIN;
1976         goto exit;
1977     }
1978 
1979     /*
1980      * Init H2C command
1981      */
1982     if (priv->rtl_chip == RTL8723B)
1983         rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
1984 exit:
1985     return ret;
1986 }
1987 
1988 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
1989 {
1990     int pages, remainder, i, ret;
1991     u8 val8;
1992     u16 val16;
1993     u32 val32;
1994     u8 *fwptr;
1995 
1996     val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
1997     val8 |= 4;
1998     rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
1999 
2000     /* 8051 enable */
2001     val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2002     val16 |= SYS_FUNC_CPU_ENABLE;
2003     rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2004 
2005     val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2006     if (val8 & MCU_FW_RAM_SEL) {
2007         pr_info("do the RAM reset\n");
2008         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2009         priv->fops->reset_8051(priv);
2010     }
2011 
2012     /* MCU firmware download enable */
2013     val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2014     val8 |= MCU_FW_DL_ENABLE;
2015     rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2016 
2017     /* 8051 reset */
2018     val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2019     val32 &= ~BIT(19);
2020     rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2021 
2022     /* Reset firmware download checksum */
2023     val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2024     val8 |= MCU_FW_DL_CSUM_REPORT;
2025     rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2026 
2027     pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2028     remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2029 
2030     fwptr = priv->fw_data->data;
2031 
2032     for (i = 0; i < pages; i++) {
2033         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2034         val8 |= i;
2035         rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2036 
2037         ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2038                       fwptr, RTL_FW_PAGE_SIZE);
2039         if (ret != RTL_FW_PAGE_SIZE) {
2040             ret = -EAGAIN;
2041             goto fw_abort;
2042         }
2043 
2044         fwptr += RTL_FW_PAGE_SIZE;
2045     }
2046 
2047     if (remainder) {
2048         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2049         val8 |= i;
2050         rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2051         ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2052                       fwptr, remainder);
2053         if (ret != remainder) {
2054             ret = -EAGAIN;
2055             goto fw_abort;
2056         }
2057     }
2058 
2059     ret = 0;
2060 fw_abort:
2061     /* MCU firmware download disable */
2062     val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2063     val16 &= ~MCU_FW_DL_ENABLE;
2064     rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2065 
2066     return ret;
2067 }
2068 
2069 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2070 {
2071     struct device *dev = &priv->udev->dev;
2072     const struct firmware *fw;
2073     int ret = 0;
2074     u16 signature;
2075 
2076     dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2077     if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2078         dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2079         ret = -EAGAIN;
2080         goto exit;
2081     }
2082     if (!fw) {
2083         dev_warn(dev, "Firmware data not available\n");
2084         ret = -EINVAL;
2085         goto exit;
2086     }
2087 
2088     priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2089     if (!priv->fw_data) {
2090         ret = -ENOMEM;
2091         goto exit;
2092     }
2093     priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2094 
2095     signature = le16_to_cpu(priv->fw_data->signature);
2096     switch (signature & 0xfff0) {
2097     case 0x92e0:
2098     case 0x92c0:
2099     case 0x88c0:
2100     case 0x5300:
2101     case 0x2300:
2102         break;
2103     default:
2104         ret = -EINVAL;
2105         dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2106              __func__, signature);
2107     }
2108 
2109     dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2110          le16_to_cpu(priv->fw_data->major_version),
2111          priv->fw_data->minor_version, signature);
2112 
2113 exit:
2114     release_firmware(fw);
2115     return ret;
2116 }
2117 
2118 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2119 {
2120     u16 val16;
2121     int i = 100;
2122 
2123     /* Inform 8051 to perform reset */
2124     rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2125 
2126     for (i = 100; i > 0; i--) {
2127         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2128 
2129         if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2130             dev_dbg(&priv->udev->dev,
2131                 "%s: Firmware self reset success!\n", __func__);
2132             break;
2133         }
2134         udelay(50);
2135     }
2136 
2137     if (!i) {
2138         /* Force firmware reset */
2139         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2140         val16 &= ~SYS_FUNC_CPU_ENABLE;
2141         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2142     }
2143 }
2144 
2145 static int
2146 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
2147 {
2148     struct rtl8xxxu_reg8val *array = priv->fops->mactable;
2149     int i, ret;
2150     u16 reg;
2151     u8 val;
2152 
2153     for (i = 0; ; i++) {
2154         reg = array[i].reg;
2155         val = array[i].val;
2156 
2157         if (reg == 0xffff && val == 0xff)
2158             break;
2159 
2160         ret = rtl8xxxu_write8(priv, reg, val);
2161         if (ret != 1) {
2162             dev_warn(&priv->udev->dev,
2163                  "Failed to initialize MAC "
2164                  "(reg: %04x, val %02x)\n", reg, val);
2165             return -EAGAIN;
2166         }
2167     }
2168 
2169     if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
2170         rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2171 
2172     return 0;
2173 }
2174 
2175 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2176                struct rtl8xxxu_reg32val *array)
2177 {
2178     int i, ret;
2179     u16 reg;
2180     u32 val;
2181 
2182     for (i = 0; ; i++) {
2183         reg = array[i].reg;
2184         val = array[i].val;
2185 
2186         if (reg == 0xffff && val == 0xffffffff)
2187             break;
2188 
2189         ret = rtl8xxxu_write32(priv, reg, val);
2190         if (ret != sizeof(val)) {
2191             dev_warn(&priv->udev->dev,
2192                  "Failed to initialize PHY\n");
2193             return -EAGAIN;
2194         }
2195         udelay(1);
2196     }
2197 
2198     return 0;
2199 }
2200 
2201 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv)
2202 {
2203     u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2204     u16 val16;
2205     u32 val32;
2206 
2207     val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2208     udelay(2);
2209     val8 |= AFE_PLL_320_ENABLE;
2210     rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2211     udelay(2);
2212 
2213     rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2214     udelay(2);
2215 
2216     val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2217     val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2218     rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2219 
2220     val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2221     val32 &= ~AFE_XTAL_RF_GATE;
2222     if (priv->has_bluetooth)
2223         val32 &= ~AFE_XTAL_BT_GATE;
2224     rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2225 
2226     /* 6. 0x1f[7:0] = 0x07 */
2227     val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2228     rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2229 
2230     if (priv->hi_pa)
2231         rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2232     else if (priv->tx_paths == 2)
2233         rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2234     else
2235         rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2236 
2237     if (priv->rtl_chip == RTL8188R && priv->hi_pa &&
2238         priv->vendor_umc && priv->chip_cut == 1)
2239         rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2240 
2241     if (priv->hi_pa)
2242         rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2243     else
2244         rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2245 
2246     ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2247     ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2248     ldohci12 = 0x57;
2249     lpldo = 1;
2250     val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2251     rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2252 }
2253 
2254 /*
2255  * Most of this is black magic retrieved from the old rtl8723au driver
2256  */
2257 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2258 {
2259     u8 val8;
2260     u32 val32;
2261 
2262     priv->fops->init_phy_bb(priv);
2263 
2264     if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2265         /*
2266          * For 1T2R boards, patch the registers.
2267          *
2268          * It looks like 8191/2 1T2R boards use path B for TX
2269          */
2270         val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2271         val32 &= ~(BIT(0) | BIT(1));
2272         val32 |= BIT(1);
2273         rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2274 
2275         val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2276         val32 &= ~0x300033;
2277         val32 |= 0x200022;
2278         rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2279 
2280         val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2281         val32 &= ~CCK0_AFE_RX_MASK;
2282         val32 &= 0x00ffffff;
2283         val32 |= 0x40000000;
2284         val32 |= CCK0_AFE_RX_ANT_B;
2285         rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2286 
2287         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2288         val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2289         val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2290               OFDM_RF_PATH_TX_B);
2291         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2292 
2293         val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2294         val32 &= ~(BIT(4) | BIT(5));
2295         val32 |= BIT(4);
2296         rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2297 
2298         val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2299         val32 &= ~(BIT(27) | BIT(26));
2300         val32 |= BIT(27);
2301         rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2302 
2303         val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2304         val32 &= ~(BIT(27) | BIT(26));
2305         val32 |= BIT(27);
2306         rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2307 
2308         val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2309         val32 &= ~(BIT(27) | BIT(26));
2310         val32 |= BIT(27);
2311         rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2312 
2313         val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2314         val32 &= ~(BIT(27) | BIT(26));
2315         val32 |= BIT(27);
2316         rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2317 
2318         val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2319         val32 &= ~(BIT(27) | BIT(26));
2320         val32 |= BIT(27);
2321         rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2322     }
2323 
2324     if (priv->has_xtalk) {
2325         val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2326 
2327         val8 = priv->xtalk;
2328         val32 &= 0xff000fff;
2329         val32 |= ((val8 | (val8 << 6)) << 12);
2330 
2331         rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2332     }
2333 
2334     if (priv->rtl_chip == RTL8192E)
2335         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);
2336 
2337     return 0;
2338 }
2339 
2340 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2341                  struct rtl8xxxu_rfregval *array,
2342                  enum rtl8xxxu_rfpath path)
2343 {
2344     int i, ret;
2345     u8 reg;
2346     u32 val;
2347 
2348     for (i = 0; ; i++) {
2349         reg = array[i].reg;
2350         val = array[i].val;
2351 
2352         if (reg == 0xff && val == 0xffffffff)
2353             break;
2354 
2355         switch (reg) {
2356         case 0xfe:
2357             msleep(50);
2358             continue;
2359         case 0xfd:
2360             mdelay(5);
2361             continue;
2362         case 0xfc:
2363             mdelay(1);
2364             continue;
2365         case 0xfb:
2366             udelay(50);
2367             continue;
2368         case 0xfa:
2369             udelay(5);
2370             continue;
2371         case 0xf9:
2372             udelay(1);
2373             continue;
2374         }
2375 
2376         ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2377         if (ret) {
2378             dev_warn(&priv->udev->dev,
2379                  "Failed to initialize RF\n");
2380             return -EAGAIN;
2381         }
2382         udelay(1);
2383     }
2384 
2385     return 0;
2386 }
2387 
2388 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2389              struct rtl8xxxu_rfregval *table,
2390              enum rtl8xxxu_rfpath path)
2391 {
2392     u32 val32;
2393     u16 val16, rfsi_rfenv;
2394     u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2395 
2396     switch (path) {
2397     case RF_A:
2398         reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2399         reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2400         reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2401         break;
2402     case RF_B:
2403         reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2404         reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2405         reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2406         break;
2407     default:
2408         dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2409             __func__, path + 'A');
2410         return -EINVAL;
2411     }
2412     /* For path B, use XB */
2413     rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2414     rfsi_rfenv &= FPGA0_RF_RFENV;
2415 
2416     /*
2417      * These two we might be able to optimize into one
2418      */
2419     val32 = rtl8xxxu_read32(priv, reg_int_oe);
2420     val32 |= BIT(20);   /* 0x10 << 16 */
2421     rtl8xxxu_write32(priv, reg_int_oe, val32);
2422     udelay(1);
2423 
2424     val32 = rtl8xxxu_read32(priv, reg_int_oe);
2425     val32 |= BIT(4);
2426     rtl8xxxu_write32(priv, reg_int_oe, val32);
2427     udelay(1);
2428 
2429     /*
2430      * These two we might be able to optimize into one
2431      */
2432     val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2433     val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2434     rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2435     udelay(1);
2436 
2437     val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2438     val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2439     rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2440     udelay(1);
2441 
2442     rtl8xxxu_init_rf_regs(priv, table, path);
2443 
2444     /* For path B, use XB */
2445     val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2446     val16 &= ~FPGA0_RF_RFENV;
2447     val16 |= rfsi_rfenv;
2448     rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2449 
2450     return 0;
2451 }
2452 
2453 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2454 {
2455     int ret = -EBUSY;
2456     int count = 0;
2457     u32 value;
2458 
2459     value = LLT_OP_WRITE | address << 8 | data;
2460 
2461     rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2462 
2463     do {
2464         value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2465         if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2466             ret = 0;
2467             break;
2468         }
2469     } while (count++ < 20);
2470 
2471     return ret;
2472 }
2473 
2474 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv)
2475 {
2476     int ret;
2477     int i;
2478     u8 last_tx_page;
2479 
2480     last_tx_page = priv->fops->total_page_num;
2481 
2482     for (i = 0; i < last_tx_page; i++) {
2483         ret = rtl8xxxu_llt_write(priv, i, i + 1);
2484         if (ret)
2485             goto exit;
2486     }
2487 
2488     ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2489     if (ret)
2490         goto exit;
2491 
2492     /* Mark remaining pages as a ring buffer */
2493     for (i = last_tx_page + 1; i < 0xff; i++) {
2494         ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2495         if (ret)
2496             goto exit;
2497     }
2498 
2499     /*  Let last entry point to the start entry of ring buffer */
2500     ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2501     if (ret)
2502         goto exit;
2503 
2504 exit:
2505     return ret;
2506 }
2507 
2508 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv)
2509 {
2510     u32 val32;
2511     int ret = 0;
2512     int i;
2513 
2514     val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2515     val32 |= AUTO_LLT_INIT_LLT;
2516     rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
2517 
2518     for (i = 500; i; i--) {
2519         val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2520         if (!(val32 & AUTO_LLT_INIT_LLT))
2521             break;
2522         usleep_range(2, 4);
2523     }
2524 
2525     if (!i) {
2526         ret = -EBUSY;
2527         dev_warn(&priv->udev->dev, "LLT table init failed\n");
2528     }
2529 
2530     return ret;
2531 }
2532 
2533 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2534 {
2535     u16 val16, hi, lo;
2536     u16 hiq, mgq, bkq, beq, viq, voq;
2537     int hip, mgp, bkp, bep, vip, vop;
2538     int ret = 0;
2539 
2540     switch (priv->ep_tx_count) {
2541     case 1:
2542         if (priv->ep_tx_high_queue) {
2543             hi = TRXDMA_QUEUE_HIGH;
2544         } else if (priv->ep_tx_low_queue) {
2545             hi = TRXDMA_QUEUE_LOW;
2546         } else if (priv->ep_tx_normal_queue) {
2547             hi = TRXDMA_QUEUE_NORMAL;
2548         } else {
2549             hi = 0;
2550             ret = -EINVAL;
2551         }
2552 
2553         hiq = hi;
2554         mgq = hi;
2555         bkq = hi;
2556         beq = hi;
2557         viq = hi;
2558         voq = hi;
2559 
2560         hip = 0;
2561         mgp = 0;
2562         bkp = 0;
2563         bep = 0;
2564         vip = 0;
2565         vop = 0;
2566         break;
2567     case 2:
2568         if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2569             hi = TRXDMA_QUEUE_HIGH;
2570             lo = TRXDMA_QUEUE_LOW;
2571         } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2572             hi = TRXDMA_QUEUE_NORMAL;
2573             lo = TRXDMA_QUEUE_LOW;
2574         } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2575             hi = TRXDMA_QUEUE_HIGH;
2576             lo = TRXDMA_QUEUE_NORMAL;
2577         } else {
2578             ret = -EINVAL;
2579             hi = 0;
2580             lo = 0;
2581         }
2582 
2583         hiq = hi;
2584         mgq = hi;
2585         bkq = lo;
2586         beq = lo;
2587         viq = hi;
2588         voq = hi;
2589 
2590         hip = 0;
2591         mgp = 0;
2592         bkp = 1;
2593         bep = 1;
2594         vip = 0;
2595         vop = 0;
2596         break;
2597     case 3:
2598         beq = TRXDMA_QUEUE_LOW;
2599         bkq = TRXDMA_QUEUE_LOW;
2600         viq = TRXDMA_QUEUE_NORMAL;
2601         voq = TRXDMA_QUEUE_HIGH;
2602         mgq = TRXDMA_QUEUE_HIGH;
2603         hiq = TRXDMA_QUEUE_HIGH;
2604 
2605         hip = hiq ^ 3;
2606         mgp = mgq ^ 3;
2607         bkp = bkq ^ 3;
2608         bep = beq ^ 3;
2609         vip = viq ^ 3;
2610         vop = viq ^ 3;
2611         break;
2612     default:
2613         ret = -EINVAL;
2614     }
2615 
2616     /*
2617      * None of the vendor drivers are configuring the beacon
2618      * queue here .... why?
2619      */
2620     if (!ret) {
2621         val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2622         val16 &= 0x7;
2623         val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2624             (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2625             (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2626             (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2627             (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2628             (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2629         rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2630 
2631         priv->pipe_out[TXDESC_QUEUE_VO] =
2632             usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2633         priv->pipe_out[TXDESC_QUEUE_VI] =
2634             usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2635         priv->pipe_out[TXDESC_QUEUE_BE] =
2636             usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2637         priv->pipe_out[TXDESC_QUEUE_BK] =
2638             usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2639         priv->pipe_out[TXDESC_QUEUE_BEACON] =
2640             usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2641         priv->pipe_out[TXDESC_QUEUE_MGNT] =
2642             usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2643         priv->pipe_out[TXDESC_QUEUE_HIGH] =
2644             usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2645         priv->pipe_out[TXDESC_QUEUE_CMD] =
2646             usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2647     }
2648 
2649     return ret;
2650 }
2651 
2652 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
2653                 int result[][8], int candidate, bool tx_only)
2654 {
2655     u32 oldval, x, tx0_a, reg;
2656     int y, tx0_c;
2657     u32 val32;
2658 
2659     if (!iqk_ok)
2660         return;
2661 
2662     val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2663     oldval = val32 >> 22;
2664 
2665     x = result[candidate][0];
2666     if ((x & 0x00000200) != 0)
2667         x = x | 0xfffffc00;
2668     tx0_a = (x * oldval) >> 8;
2669 
2670     val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2671     val32 &= ~0x3ff;
2672     val32 |= tx0_a;
2673     rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2674 
2675     val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2676     val32 &= ~BIT(31);
2677     if ((x * oldval >> 7) & 0x1)
2678         val32 |= BIT(31);
2679     rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2680 
2681     y = result[candidate][1];
2682     if ((y & 0x00000200) != 0)
2683         y = y | 0xfffffc00;
2684     tx0_c = (y * oldval) >> 8;
2685 
2686     val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2687     val32 &= ~0xf0000000;
2688     val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2689     rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2690 
2691     val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2692     val32 &= ~0x003f0000;
2693     val32 |= ((tx0_c & 0x3f) << 16);
2694     rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2695 
2696     val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2697     val32 &= ~BIT(29);
2698     if ((y * oldval >> 7) & 0x1)
2699         val32 |= BIT(29);
2700     rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2701 
2702     if (tx_only) {
2703         dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2704         return;
2705     }
2706 
2707     reg = result[candidate][2];
2708 
2709     val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2710     val32 &= ~0x3ff;
2711     val32 |= (reg & 0x3ff);
2712     rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2713 
2714     reg = result[candidate][3] & 0x3F;
2715 
2716     val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2717     val32 &= ~0xfc00;
2718     val32 |= ((reg << 10) & 0xfc00);
2719     rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2720 
2721     reg = (result[candidate][3] >> 6) & 0xF;
2722 
2723     val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2724     val32 &= ~0xf0000000;
2725     val32 |= (reg << 28);
2726     rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2727 }
2728 
2729 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
2730                 int result[][8], int candidate, bool tx_only)
2731 {
2732     u32 oldval, x, tx1_a, reg;
2733     int y, tx1_c;
2734     u32 val32;
2735 
2736     if (!iqk_ok)
2737         return;
2738 
2739     val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2740     oldval = val32 >> 22;
2741 
2742     x = result[candidate][4];
2743     if ((x & 0x00000200) != 0)
2744         x = x | 0xfffffc00;
2745     tx1_a = (x * oldval) >> 8;
2746 
2747     val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2748     val32 &= ~0x3ff;
2749     val32 |= tx1_a;
2750     rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2751 
2752     val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2753     val32 &= ~BIT(27);
2754     if ((x * oldval >> 7) & 0x1)
2755         val32 |= BIT(27);
2756     rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2757 
2758     y = result[candidate][5];
2759     if ((y & 0x00000200) != 0)
2760         y = y | 0xfffffc00;
2761     tx1_c = (y * oldval) >> 8;
2762 
2763     val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2764     val32 &= ~0xf0000000;
2765     val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2766     rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2767 
2768     val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2769     val32 &= ~0x003f0000;
2770     val32 |= ((tx1_c & 0x3f) << 16);
2771     rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2772 
2773     val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2774     val32 &= ~BIT(25);
2775     if ((y * oldval >> 7) & 0x1)
2776         val32 |= BIT(25);
2777     rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2778 
2779     if (tx_only) {
2780         dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2781         return;
2782     }
2783 
2784     reg = result[candidate][6];
2785 
2786     val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2787     val32 &= ~0x3ff;
2788     val32 |= (reg & 0x3ff);
2789     rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2790 
2791     reg = result[candidate][7] & 0x3f;
2792 
2793     val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2794     val32 &= ~0xfc00;
2795     val32 |= ((reg << 10) & 0xfc00);
2796     rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2797 
2798     reg = (result[candidate][7] >> 6) & 0xf;
2799 
2800     val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
2801     val32 &= ~0x0000f000;
2802     val32 |= (reg << 12);
2803     rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
2804 }
2805 
2806 #define MAX_TOLERANCE       5
2807 
2808 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2809                     int result[][8], int c1, int c2)
2810 {
2811     u32 i, j, diff, simubitmap, bound = 0;
2812     int candidate[2] = {-1, -1};    /* for path A and path B */
2813     bool retval = true;
2814 
2815     if (priv->tx_paths > 1)
2816         bound = 8;
2817     else
2818         bound = 4;
2819 
2820     simubitmap = 0;
2821 
2822     for (i = 0; i < bound; i++) {
2823         diff = (result[c1][i] > result[c2][i]) ?
2824             (result[c1][i] - result[c2][i]) :
2825             (result[c2][i] - result[c1][i]);
2826         if (diff > MAX_TOLERANCE) {
2827             if ((i == 2 || i == 6) && !simubitmap) {
2828                 if (result[c1][i] + result[c1][i + 1] == 0)
2829                     candidate[(i / 4)] = c2;
2830                 else if (result[c2][i] + result[c2][i + 1] == 0)
2831                     candidate[(i / 4)] = c1;
2832                 else
2833                     simubitmap = simubitmap | (1 << i);
2834             } else {
2835                 simubitmap = simubitmap | (1 << i);
2836             }
2837         }
2838     }
2839 
2840     if (simubitmap == 0) {
2841         for (i = 0; i < (bound / 4); i++) {
2842             if (candidate[i] >= 0) {
2843                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2844                     result[3][j] = result[candidate[i]][j];
2845                 retval = false;
2846             }
2847         }
2848         return retval;
2849     } else if (!(simubitmap & 0x0f)) {
2850         /* path A OK */
2851         for (i = 0; i < 4; i++)
2852             result[3][i] = result[c1][i];
2853     } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2854         /* path B OK */
2855         for (i = 4; i < 8; i++)
2856             result[3][i] = result[c1][i];
2857     }
2858 
2859     return false;
2860 }
2861 
2862 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
2863                       int result[][8], int c1, int c2)
2864 {
2865     u32 i, j, diff, simubitmap, bound = 0;
2866     int candidate[2] = {-1, -1};    /* for path A and path B */
2867     int tmp1, tmp2;
2868     bool retval = true;
2869 
2870     if (priv->tx_paths > 1)
2871         bound = 8;
2872     else
2873         bound = 4;
2874 
2875     simubitmap = 0;
2876 
2877     for (i = 0; i < bound; i++) {
2878         if (i & 1) {
2879             if ((result[c1][i] & 0x00000200))
2880                 tmp1 = result[c1][i] | 0xfffffc00;
2881             else
2882                 tmp1 = result[c1][i];
2883 
2884             if ((result[c2][i]& 0x00000200))
2885                 tmp2 = result[c2][i] | 0xfffffc00;
2886             else
2887                 tmp2 = result[c2][i];
2888         } else {
2889             tmp1 = result[c1][i];
2890             tmp2 = result[c2][i];
2891         }
2892 
2893         diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2894 
2895         if (diff > MAX_TOLERANCE) {
2896             if ((i == 2 || i == 6) && !simubitmap) {
2897                 if (result[c1][i] + result[c1][i + 1] == 0)
2898                     candidate[(i / 4)] = c2;
2899                 else if (result[c2][i] + result[c2][i + 1] == 0)
2900                     candidate[(i / 4)] = c1;
2901                 else
2902                     simubitmap = simubitmap | (1 << i);
2903             } else {
2904                 simubitmap = simubitmap | (1 << i);
2905             }
2906         }
2907     }
2908 
2909     if (simubitmap == 0) {
2910         for (i = 0; i < (bound / 4); i++) {
2911             if (candidate[i] >= 0) {
2912                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2913                     result[3][j] = result[candidate[i]][j];
2914                 retval = false;
2915             }
2916         }
2917         return retval;
2918     } else {
2919         if (!(simubitmap & 0x03)) {
2920             /* path A TX OK */
2921             for (i = 0; i < 2; i++)
2922                 result[3][i] = result[c1][i];
2923         }
2924 
2925         if (!(simubitmap & 0x0c)) {
2926             /* path A RX OK */
2927             for (i = 2; i < 4; i++)
2928                 result[3][i] = result[c1][i];
2929         }
2930 
2931         if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
2932             /* path B RX OK */
2933             for (i = 4; i < 6; i++)
2934                 result[3][i] = result[c1][i];
2935         }
2936 
2937         if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
2938             /* path B RX OK */
2939             for (i = 6; i < 8; i++)
2940                 result[3][i] = result[c1][i];
2941         }
2942     }
2943 
2944     return false;
2945 }
2946 
2947 void
2948 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
2949 {
2950     int i;
2951 
2952     for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2953         backup[i] = rtl8xxxu_read8(priv, reg[i]);
2954 
2955     backup[i] = rtl8xxxu_read32(priv, reg[i]);
2956 }
2957 
2958 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
2959                    const u32 *reg, u32 *backup)
2960 {
2961     int i;
2962 
2963     for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2964         rtl8xxxu_write8(priv, reg[i], backup[i]);
2965 
2966     rtl8xxxu_write32(priv, reg[i], backup[i]);
2967 }
2968 
2969 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2970             u32 *backup, int count)
2971 {
2972     int i;
2973 
2974     for (i = 0; i < count; i++)
2975         backup[i] = rtl8xxxu_read32(priv, regs[i]);
2976 }
2977 
2978 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2979                u32 *backup, int count)
2980 {
2981     int i;
2982 
2983     for (i = 0; i < count; i++)
2984         rtl8xxxu_write32(priv, regs[i], backup[i]);
2985 }
2986 
2987 
2988 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
2989                bool path_a_on)
2990 {
2991     u32 path_on;
2992     int i;
2993 
2994     if (priv->tx_paths == 1) {
2995         path_on = priv->fops->adda_1t_path_on;
2996         rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
2997     } else {
2998         path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
2999             priv->fops->adda_2t_path_on_b;
3000 
3001         rtl8xxxu_write32(priv, regs[0], path_on);
3002     }
3003 
3004     for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3005         rtl8xxxu_write32(priv, regs[i], path_on);
3006 }
3007 
3008 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3009                   const u32 *regs, u32 *backup)
3010 {
3011     int i = 0;
3012 
3013     rtl8xxxu_write8(priv, regs[i], 0x3f);
3014 
3015     for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3016         rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3017 
3018     rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3019 }
3020 
3021 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3022 {
3023     u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3024     int result = 0;
3025 
3026     /* path-A IQK setting */
3027     rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3028     rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3029     rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3030 
3031     val32 = (priv->rf_paths > 1) ? 0x28160202 :
3032         /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3033         0x28160502;
3034     rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3035 
3036     /* path-B IQK setting */
3037     if (priv->rf_paths > 1) {
3038         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3039         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3040         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3041         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3042     }
3043 
3044     /* LO calibration setting */
3045     rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3046 
3047     /* One shot, path A LOK & IQK */
3048     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3049     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3050 
3051     mdelay(1);
3052 
3053     /* Check failed */
3054     reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3055     reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3056     reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3057     reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3058 
3059     if (!(reg_eac & BIT(28)) &&
3060         ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3061         ((reg_e9c & 0x03ff0000) != 0x00420000))
3062         result |= 0x01;
3063     else    /* If TX not OK, ignore RX */
3064         goto out;
3065 
3066     /* If TX is OK, check whether RX is OK */
3067     if (!(reg_eac & BIT(27)) &&
3068         ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3069         ((reg_eac & 0x03ff0000) != 0x00360000))
3070         result |= 0x02;
3071     else
3072         dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3073              __func__);
3074 out:
3075     return result;
3076 }
3077 
3078 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3079 {
3080     u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3081     int result = 0;
3082 
3083     /* One shot, path B LOK & IQK */
3084     rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3085     rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3086 
3087     mdelay(1);
3088 
3089     /* Check failed */
3090     reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3091     reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3092     reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3093     reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3094     reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3095 
3096     if (!(reg_eac & BIT(31)) &&
3097         ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3098         ((reg_ebc & 0x03ff0000) != 0x00420000))
3099         result |= 0x01;
3100     else
3101         goto out;
3102 
3103     if (!(reg_eac & BIT(30)) &&
3104         (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3105         (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3106         result |= 0x02;
3107     else
3108         dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3109              __func__);
3110 out:
3111     return result;
3112 }
3113 
3114 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3115                      int result[][8], int t)
3116 {
3117     struct device *dev = &priv->udev->dev;
3118     u32 i, val32;
3119     int path_a_ok, path_b_ok;
3120     int retry = 2;
3121     static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3122         REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3123         REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3124         REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3125         REG_TX_OFDM_BBON, REG_TX_TO_RX,
3126         REG_TX_TO_TX, REG_RX_CCK,
3127         REG_RX_OFDM, REG_RX_WAIT_RIFS,
3128         REG_RX_TO_RX, REG_STANDBY,
3129         REG_SLEEP, REG_PMPD_ANAEN
3130     };
3131     static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3132         REG_TXPAUSE, REG_BEACON_CTRL,
3133         REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3134     };
3135     static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3136         REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3137         REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3138         REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3139         REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3140     };
3141 
3142     /*
3143      * Note: IQ calibration must be performed after loading
3144      *       PHY_REG.txt , and radio_a, radio_b.txt
3145      */
3146 
3147     if (t == 0) {
3148         /* Save ADDA parameters, turn Path A ADDA on */
3149         rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3150                    RTL8XXXU_ADDA_REGS);
3151         rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3152         rtl8xxxu_save_regs(priv, iqk_bb_regs,
3153                    priv->bb_backup, RTL8XXXU_BB_REGS);
3154     }
3155 
3156     rtl8xxxu_path_adda_on(priv, adda_regs, true);
3157 
3158     if (t == 0) {
3159         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3160         if (val32 & FPGA0_HSSI_PARM1_PI)
3161             priv->pi_enabled = 1;
3162     }
3163 
3164     if (!priv->pi_enabled) {
3165         /* Switch BB to PI mode to do IQ Calibration. */
3166         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3167         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3168     }
3169 
3170     val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3171     val32 &= ~FPGA_RF_MODE_CCK;
3172     rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3173 
3174     rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3175     rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3176     rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3177 
3178     if (!priv->no_pape) {
3179         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3180         val32 |= (FPGA0_RF_PAPE |
3181               (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3182         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3183     }
3184 
3185     val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3186     val32 &= ~BIT(10);
3187     rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3188     val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3189     val32 &= ~BIT(10);
3190     rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3191 
3192     if (priv->tx_paths > 1) {
3193         rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3194         rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3195     }
3196 
3197     /* MAC settings */
3198     rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3199 
3200     /* Page B init */
3201     rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3202 
3203     if (priv->tx_paths > 1)
3204         rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3205 
3206     /* IQ calibration setting */
3207     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3208     rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3209     rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3210 
3211     for (i = 0; i < retry; i++) {
3212         path_a_ok = rtl8xxxu_iqk_path_a(priv);
3213         if (path_a_ok == 0x03) {
3214             val32 = rtl8xxxu_read32(priv,
3215                         REG_TX_POWER_BEFORE_IQK_A);
3216             result[t][0] = (val32 >> 16) & 0x3ff;
3217             val32 = rtl8xxxu_read32(priv,
3218                         REG_TX_POWER_AFTER_IQK_A);
3219             result[t][1] = (val32 >> 16) & 0x3ff;
3220             val32 = rtl8xxxu_read32(priv,
3221                         REG_RX_POWER_BEFORE_IQK_A_2);
3222             result[t][2] = (val32 >> 16) & 0x3ff;
3223             val32 = rtl8xxxu_read32(priv,
3224                         REG_RX_POWER_AFTER_IQK_A_2);
3225             result[t][3] = (val32 >> 16) & 0x3ff;
3226             break;
3227         } else if (i == (retry - 1) && path_a_ok == 0x01) {
3228             /* TX IQK OK */
3229             dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3230                 __func__);
3231 
3232             val32 = rtl8xxxu_read32(priv,
3233                         REG_TX_POWER_BEFORE_IQK_A);
3234             result[t][0] = (val32 >> 16) & 0x3ff;
3235             val32 = rtl8xxxu_read32(priv,
3236                         REG_TX_POWER_AFTER_IQK_A);
3237             result[t][1] = (val32 >> 16) & 0x3ff;
3238         }
3239     }
3240 
3241     if (!path_a_ok)
3242         dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3243 
3244     if (priv->tx_paths > 1) {
3245         /*
3246          * Path A into standby
3247          */
3248         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3249         rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3250         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3251 
3252         /* Turn Path B ADDA on */
3253         rtl8xxxu_path_adda_on(priv, adda_regs, false);
3254 
3255         for (i = 0; i < retry; i++) {
3256             path_b_ok = rtl8xxxu_iqk_path_b(priv);
3257             if (path_b_ok == 0x03) {
3258                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3259                 result[t][4] = (val32 >> 16) & 0x3ff;
3260                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3261                 result[t][5] = (val32 >> 16) & 0x3ff;
3262                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3263                 result[t][6] = (val32 >> 16) & 0x3ff;
3264                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3265                 result[t][7] = (val32 >> 16) & 0x3ff;
3266                 break;
3267             } else if (i == (retry - 1) && path_b_ok == 0x01) {
3268                 /* TX IQK OK */
3269                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3270                 result[t][4] = (val32 >> 16) & 0x3ff;
3271                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3272                 result[t][5] = (val32 >> 16) & 0x3ff;
3273             }
3274         }
3275 
3276         if (!path_b_ok)
3277             dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3278     }
3279 
3280     /* Back to BB mode, load original value */
3281     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3282 
3283     if (t) {
3284         if (!priv->pi_enabled) {
3285             /*
3286              * Switch back BB to SI mode after finishing
3287              * IQ Calibration
3288              */
3289             val32 = 0x01000000;
3290             rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3291             rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3292         }
3293 
3294         /* Reload ADDA power saving parameters */
3295         rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3296                       RTL8XXXU_ADDA_REGS);
3297 
3298         /* Reload MAC parameters */
3299         rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3300 
3301         /* Reload BB parameters */
3302         rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3303                       priv->bb_backup, RTL8XXXU_BB_REGS);
3304 
3305         /* Restore RX initial gain */
3306         rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3307 
3308         if (priv->tx_paths > 1) {
3309             rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3310                      0x00032ed3);
3311         }
3312 
3313         /* Load 0xe30 IQC default value */
3314         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3315         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3316     }
3317 }
3318 
3319 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
3320 {
3321     struct h2c_cmd h2c;
3322 
3323     memset(&h2c, 0, sizeof(struct h2c_cmd));
3324     h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
3325     h2c.bt_wlan_calibration.data = start;
3326 
3327     rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
3328 }
3329 
3330 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3331 {
3332     struct device *dev = &priv->udev->dev;
3333     int result[4][8];   /* last is final result */
3334     int i, candidate;
3335     bool path_a_ok, path_b_ok;
3336     u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3337     u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3338     s32 reg_tmp = 0;
3339     bool simu;
3340 
3341     memset(result, 0, sizeof(result));
3342     candidate = -1;
3343 
3344     path_a_ok = false;
3345     path_b_ok = false;
3346 
3347     rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3348 
3349     for (i = 0; i < 3; i++) {
3350         rtl8xxxu_phy_iqcalibrate(priv, result, i);
3351 
3352         if (i == 1) {
3353             simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3354             if (simu) {
3355                 candidate = 0;
3356                 break;
3357             }
3358         }
3359 
3360         if (i == 2) {
3361             simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3362             if (simu) {
3363                 candidate = 0;
3364                 break;
3365             }
3366 
3367             simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3368             if (simu) {
3369                 candidate = 1;
3370             } else {
3371                 for (i = 0; i < 8; i++)
3372                     reg_tmp += result[3][i];
3373 
3374                 if (reg_tmp)
3375                     candidate = 3;
3376                 else
3377                     candidate = -1;
3378             }
3379         }
3380     }
3381 
3382     for (i = 0; i < 4; i++) {
3383         reg_e94 = result[i][0];
3384         reg_e9c = result[i][1];
3385         reg_ea4 = result[i][2];
3386         reg_eac = result[i][3];
3387         reg_eb4 = result[i][4];
3388         reg_ebc = result[i][5];
3389         reg_ec4 = result[i][6];
3390         reg_ecc = result[i][7];
3391     }
3392 
3393     if (candidate >= 0) {
3394         reg_e94 = result[candidate][0];
3395         priv->rege94 =  reg_e94;
3396         reg_e9c = result[candidate][1];
3397         priv->rege9c = reg_e9c;
3398         reg_ea4 = result[candidate][2];
3399         reg_eac = result[candidate][3];
3400         reg_eb4 = result[candidate][4];
3401         priv->regeb4 = reg_eb4;
3402         reg_ebc = result[candidate][5];
3403         priv->regebc = reg_ebc;
3404         reg_ec4 = result[candidate][6];
3405         reg_ecc = result[candidate][7];
3406         dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3407         dev_dbg(dev,
3408             "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
3409             __func__, reg_e94, reg_e9c,
3410             reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3411         path_a_ok = true;
3412         path_b_ok = true;
3413     } else {
3414         reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3415         reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3416     }
3417 
3418     if (reg_e94 && candidate >= 0)
3419         rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3420                        candidate, (reg_ea4 == 0));
3421 
3422     if (priv->tx_paths > 1 && reg_eb4)
3423         rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3424                        candidate, (reg_ec4 == 0));
3425 
3426     rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
3427                priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3428 }
3429 
3430 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3431 {
3432     u32 val32;
3433     u32 rf_amode, rf_bmode = 0, lstf;
3434 
3435     /* Check continuous TX and Packet TX */
3436     lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3437 
3438     if (lstf & OFDM_LSTF_MASK) {
3439         /* Disable all continuous TX */
3440         val32 = lstf & ~OFDM_LSTF_MASK;
3441         rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3442 
3443         /* Read original RF mode Path A */
3444         rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3445 
3446         /* Set RF mode to standby Path A */
3447         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3448                      (rf_amode & 0x8ffff) | 0x10000);
3449 
3450         /* Path-B */
3451         if (priv->tx_paths > 1) {
3452             rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3453                                RF6052_REG_AC);
3454 
3455             rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3456                          (rf_bmode & 0x8ffff) | 0x10000);
3457         }
3458     } else {
3459         /*  Deal with Packet TX case */
3460         /*  block all queues */
3461         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3462     }
3463 
3464     /* Start LC calibration */
3465     if (priv->fops->has_s0s1)
3466         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
3467     val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3468     val32 |= 0x08000;
3469     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3470 
3471     msleep(100);
3472 
3473     if (priv->fops->has_s0s1)
3474         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
3475 
3476     /* Restore original parameters */
3477     if (lstf & OFDM_LSTF_MASK) {
3478         /* Path-A */
3479         rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3480         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3481 
3482         /* Path-B */
3483         if (priv->tx_paths > 1)
3484             rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3485                          rf_bmode);
3486     } else /*  Deal with Packet TX case */
3487         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3488 }
3489 
3490 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3491 {
3492     int i;
3493     u16 reg;
3494 
3495     reg = REG_MACID;
3496 
3497     for (i = 0; i < ETH_ALEN; i++)
3498         rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3499 
3500     return 0;
3501 }
3502 
3503 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3504 {
3505     int i;
3506     u16 reg;
3507 
3508     dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3509 
3510     reg = REG_BSSID;
3511 
3512     for (i = 0; i < ETH_ALEN; i++)
3513         rtl8xxxu_write8(priv, reg + i, bssid[i]);
3514 
3515     return 0;
3516 }
3517 
3518 static void
3519 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3520 {
3521     u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3522     u8 max_agg = 0xf;
3523     int i;
3524 
3525     ampdu_factor = 1 << (ampdu_factor + 2);
3526     if (ampdu_factor > max_agg)
3527         ampdu_factor = max_agg;
3528 
3529     for (i = 0; i < 4; i++) {
3530         if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3531             vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3532 
3533         if ((vals[i] & 0x0f) > ampdu_factor)
3534             vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3535 
3536         rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3537     }
3538 }
3539 
3540 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3541 {
3542     u8 val8;
3543 
3544     val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3545     val8 &= 0xf8;
3546     val8 |= density;
3547     rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3548 }
3549 
3550 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3551 {
3552     u8 val8;
3553     int count, ret = 0;
3554 
3555     /* Start of rtl8723AU_card_enable_flow */
3556     /* Act to Cardemu sequence*/
3557     /* Turn off RF */
3558     rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3559 
3560     /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3561     val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3562     val8 &= ~LEDCFG2_DPDT_SELECT;
3563     rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3564 
3565     /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3566     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3567     val8 |= BIT(1);
3568     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3569 
3570     for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3571         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3572         if ((val8 & BIT(1)) == 0)
3573             break;
3574         udelay(10);
3575     }
3576 
3577     if (!count) {
3578         dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3579              __func__);
3580         ret = -EBUSY;
3581         goto exit;
3582     }
3583 
3584     /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3585     val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3586     val8 |= SYS_ISO_ANALOG_IPS;
3587     rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3588 
3589     /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3590     val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3591     val8 &= ~LDOA15_ENABLE;
3592     rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3593 
3594 exit:
3595     return ret;
3596 }
3597 
3598 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3599 {
3600     u8 val8;
3601     u8 val32;
3602     int count, ret = 0;
3603 
3604     rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3605 
3606     /*
3607      * Poll - wait for RX packet to complete
3608      */
3609     for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3610         val32 = rtl8xxxu_read32(priv, 0x5f8);
3611         if (!val32)
3612             break;
3613         udelay(10);
3614     }
3615 
3616     if (!count) {
3617         dev_warn(&priv->udev->dev,
3618              "%s: RX poll timed out (0x05f8)\n", __func__);
3619         ret = -EBUSY;
3620         goto exit;
3621     }
3622 
3623     /* Disable CCK and OFDM, clock gated */
3624     val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3625     val8 &= ~SYS_FUNC_BBRSTB;
3626     rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3627 
3628     udelay(2);
3629 
3630     /* Reset baseband */
3631     val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3632     val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3633     rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3634 
3635     /* Reset MAC TRX */
3636     val8 = rtl8xxxu_read8(priv, REG_CR);
3637     val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3638     rtl8xxxu_write8(priv, REG_CR, val8);
3639 
3640     /* Reset MAC TRX */
3641     val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3642     val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3643     rtl8xxxu_write8(priv, REG_CR + 1, val8);
3644 
3645     /* Respond TX OK to scheduler */
3646     val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3647     val8 |= DUAL_TSF_TX_OK;
3648     rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3649 
3650 exit:
3651     return ret;
3652 }
3653 
3654 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3655 {
3656     u8 val8;
3657 
3658     /* Clear suspend enable and power down enable*/
3659     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3660     val8 &= ~(BIT(3) | BIT(7));
3661     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3662 
3663     /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3664     val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3665     val8 &= ~BIT(0);
3666     rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3667 
3668     /* 0x04[12:11] = 11 enable WL suspend*/
3669     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3670     val8 &= ~(BIT(3) | BIT(4));
3671     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3672 }
3673 
3674 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3675 {
3676     u8 val8;
3677 
3678     /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3679     rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3680 
3681     /* 0x04[12:11] = 01 enable WL suspend */
3682     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3683     val8 &= ~BIT(4);
3684     val8 |= BIT(3);
3685     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3686 
3687     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3688     val8 |= BIT(7);
3689     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3690 
3691     /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3692     val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3693     val8 |= BIT(0);
3694     rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3695 
3696     return 0;
3697 }
3698 
3699 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
3700 {
3701     struct device *dev = &priv->udev->dev;
3702     u32 val32;
3703     int retry, retval;
3704 
3705     rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3706 
3707     val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3708     val32 |= RXPKT_NUM_RW_RELEASE_EN;
3709     rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
3710 
3711     retry = 100;
3712     retval = -EBUSY;
3713 
3714     do {
3715         val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3716         if (val32 & RXPKT_NUM_RXDMA_IDLE) {
3717             retval = 0;
3718             break;
3719         }
3720     } while (retry--);
3721 
3722     rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
3723     rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
3724     mdelay(2);
3725 
3726     if (!retry)
3727         dev_warn(dev, "Failed to flush FIFO\n");
3728 
3729     return retval;
3730 }
3731 
3732 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)
3733 {
3734     /* Fix USB interface interference issue */
3735     rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3736     rtl8xxxu_write8(priv, 0xfe41, 0x8d);
3737     rtl8xxxu_write8(priv, 0xfe42, 0x80);
3738     /*
3739      * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits
3740      * 8 and 5, for which I have found no documentation.
3741      */
3742     rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
3743 
3744     /*
3745      * Solve too many protocol error on USB bus.
3746      * Can't do this for 8188/8192 UMC A cut parts
3747      */
3748     if (!(!priv->chip_cut && priv->vendor_umc)) {
3749         rtl8xxxu_write8(priv, 0xfe40, 0xe6);
3750         rtl8xxxu_write8(priv, 0xfe41, 0x94);
3751         rtl8xxxu_write8(priv, 0xfe42, 0x80);
3752 
3753         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3754         rtl8xxxu_write8(priv, 0xfe41, 0x19);
3755         rtl8xxxu_write8(priv, 0xfe42, 0x80);
3756 
3757         rtl8xxxu_write8(priv, 0xfe40, 0xe5);
3758         rtl8xxxu_write8(priv, 0xfe41, 0x91);
3759         rtl8xxxu_write8(priv, 0xfe42, 0x80);
3760 
3761         rtl8xxxu_write8(priv, 0xfe40, 0xe2);
3762         rtl8xxxu_write8(priv, 0xfe41, 0x81);
3763         rtl8xxxu_write8(priv, 0xfe42, 0x80);
3764     }
3765 }
3766 
3767 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)
3768 {
3769     u32 val32;
3770 
3771     val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
3772     val32 |= TXDMA_OFFSET_DROP_DATA_EN;
3773     rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
3774 }
3775 
3776 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3777 {
3778     u8 val8;
3779     u16 val16;
3780     u32 val32;
3781 
3782     /*
3783      * Workaround for 8188RU LNA power leakage problem.
3784      */
3785     if (priv->rtl_chip == RTL8188R) {
3786         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3787         val32 |= BIT(1);
3788         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3789     }
3790 
3791     rtl8xxxu_flush_fifo(priv);
3792 
3793     rtl8xxxu_active_to_lps(priv);
3794 
3795     /* Turn off RF */
3796     rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3797 
3798     /* Reset Firmware if running in RAM */
3799     if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3800         rtl8xxxu_firmware_self_reset(priv);
3801 
3802     /* Reset MCU */
3803     val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3804     val16 &= ~SYS_FUNC_CPU_ENABLE;
3805     rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3806 
3807     /* Reset MCU ready status */
3808     rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3809 
3810     rtl8xxxu_active_to_emu(priv);
3811     rtl8xxxu_emu_to_disabled(priv);
3812 
3813     /* Reset MCU IO Wrapper */
3814     val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3815     val8 &= ~BIT(0);
3816     rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3817 
3818     val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3819     val8 |= BIT(0);
3820     rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3821 
3822     /* RSV_CTRL 0x1C[7:0] = 0x0e  lock ISO/CLK/Power control register */
3823     rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3824 }
3825 
3826 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
3827                u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
3828 {
3829     struct h2c_cmd h2c;
3830 
3831     memset(&h2c, 0, sizeof(struct h2c_cmd));
3832     h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
3833     h2c.b_type_dma.data1 = arg1;
3834     h2c.b_type_dma.data2 = arg2;
3835     h2c.b_type_dma.data3 = arg3;
3836     h2c.b_type_dma.data4 = arg4;
3837     h2c.b_type_dma.data5 = arg5;
3838     rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
3839 }
3840 
3841 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv)
3842 {
3843     u32 val32;
3844 
3845     val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
3846     val32 &= ~(BIT(22) | BIT(23));
3847     rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
3848 }
3849 
3850 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
3851 {
3852     struct rtl8xxxu_fileops *fops = priv->fops;
3853     u32 hq, lq, nq, eq, pubq;
3854     u32 val32;
3855 
3856     hq = 0;
3857     lq = 0;
3858     nq = 0;
3859     eq = 0;
3860     pubq = 0;
3861 
3862     if (priv->ep_tx_high_queue)
3863         hq = fops->page_num_hi;
3864     if (priv->ep_tx_low_queue)
3865         lq = fops->page_num_lo;
3866     if (priv->ep_tx_normal_queue)
3867         nq = fops->page_num_norm;
3868 
3869     val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);
3870     rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);
3871 
3872     pubq = fops->total_page_num - hq - lq - nq - 1;
3873 
3874     val32 = RQPN_LOAD;
3875     val32 |= (hq << RQPN_HI_PQ_SHIFT);
3876     val32 |= (lq << RQPN_LO_PQ_SHIFT);
3877     val32 |= (pubq << RQPN_PUB_PQ_SHIFT);
3878 
3879     rtl8xxxu_write32(priv, REG_RQPN, val32);
3880 }
3881 
3882 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
3883 {
3884     struct rtl8xxxu_priv *priv = hw->priv;
3885     struct device *dev = &priv->udev->dev;
3886     struct rtl8xxxu_fileops *fops = priv->fops;
3887     bool macpower;
3888     int ret;
3889     u8 val8;
3890     u16 val16;
3891     u32 val32;
3892 
3893     /* Check if MAC is already powered on */
3894     val8 = rtl8xxxu_read8(priv, REG_CR);
3895     val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
3896 
3897     /*
3898      * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
3899      * initialized. First MAC returns 0xea, second MAC returns 0x00
3900      */
3901     if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE))
3902         macpower = false;
3903     else
3904         macpower = true;
3905 
3906     if (fops->needs_full_init)
3907         macpower = false;
3908 
3909     ret = fops->power_on(priv);
3910     if (ret < 0) {
3911         dev_warn(dev, "%s: Failed power on\n", __func__);
3912         goto exit;
3913     }
3914 
3915     if (!macpower)
3916         rtl8xxxu_init_queue_reserved_page(priv);
3917 
3918     ret = rtl8xxxu_init_queue_priority(priv);
3919     dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
3920     if (ret)
3921         goto exit;
3922 
3923     /*
3924      * Set RX page boundary
3925      */
3926     rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary);
3927 
3928     ret = rtl8xxxu_download_firmware(priv);
3929     dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret);
3930     if (ret)
3931         goto exit;
3932     ret = rtl8xxxu_start_firmware(priv);
3933     dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret);
3934     if (ret)
3935         goto exit;
3936 
3937     if (fops->phy_init_antenna_selection)
3938         fops->phy_init_antenna_selection(priv);
3939 
3940     ret = rtl8xxxu_init_mac(priv);
3941 
3942     dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
3943     if (ret)
3944         goto exit;
3945 
3946     ret = rtl8xxxu_init_phy_bb(priv);
3947     dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
3948     if (ret)
3949         goto exit;
3950 
3951     ret = fops->init_phy_rf(priv);
3952     if (ret)
3953         goto exit;
3954 
3955     /* RFSW Control - clear bit 14 ?? */
3956     if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
3957         rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
3958 
3959     val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
3960         FPGA0_RF_ANTSWB |
3961         ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);
3962     if (!priv->no_pape) {
3963         val32 |= (FPGA0_RF_PAPE |
3964               (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3965     }
3966     rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3967 
3968     /* 0x860[6:5]= 00 - why? - this sets antenna B */
3969     if (priv->rtl_chip != RTL8192E)
3970         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
3971 
3972     if (!macpower) {
3973         /*
3974          * Set TX buffer boundary
3975          */
3976         val8 = fops->total_page_num + 1;
3977 
3978         rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
3979         rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
3980         rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
3981         rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
3982         rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
3983     }
3984 
3985     /*
3986      * The vendor drivers set PBP for all devices, except 8192e.
3987      * There is no explanation for this in any of the sources.
3988      */
3989     val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |
3990         (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);
3991     if (priv->rtl_chip != RTL8192E)
3992         rtl8xxxu_write8(priv, REG_PBP, val8);
3993 
3994     dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
3995     if (!macpower) {
3996         ret = fops->llt_init(priv);
3997         if (ret) {
3998             dev_warn(dev, "%s: LLT table init failed\n", __func__);
3999             goto exit;
4000         }
4001 
4002         /*
4003          * Chip specific quirks
4004          */
4005         fops->usb_quirks(priv);
4006 
4007         /*
4008          * Enable TX report and TX report timer for 8723bu/8188eu/...
4009          */
4010         if (fops->has_tx_report) {
4011             val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
4012             val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
4013             rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
4014             /* Set MAX RPT MACID */
4015             rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
4016             /* TX report Timer. Unit: 32us */
4017             rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
4018 
4019             /* tmp ps ? */
4020             val8 = rtl8xxxu_read8(priv, 0xa3);
4021             val8 &= 0xf8;
4022             rtl8xxxu_write8(priv, 0xa3, val8);
4023         }
4024     }
4025 
4026     /*
4027      * Unit in 8 bytes, not obvious what it is used for
4028      */
4029     rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4030 
4031     if (priv->rtl_chip == RTL8192E) {
4032         rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4033         rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4034     } else {
4035         /*
4036          * Enable all interrupts - not obvious USB needs to do this
4037          */
4038         rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4039         rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4040     }
4041 
4042     rtl8xxxu_set_mac(priv);
4043     rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4044 
4045     /*
4046      * Configure initial WMAC settings
4047      */
4048     val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4049         RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4050         RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4051     rtl8xxxu_write32(priv, REG_RCR, val32);
4052 
4053     /*
4054      * Accept all multicast
4055      */
4056     rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4057     rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4058 
4059     /*
4060      * Init adaptive controls
4061      */
4062     val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4063     val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4064     val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4065     rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4066 
4067     /* CCK = 0x0a, OFDM = 0x10 */
4068     rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4069     rtl8xxxu_set_retry(priv, 0x30, 0x30);
4070     rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4071 
4072     /*
4073      * Init EDCA
4074      */
4075     rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4076 
4077     /* Set CCK SIFS */
4078     rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4079 
4080     /* Set OFDM SIFS */
4081     rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4082 
4083     /* TXOP */
4084     rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4085     rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4086     rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4087     rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4088 
4089     /* Set data auto rate fallback retry count */
4090     rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4091     rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4092     rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4093     rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4094 
4095     val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4096     val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4097     rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4098 
4099     /*  Set ACK timeout */
4100     rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4101 
4102     /*
4103      * Initialize beacon parameters
4104      */
4105     val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4106     rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4107     rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4108     rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4109     rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4110     rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4111 
4112     /*
4113      * Initialize burst parameters
4114      */
4115     if (priv->rtl_chip == RTL8723B) {
4116         /*
4117          * For USB high speed set 512B packets
4118          */
4119         val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
4120         val8 &= ~(BIT(4) | BIT(5));
4121         val8 |= BIT(4);
4122         val8 |= BIT(1) | BIT(2) | BIT(3);
4123         rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
4124 
4125         /*
4126          * For USB high speed set 512B packets
4127          */
4128         val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
4129         val8 |= BIT(7);
4130         rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
4131 
4132         rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
4133         rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
4134         rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
4135         rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
4136         rtl8xxxu_write8(priv, REG_PIFS, 0x00);
4137         rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
4138         rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
4139 
4140         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
4141         val8 |= BIT(5) | BIT(6);
4142         rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
4143     }
4144 
4145     if (fops->init_aggregation)
4146         fops->init_aggregation(priv);
4147 
4148     /*
4149      * Enable CCK and OFDM block
4150      */
4151     val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4152     val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4153     rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4154 
4155     /*
4156      * Invalidate all CAM entries - bit 30 is undocumented
4157      */
4158     rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4159 
4160     /*
4161      * Start out with default power levels for channel 6, 20MHz
4162      */
4163     fops->set_tx_power(priv, 1, false);
4164 
4165     /* Let the 8051 take control of antenna setting */
4166     if (priv->rtl_chip != RTL8192E) {
4167         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4168         val8 |= LEDCFG2_DPDT_SELECT;
4169         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4170     }
4171 
4172     rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4173 
4174     /* Disable BAR - not sure if this has any effect on USB */
4175     rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4176 
4177     rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4178 
4179     if (fops->init_statistics)
4180         fops->init_statistics(priv);
4181 
4182     if (priv->rtl_chip == RTL8192E) {
4183         /*
4184          * 0x4c6[3] 1: RTS BW = Data BW
4185          * 0: RTS BW depends on CCA / secondary CCA result.
4186          */
4187         val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);
4188         val8 &= ~BIT(3);
4189         rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);
4190         /*
4191          * Reset USB mode switch setting
4192          */
4193         rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
4194     }
4195 
4196     rtl8723a_phy_lc_calibrate(priv);
4197 
4198     fops->phy_iq_calibrate(priv);
4199 
4200     /*
4201      * This should enable thermal meter
4202      */
4203     if (fops->gen2_thermal_meter)
4204         rtl8xxxu_write_rfreg(priv,
4205                      RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
4206     else
4207         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4208 
4209     /* Set NAV_UPPER to 30000us */
4210     val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4211     rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4212 
4213     if (priv->rtl_chip == RTL8723A) {
4214         /*
4215          * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4216          * but we need to find root cause.
4217          * This is 8723au only.
4218          */
4219         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4220         if ((val32 & 0xff000000) != 0x83000000) {
4221             val32 |= FPGA_RF_MODE_CCK;
4222             rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4223         }
4224     } else if (priv->rtl_chip == RTL8192E) {
4225         rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
4226     }
4227 
4228     val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4229     val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4230     /* ack for xmit mgmt frames. */
4231     rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4232 
4233     if (priv->rtl_chip == RTL8192E) {
4234         /*
4235          * Fix LDPC rx hang issue.
4236          */
4237         val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
4238         rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);
4239         val32 &= 0xfff00fff;
4240         val32 |= 0x0007e000;
4241         rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
4242     }
4243 exit:
4244     return ret;
4245 }
4246 
4247 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4248                    struct ieee80211_key_conf *key, const u8 *mac)
4249 {
4250     u32 cmd, val32, addr, ctrl;
4251     int j, i, tmp_debug;
4252 
4253     tmp_debug = rtl8xxxu_debug;
4254     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4255         rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4256 
4257     /*
4258      * This is a bit of a hack - the lower bits of the cipher
4259      * suite selector happens to match the cipher index in the CAM
4260      */
4261     addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4262     ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4263 
4264     for (j = 5; j >= 0; j--) {
4265         switch (j) {
4266         case 0:
4267             val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4268             break;
4269         case 1:
4270             val32 = mac[2] | (mac[3] << 8) |
4271                 (mac[4] << 16) | (mac[5] << 24);
4272             break;
4273         default:
4274             i = (j - 2) << 2;
4275             val32 = key->key[i] | (key->key[i + 1] << 8) |
4276                 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4277             break;
4278         }
4279 
4280         rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4281         cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4282         rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4283         udelay(100);
4284     }
4285 
4286     rtl8xxxu_debug = tmp_debug;
4287 }
4288 
4289 static
4290 int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
4291 {
4292     struct rtl8xxxu_priv *priv = hw->priv;
4293 
4294     *tx_ant = BIT(priv->tx_paths) - 1;
4295     *rx_ant = BIT(priv->rx_paths) - 1;
4296 
4297     return 0;
4298 }
4299 
4300 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4301                    struct ieee80211_vif *vif, const u8 *mac)
4302 {
4303     struct rtl8xxxu_priv *priv = hw->priv;
4304     u8 val8;
4305 
4306     val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4307     val8 |= BEACON_DISABLE_TSF_UPDATE;
4308     rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4309 }
4310 
4311 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4312                       struct ieee80211_vif *vif)
4313 {
4314     struct rtl8xxxu_priv *priv = hw->priv;
4315     u8 val8;
4316 
4317     val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4318     val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4319     rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4320 }
4321 
4322 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4323                    u32 ramask, u8 rateid, int sgi)
4324 {
4325     struct h2c_cmd h2c;
4326 
4327     memset(&h2c, 0, sizeof(struct h2c_cmd));
4328 
4329     h2c.ramask.cmd = H2C_SET_RATE_MASK;
4330     h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4331     h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4332 
4333     h2c.ramask.arg = 0x80;
4334     if (sgi)
4335         h2c.ramask.arg |= 0x20;
4336 
4337     dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4338         __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
4339     rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
4340 }
4341 
4342 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
4343                     u32 ramask, u8 rateid, int sgi)
4344 {
4345     struct h2c_cmd h2c;
4346     u8 bw = RTL8XXXU_CHANNEL_WIDTH_20;
4347 
4348     memset(&h2c, 0, sizeof(struct h2c_cmd));
4349 
4350     h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
4351     h2c.b_macid_cfg.ramask0 = ramask & 0xff;
4352     h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
4353     h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
4354     h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
4355 
4356     h2c.ramask.arg = 0x80;
4357     h2c.b_macid_cfg.data1 = rateid;
4358     if (sgi)
4359         h2c.b_macid_cfg.data1 |= BIT(7);
4360 
4361     h2c.b_macid_cfg.data2 = bw;
4362 
4363     dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4364         __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
4365     rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
4366 }
4367 
4368 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
4369                   u8 macid, bool connect)
4370 {
4371     struct h2c_cmd h2c;
4372 
4373     memset(&h2c, 0, sizeof(struct h2c_cmd));
4374 
4375     h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4376 
4377     if (connect)
4378         h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4379     else
4380         h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4381 
4382     rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
4383 }
4384 
4385 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
4386                   u8 macid, bool connect)
4387 {
4388 #ifdef RTL8XXXU_GEN2_REPORT_CONNECT
4389     /*
4390      * Barry Day reports this causes issues with 8192eu and 8723bu
4391      * devices reconnecting. The reason for this is unclear, but
4392      * until it is better understood, leave the code in place but
4393      * disabled, so it is not lost.
4394      */
4395     struct h2c_cmd h2c;
4396 
4397     memset(&h2c, 0, sizeof(struct h2c_cmd));
4398 
4399     h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
4400     if (connect)
4401         h2c.media_status_rpt.parm |= BIT(0);
4402     else
4403         h2c.media_status_rpt.parm &= ~BIT(0);
4404 
4405     rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
4406 #endif
4407 }
4408 
4409 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv)
4410 {
4411     u8 agg_ctrl, usb_spec, page_thresh, timeout;
4412 
4413     usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4414     usb_spec &= ~USB_SPEC_USB_AGG_ENABLE;
4415     rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec);
4416 
4417     agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
4418     agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
4419 
4420     if (!rtl8xxxu_dma_aggregation) {
4421         rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4422         return;
4423     }
4424 
4425     agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN;
4426     rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4427 
4428     /*
4429      * The number of packets we can take looks to be buffer size / 512
4430      * which matches the 512 byte rounding we have to do when de-muxing
4431      * the packets.
4432      *
4433      * Sample numbers from the vendor driver:
4434      * USB High-Speed mode values:
4435      *   RxAggBlockCount = 8 : 512 byte unit
4436      *   RxAggBlockTimeout = 6
4437      *   RxAggPageCount = 48 : 128 byte unit
4438      *   RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6))
4439      */
4440 
4441     page_thresh = (priv->fops->rx_agg_buf_size / 512);
4442     if (rtl8xxxu_dma_agg_pages >= 0) {
4443         if (rtl8xxxu_dma_agg_pages <= page_thresh)
4444             timeout = page_thresh;
4445         else if (rtl8xxxu_dma_agg_pages <= 6)
4446             dev_err(&priv->udev->dev,
4447                 "%s: dma_agg_pages=%i too small, minimum is 6\n",
4448                 __func__, rtl8xxxu_dma_agg_pages);
4449         else
4450             dev_err(&priv->udev->dev,
4451                 "%s: dma_agg_pages=%i larger than limit %i\n",
4452                 __func__, rtl8xxxu_dma_agg_pages, page_thresh);
4453     }
4454     rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh);
4455     /*
4456      * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on
4457      * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we
4458      * don't set it, so better set both.
4459      */
4460     timeout = 4;
4461 
4462     if (rtl8xxxu_dma_agg_timeout >= 0) {
4463         if (rtl8xxxu_dma_agg_timeout <= 127)
4464             timeout = rtl8xxxu_dma_agg_timeout;
4465         else
4466             dev_err(&priv->udev->dev,
4467                 "%s: Invalid dma_agg_timeout: %i\n",
4468                 __func__, rtl8xxxu_dma_agg_timeout);
4469     }
4470 
4471     rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout);
4472     rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout);
4473     priv->rx_buf_aggregation = 1;
4474 }
4475 
4476 static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = {
4477     {.bitrate = 10, .hw_value = 0x00,},
4478     {.bitrate = 20, .hw_value = 0x01,},
4479     {.bitrate = 55, .hw_value = 0x02,},
4480     {.bitrate = 110, .hw_value = 0x03,},
4481     {.bitrate = 60, .hw_value = 0x04,},
4482     {.bitrate = 90, .hw_value = 0x05,},
4483     {.bitrate = 120, .hw_value = 0x06,},
4484     {.bitrate = 180, .hw_value = 0x07,},
4485     {.bitrate = 240, .hw_value = 0x08,},
4486     {.bitrate = 360, .hw_value = 0x09,},
4487     {.bitrate = 480, .hw_value = 0x0a,},
4488     {.bitrate = 540, .hw_value = 0x0b,},
4489 };
4490 
4491 static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss)
4492 {
4493     if (rate <= DESC_RATE_54M)
4494         return;
4495 
4496     if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) {
4497         if (rate < DESC_RATE_MCS8)
4498             *nss = 1;
4499         else
4500             *nss = 2;
4501         *mcs = rate - DESC_RATE_MCS0;
4502     }
4503 }
4504 
4505 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4506 {
4507     struct ieee80211_hw *hw = priv->hw;
4508     u32 val32;
4509     u8 rate_idx = 0;
4510 
4511     rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4512 
4513     val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4514     if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ)
4515         val32 &= RESPONSE_RATE_RRSR_INIT_5G;
4516     else
4517         val32 &= RESPONSE_RATE_RRSR_INIT_2G;
4518     val32 |= rate_cfg;
4519     rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4520 
4521     dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4522 
4523     while (rate_cfg) {
4524         rate_cfg = (rate_cfg >> 1);
4525         rate_idx++;
4526     }
4527     rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4528 }
4529 
4530 static u16
4531 rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta)
4532 {
4533     u16 network_type = WIRELESS_MODE_UNKNOWN;
4534 
4535     if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) {
4536         if (sta->deflink.vht_cap.vht_supported)
4537             network_type = WIRELESS_MODE_AC;
4538         else if (sta->deflink.ht_cap.ht_supported)
4539             network_type = WIRELESS_MODE_N_5G;
4540 
4541         network_type |= WIRELESS_MODE_A;
4542     } else {
4543         if (sta->deflink.vht_cap.vht_supported)
4544             network_type = WIRELESS_MODE_AC;
4545         else if (sta->deflink.ht_cap.ht_supported)
4546             network_type = WIRELESS_MODE_N_24G;
4547 
4548         if (sta->deflink.supp_rates[0] <= 0xf)
4549             network_type |= WIRELESS_MODE_B;
4550         else if (sta->deflink.supp_rates[0] & 0xf)
4551             network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G);
4552         else
4553             network_type |= WIRELESS_MODE_G;
4554     }
4555 
4556     return network_type;
4557 }
4558 
4559 static void
4560 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4561               struct ieee80211_bss_conf *bss_conf, u64 changed)
4562 {
4563     struct rtl8xxxu_priv *priv = hw->priv;
4564     struct device *dev = &priv->udev->dev;
4565     struct ieee80211_sta *sta;
4566     struct rtl8xxxu_ra_report *rarpt;
4567     u32 val32;
4568     u8 val8;
4569 
4570     rarpt = &priv->ra_report;
4571 
4572     if (changed & BSS_CHANGED_ASSOC) {
4573         dev_dbg(dev, "Changed ASSOC: %i!\n", vif->cfg.assoc);
4574 
4575         rtl8xxxu_set_linktype(priv, vif->type);
4576 
4577         if (vif->cfg.assoc) {
4578             u32 ramask;
4579             int sgi = 0;
4580             u8 highest_rate;
4581             u8 mcs = 0, nss = 0;
4582             u32 bit_rate;
4583 
4584 
4585             rcu_read_lock();
4586             sta = ieee80211_find_sta(vif, bss_conf->bssid);
4587             if (!sta) {
4588                 dev_info(dev, "%s: ASSOC no sta found\n",
4589                      __func__);
4590                 rcu_read_unlock();
4591                 goto error;
4592             }
4593 
4594             if (sta->deflink.ht_cap.ht_supported)
4595                 dev_info(dev, "%s: HT supported\n", __func__);
4596             if (sta->deflink.vht_cap.vht_supported)
4597                 dev_info(dev, "%s: VHT supported\n", __func__);
4598 
4599             /* TODO: Set bits 28-31 for rate adaptive id */
4600             ramask = (sta->deflink.supp_rates[0] & 0xfff) |
4601                 sta->deflink.ht_cap.mcs.rx_mask[0] << 12 |
4602                 sta->deflink.ht_cap.mcs.rx_mask[1] << 20;
4603             if (sta->deflink.ht_cap.cap &
4604                 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4605                 sgi = 1;
4606             rcu_read_unlock();
4607 
4608             highest_rate = fls(ramask) - 1;
4609             if (highest_rate < DESC_RATE_MCS0) {
4610                 rarpt->txrate.legacy =
4611                 rtl8xxxu_legacy_ratetable[highest_rate].bitrate;
4612             } else {
4613                 rtl8xxxu_desc_to_mcsrate(highest_rate,
4614                              &mcs, &nss);
4615                 rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS;
4616 
4617                 rarpt->txrate.mcs = mcs;
4618                 rarpt->txrate.nss = nss;
4619 
4620                 if (sgi) {
4621                     rarpt->txrate.flags |=
4622                         RATE_INFO_FLAGS_SHORT_GI;
4623                 }
4624 
4625                 rarpt->txrate.bw |= RATE_INFO_BW_20;
4626             }
4627             bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate);
4628             rarpt->bit_rate = bit_rate;
4629             rarpt->desc_rate = highest_rate;
4630 
4631             priv->vif = vif;
4632             priv->rssi_level = RTL8XXXU_RATR_STA_INIT;
4633 
4634             priv->fops->update_rate_mask(priv, ramask, 0, sgi);
4635 
4636             rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4637 
4638             rtl8xxxu_stop_tx_beacon(priv);
4639 
4640             /* joinbss sequence */
4641             rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4642                      0xc000 | vif->cfg.aid);
4643 
4644             priv->fops->report_connect(priv, 0, true);
4645         } else {
4646             val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4647             val8 |= BEACON_DISABLE_TSF_UPDATE;
4648             rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4649 
4650             priv->fops->report_connect(priv, 0, false);
4651         }
4652     }
4653 
4654     if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4655         dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4656             bss_conf->use_short_preamble);
4657         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4658         if (bss_conf->use_short_preamble)
4659             val32 |= RSR_ACK_SHORT_PREAMBLE;
4660         else
4661             val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4662         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4663     }
4664 
4665     if (changed & BSS_CHANGED_ERP_SLOT) {
4666         dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4667             bss_conf->use_short_slot);
4668 
4669         if (bss_conf->use_short_slot)
4670             val8 = 9;
4671         else
4672             val8 = 20;
4673         rtl8xxxu_write8(priv, REG_SLOT, val8);
4674     }
4675 
4676     if (changed & BSS_CHANGED_BSSID) {
4677         dev_dbg(dev, "Changed BSSID!\n");
4678         rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4679     }
4680 
4681     if (changed & BSS_CHANGED_BASIC_RATES) {
4682         dev_dbg(dev, "Changed BASIC_RATES!\n");
4683         rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4684     }
4685 error:
4686     return;
4687 }
4688 
4689 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4690 {
4691     u32 rtlqueue;
4692 
4693     switch (queue) {
4694     case IEEE80211_AC_VO:
4695         rtlqueue = TXDESC_QUEUE_VO;
4696         break;
4697     case IEEE80211_AC_VI:
4698         rtlqueue = TXDESC_QUEUE_VI;
4699         break;
4700     case IEEE80211_AC_BE:
4701         rtlqueue = TXDESC_QUEUE_BE;
4702         break;
4703     case IEEE80211_AC_BK:
4704         rtlqueue = TXDESC_QUEUE_BK;
4705         break;
4706     default:
4707         rtlqueue = TXDESC_QUEUE_BE;
4708     }
4709 
4710     return rtlqueue;
4711 }
4712 
4713 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4714 {
4715     struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4716     u32 queue;
4717 
4718     if (ieee80211_is_mgmt(hdr->frame_control))
4719         queue = TXDESC_QUEUE_MGNT;
4720     else
4721         queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4722 
4723     return queue;
4724 }
4725 
4726 /*
4727  * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
4728  * format. The descriptor checksum is still only calculated over the
4729  * initial 32 bytes of the descriptor!
4730  */
4731 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
4732 {
4733     __le16 *ptr = (__le16 *)tx_desc;
4734     u16 csum = 0;
4735     int i;
4736 
4737     /*
4738      * Clear csum field before calculation, as the csum field is
4739      * in the middle of the struct.
4740      */
4741     tx_desc->csum = cpu_to_le16(0);
4742 
4743     for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
4744         csum = csum ^ le16_to_cpu(ptr[i]);
4745 
4746     tx_desc->csum |= cpu_to_le16(csum);
4747 }
4748 
4749 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4750 {
4751     struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4752     unsigned long flags;
4753 
4754     spin_lock_irqsave(&priv->tx_urb_lock, flags);
4755     list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4756         list_del(&tx_urb->list);
4757         priv->tx_urb_free_count--;
4758         usb_free_urb(&tx_urb->urb);
4759     }
4760     spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4761 }
4762 
4763 static struct rtl8xxxu_tx_urb *
4764 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4765 {
4766     struct rtl8xxxu_tx_urb *tx_urb;
4767     unsigned long flags;
4768 
4769     spin_lock_irqsave(&priv->tx_urb_lock, flags);
4770     tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4771                       struct rtl8xxxu_tx_urb, list);
4772     if (tx_urb) {
4773         list_del(&tx_urb->list);
4774         priv->tx_urb_free_count--;
4775         if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4776             !priv->tx_stopped) {
4777             priv->tx_stopped = true;
4778             ieee80211_stop_queues(priv->hw);
4779         }
4780     }
4781 
4782     spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4783 
4784     return tx_urb;
4785 }
4786 
4787 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4788                  struct rtl8xxxu_tx_urb *tx_urb)
4789 {
4790     unsigned long flags;
4791 
4792     INIT_LIST_HEAD(&tx_urb->list);
4793 
4794     spin_lock_irqsave(&priv->tx_urb_lock, flags);
4795 
4796     list_add(&tx_urb->list, &priv->tx_urb_free_list);
4797     priv->tx_urb_free_count++;
4798     if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4799         priv->tx_stopped) {
4800         priv->tx_stopped = false;
4801         ieee80211_wake_queues(priv->hw);
4802     }
4803 
4804     spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4805 }
4806 
4807 static void rtl8xxxu_tx_complete(struct urb *urb)
4808 {
4809     struct sk_buff *skb = (struct sk_buff *)urb->context;
4810     struct ieee80211_tx_info *tx_info;
4811     struct ieee80211_hw *hw;
4812     struct rtl8xxxu_priv *priv;
4813     struct rtl8xxxu_tx_urb *tx_urb =
4814         container_of(urb, struct rtl8xxxu_tx_urb, urb);
4815 
4816     tx_info = IEEE80211_SKB_CB(skb);
4817     hw = tx_info->rate_driver_data[0];
4818     priv = hw->priv;
4819 
4820     skb_pull(skb, priv->fops->tx_desc_size);
4821 
4822     ieee80211_tx_info_clear_status(tx_info);
4823     tx_info->status.rates[0].idx = -1;
4824     tx_info->status.rates[0].count = 0;
4825 
4826     if (!urb->status)
4827         tx_info->flags |= IEEE80211_TX_STAT_ACK;
4828 
4829     ieee80211_tx_status_irqsafe(hw, skb);
4830 
4831     rtl8xxxu_free_tx_urb(priv, tx_urb);
4832 }
4833 
4834 static void rtl8xxxu_dump_action(struct device *dev,
4835                  struct ieee80211_hdr *hdr)
4836 {
4837     struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4838     u16 cap, timeout;
4839 
4840     if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4841         return;
4842 
4843     switch (mgmt->u.action.u.addba_resp.action_code) {
4844     case WLAN_ACTION_ADDBA_RESP:
4845         cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4846         timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4847         dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4848              "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4849              "status %02x\n",
4850              timeout,
4851              (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4852              (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4853              (cap >> 1) & 0x1,
4854              le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4855         break;
4856     case WLAN_ACTION_ADDBA_REQ:
4857         cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4858         timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4859         dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4860              "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4861              timeout,
4862              (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4863              (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4864              (cap >> 1) & 0x1);
4865         break;
4866     default:
4867         dev_info(dev, "action frame %02x\n",
4868              mgmt->u.action.u.addba_resp.action_code);
4869         break;
4870     }
4871 }
4872 
4873 /*
4874  * Fill in v1 (gen1) specific TX descriptor bits.
4875  * This format is used on 8188cu/8192cu/8723au
4876  */
4877 void
4878 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
4879             struct ieee80211_tx_info *tx_info,
4880             struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
4881             bool short_preamble, bool ampdu_enable, u32 rts_rate)
4882 {
4883     struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4884     struct rtl8xxxu_priv *priv = hw->priv;
4885     struct device *dev = &priv->udev->dev;
4886     u8 *qc = ieee80211_get_qos_ctl(hdr);
4887     u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
4888     u32 rate;
4889     u16 rate_flags = tx_info->control.rates[0].flags;
4890     u16 seq_number;
4891 
4892     if (rate_flags & IEEE80211_TX_RC_MCS &&
4893         !ieee80211_is_mgmt(hdr->frame_control))
4894         rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4895     else
4896         rate = tx_rate->hw_value;
4897 
4898     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4899         dev_info(dev, "%s: TX rate: %d, pkt size %u\n",
4900              __func__, rate, le16_to_cpu(tx_desc->pkt_size));
4901 
4902     seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4903 
4904     tx_desc->txdw5 = cpu_to_le32(rate);
4905 
4906     if (ieee80211_is_data(hdr->frame_control))
4907         tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4908 
4909     tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
4910 
4911     if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
4912         tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
4913     else
4914         tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
4915 
4916     if (ieee80211_is_mgmt(hdr->frame_control)) {
4917         tx_desc->txdw5 = cpu_to_le32(rate);
4918         tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
4919         tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
4920         tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
4921     }
4922 
4923     if (ieee80211_is_data_qos(hdr->frame_control))
4924         tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
4925 
4926     if (short_preamble)
4927         tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
4928 
4929     if (sgi)
4930         tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
4931 
4932     /*
4933      * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
4934      */
4935     tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
4936     if (ampdu_enable || (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
4937         tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
4938         tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
4939     } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
4940         tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
4941         tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
4942     }
4943 }
4944 
4945 /*
4946  * Fill in v2 (gen2) specific TX descriptor bits.
4947  * This format is used on 8192eu/8723bu
4948  */
4949 void
4950 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
4951             struct ieee80211_tx_info *tx_info,
4952             struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
4953             bool short_preamble, bool ampdu_enable, u32 rts_rate)
4954 {
4955     struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4956     struct rtl8xxxu_priv *priv = hw->priv;
4957     struct device *dev = &priv->udev->dev;
4958     struct rtl8xxxu_txdesc40 *tx_desc40;
4959     u8 *qc = ieee80211_get_qos_ctl(hdr);
4960     u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
4961     u32 rate;
4962     u16 rate_flags = tx_info->control.rates[0].flags;
4963     u16 seq_number;
4964 
4965     tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32;
4966 
4967     if (rate_flags & IEEE80211_TX_RC_MCS &&
4968         !ieee80211_is_mgmt(hdr->frame_control))
4969         rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4970     else
4971         rate = tx_rate->hw_value;
4972 
4973     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4974         dev_info(dev, "%s: TX rate: %d, pkt size %u\n",
4975              __func__, rate, le16_to_cpu(tx_desc40->pkt_size));
4976 
4977     seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4978 
4979     tx_desc40->txdw4 = cpu_to_le32(rate);
4980     if (ieee80211_is_data(hdr->frame_control)) {
4981         tx_desc40->txdw4 |= cpu_to_le32(0x1f <<
4982                         TXDESC40_DATA_RATE_FB_SHIFT);
4983     }
4984 
4985     tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
4986 
4987     if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
4988         tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
4989     else
4990         tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
4991 
4992     if (ieee80211_is_mgmt(hdr->frame_control)) {
4993         tx_desc40->txdw4 = cpu_to_le32(rate);
4994         tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
4995         tx_desc40->txdw4 |=
4996             cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
4997         tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
4998     }
4999 
5000     if (short_preamble)
5001         tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
5002 
5003     tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT);
5004     /*
5005      * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
5006      */
5007     if (ampdu_enable || (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
5008         tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
5009         tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
5010     } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
5011         /*
5012          * For some reason the vendor driver doesn't set
5013          * TXDESC40_HW_RTS_ENABLE for CTS to SELF
5014          */
5015         tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE);
5016     }
5017 }
5018 
5019 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
5020             struct ieee80211_tx_control *control,
5021             struct sk_buff *skb)
5022 {
5023     struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5024     struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
5025     struct rtl8xxxu_priv *priv = hw->priv;
5026     struct rtl8xxxu_txdesc32 *tx_desc;
5027     struct rtl8xxxu_tx_urb *tx_urb;
5028     struct ieee80211_sta *sta = NULL;
5029     struct ieee80211_vif *vif = tx_info->control.vif;
5030     struct device *dev = &priv->udev->dev;
5031     u32 queue, rts_rate;
5032     u16 pktlen = skb->len;
5033     u16 rate_flag = tx_info->control.rates[0].flags;
5034     int tx_desc_size = priv->fops->tx_desc_size;
5035     int ret;
5036     bool ampdu_enable, sgi = false, short_preamble = false;
5037 
5038     if (skb_headroom(skb) < tx_desc_size) {
5039         dev_warn(dev,
5040              "%s: Not enough headroom (%i) for tx descriptor\n",
5041              __func__, skb_headroom(skb));
5042         goto error;
5043     }
5044 
5045     if (unlikely(skb->len > (65535 - tx_desc_size))) {
5046         dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
5047              __func__, skb->len);
5048         goto error;
5049     }
5050 
5051     tx_urb = rtl8xxxu_alloc_tx_urb(priv);
5052     if (!tx_urb) {
5053         dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
5054         goto error;
5055     }
5056 
5057     if (ieee80211_is_action(hdr->frame_control))
5058         rtl8xxxu_dump_action(dev, hdr);
5059 
5060     tx_info->rate_driver_data[0] = hw;
5061 
5062     if (control && control->sta)
5063         sta = control->sta;
5064 
5065     tx_desc = skb_push(skb, tx_desc_size);
5066 
5067     memset(tx_desc, 0, tx_desc_size);
5068     tx_desc->pkt_size = cpu_to_le16(pktlen);
5069     tx_desc->pkt_offset = tx_desc_size;
5070 
5071     tx_desc->txdw0 =
5072         TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
5073     if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
5074         is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
5075         tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
5076 
5077     queue = rtl8xxxu_queue_select(hw, skb);
5078     tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
5079 
5080     if (tx_info->control.hw_key) {
5081         switch (tx_info->control.hw_key->cipher) {
5082         case WLAN_CIPHER_SUITE_WEP40:
5083         case WLAN_CIPHER_SUITE_WEP104:
5084         case WLAN_CIPHER_SUITE_TKIP:
5085             tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
5086             break;
5087         case WLAN_CIPHER_SUITE_CCMP:
5088             tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
5089             break;
5090         default:
5091             break;
5092         }
5093     }
5094 
5095     /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
5096     ampdu_enable = false;
5097     if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
5098         if (sta->deflink.ht_cap.ht_supported) {
5099             u32 ampdu, val32;
5100             u8 *qc = ieee80211_get_qos_ctl(hdr);
5101             u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5102 
5103             ampdu = (u32)sta->deflink.ht_cap.ampdu_density;
5104             val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
5105             tx_desc->txdw2 |= cpu_to_le32(val32);
5106 
5107             ampdu_enable = true;
5108 
5109             if (!test_bit(tid, priv->tx_aggr_started) &&
5110                 !(skb->protocol == cpu_to_be16(ETH_P_PAE)))
5111                 if (!ieee80211_start_tx_ba_session(sta, tid, 0))
5112                     set_bit(tid, priv->tx_aggr_started);
5113         }
5114     }
5115 
5116     if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
5117         (ieee80211_is_data_qos(hdr->frame_control) &&
5118          sta && sta->deflink.ht_cap.cap &
5119          (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)))
5120         sgi = true;
5121 
5122     if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
5123         (sta && vif && vif->bss_conf.use_short_preamble))
5124         short_preamble = true;
5125 
5126     if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS)
5127         rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value;
5128     else if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT)
5129         rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value;
5130     else
5131         rts_rate = 0;
5132 
5133 
5134     priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble,
5135                 ampdu_enable, rts_rate);
5136 
5137     rtl8xxxu_calc_tx_desc_csum(tx_desc);
5138 
5139     usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5140               skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5141 
5142     usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5143     ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5144     if (ret) {
5145         usb_unanchor_urb(&tx_urb->urb);
5146         rtl8xxxu_free_tx_urb(priv, tx_urb);
5147         goto error;
5148     }
5149     return;
5150 error:
5151     dev_kfree_skb(skb);
5152 }
5153 
5154 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5155                        struct ieee80211_rx_status *rx_status,
5156                        struct rtl8723au_phy_stats *phy_stats,
5157                        u32 rxmcs)
5158 {
5159     if (phy_stats->sgi_en)
5160         rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
5161 
5162     if (rxmcs < DESC_RATE_6M) {
5163         /*
5164          * Handle PHY stats for CCK rates
5165          */
5166         u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
5167 
5168         switch (cck_agc_rpt & 0xc0) {
5169         case 0xc0:
5170             rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
5171             break;
5172         case 0x80:
5173             rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
5174             break;
5175         case 0x40:
5176             rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
5177             break;
5178         case 0x00:
5179             rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
5180             break;
5181         }
5182     } else {
5183         rx_status->signal =
5184             (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5185     }
5186 }
5187 
5188 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5189 {
5190     struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5191     unsigned long flags;
5192 
5193     spin_lock_irqsave(&priv->rx_urb_lock, flags);
5194 
5195     list_for_each_entry_safe(rx_urb, tmp,
5196                  &priv->rx_urb_pending_list, list) {
5197         list_del(&rx_urb->list);
5198         priv->rx_urb_pending_count--;
5199         usb_free_urb(&rx_urb->urb);
5200     }
5201 
5202     spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5203 }
5204 
5205 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5206                   struct rtl8xxxu_rx_urb *rx_urb)
5207 {
5208     struct sk_buff *skb;
5209     unsigned long flags;
5210     int pending = 0;
5211 
5212     spin_lock_irqsave(&priv->rx_urb_lock, flags);
5213 
5214     if (!priv->shutdown) {
5215         list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5216         priv->rx_urb_pending_count++;
5217         pending = priv->rx_urb_pending_count;
5218     } else {
5219         skb = (struct sk_buff *)rx_urb->urb.context;
5220         dev_kfree_skb(skb);
5221         usb_free_urb(&rx_urb->urb);
5222     }
5223 
5224     spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5225 
5226     if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5227         schedule_work(&priv->rx_urb_wq);
5228 }
5229 
5230 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5231 {
5232     struct rtl8xxxu_priv *priv;
5233     struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5234     struct list_head local;
5235     struct sk_buff *skb;
5236     unsigned long flags;
5237     int ret;
5238 
5239     priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5240     INIT_LIST_HEAD(&local);
5241 
5242     spin_lock_irqsave(&priv->rx_urb_lock, flags);
5243 
5244     list_splice_init(&priv->rx_urb_pending_list, &local);
5245     priv->rx_urb_pending_count = 0;
5246 
5247     spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5248 
5249     list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5250         list_del_init(&rx_urb->list);
5251         ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5252         /*
5253          * If out of memory or temporary error, put it back on the
5254          * queue and try again. Otherwise the device is dead/gone
5255          * and we should drop it.
5256          */
5257         switch (ret) {
5258         case 0:
5259             break;
5260         case -ENOMEM:
5261         case -EAGAIN:
5262             rtl8xxxu_queue_rx_urb(priv, rx_urb);
5263             break;
5264         default:
5265             pr_info("failed to requeue urb %i\n", ret);
5266             skb = (struct sk_buff *)rx_urb->urb.context;
5267             dev_kfree_skb(skb);
5268             usb_free_urb(&rx_urb->urb);
5269         }
5270     }
5271 }
5272 
5273 /*
5274  * The RTL8723BU/RTL8192EU vendor driver use coexistence table type
5275  * 0-7 to represent writing different combinations of register values
5276  * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use
5277  * cases which Realtek doesn't provide detail for these settings. Keep
5278  * this aligned with vendor driver for easier maintenance.
5279  */
5280 static
5281 void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type)
5282 {
5283     switch (type) {
5284     case 0:
5285         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5286         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
5287         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5288         rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5289         break;
5290     case 1:
5291     case 3:
5292         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5293         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5294         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5295         rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5296         break;
5297     case 2:
5298         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5299         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5300         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5301         rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5302         break;
5303     case 4:
5304         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5305         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a);
5306         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5307         rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5308         break;
5309     case 5:
5310         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5311         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a);
5312         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5313         rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5314         break;
5315     case 6:
5316         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5317         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa);
5318         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5319         rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5320         break;
5321     case 7:
5322         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa);
5323         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa);
5324         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5325         rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5326         break;
5327     default:
5328         break;
5329     }
5330 }
5331 
5332 static
5333 void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info)
5334 {
5335     struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex;
5336 
5337     if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE)
5338         btcoex->c2h_bt_inquiry = true;
5339     else
5340         btcoex->c2h_bt_inquiry = false;
5341 
5342     if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) {
5343         btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE;
5344         btcoex->has_sco = false;
5345         btcoex->has_hid = false;
5346         btcoex->has_pan = false;
5347         btcoex->has_a2dp = false;
5348     } else {
5349         if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION)
5350             btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE;
5351         else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) ||
5352              (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY))
5353             btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY;
5354         else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY)
5355             btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY;
5356         else
5357             btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX;
5358 
5359         if (bt_info & BT_INFO_8723B_1ANT_B_FTP)
5360             btcoex->has_pan = true;
5361         else
5362             btcoex->has_pan = false;
5363 
5364         if (bt_info & BT_INFO_8723B_1ANT_B_A2DP)
5365             btcoex->has_a2dp = true;
5366         else
5367             btcoex->has_a2dp = false;
5368 
5369         if (bt_info & BT_INFO_8723B_1ANT_B_HID)
5370             btcoex->has_hid = true;
5371         else
5372             btcoex->has_hid = false;
5373 
5374         if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO)
5375             btcoex->has_sco = true;
5376         else
5377             btcoex->has_sco = false;
5378     }
5379 
5380     if (!btcoex->has_a2dp && !btcoex->has_sco &&
5381         !btcoex->has_pan && btcoex->has_hid)
5382         btcoex->hid_only = true;
5383     else
5384         btcoex->hid_only = false;
5385 
5386     if (!btcoex->has_sco && !btcoex->has_pan &&
5387         !btcoex->has_hid && btcoex->has_a2dp)
5388         btcoex->has_a2dp = true;
5389     else
5390         btcoex->has_a2dp = false;
5391 
5392     if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY ||
5393         btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY)
5394         btcoex->bt_busy = true;
5395     else
5396         btcoex->bt_busy = false;
5397 }
5398 
5399 static
5400 void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv)
5401 {
5402     struct ieee80211_vif *vif;
5403     struct rtl8xxxu_btcoex *btcoex;
5404     bool wifi_connected;
5405 
5406     vif = priv->vif;
5407     btcoex = &priv->bt_coex;
5408     wifi_connected = (vif && vif->cfg.assoc);
5409 
5410     if (!wifi_connected) {
5411         rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
5412         rtl8723bu_set_coex_with_type(priv, 0);
5413     } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) {
5414         rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11);
5415         rtl8723bu_set_coex_with_type(priv, 4);
5416     } else if (btcoex->has_pan) {
5417         rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11);
5418         rtl8723bu_set_coex_with_type(priv, 4);
5419     } else {
5420         rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
5421         rtl8723bu_set_coex_with_type(priv, 7);
5422     }
5423 }
5424 
5425 static
5426 void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv)
5427 {
5428     struct ieee80211_vif *vif;
5429     struct rtl8xxxu_btcoex *btcoex;
5430     bool wifi_connected;
5431 
5432     vif = priv->vif;
5433     btcoex = &priv->bt_coex;
5434     wifi_connected = (vif && vif->cfg.assoc);
5435 
5436     if (wifi_connected) {
5437         u32 val32 = 0;
5438         u32 high_prio_tx = 0, high_prio_rx = 0;
5439 
5440         val32 = rtl8xxxu_read32(priv, 0x770);
5441         high_prio_tx = val32 & 0x0000ffff;
5442         high_prio_rx = (val32  & 0xffff0000) >> 16;
5443 
5444         if (btcoex->bt_busy) {
5445             if (btcoex->hid_only) {
5446                 rtl8723bu_set_ps_tdma(priv, 0x61, 0x20,
5447                               0x3, 0x11, 0x11);
5448                 rtl8723bu_set_coex_with_type(priv, 5);
5449             } else if (btcoex->a2dp_only) {
5450                 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35,
5451                               0x3, 0x11, 0x11);
5452                 rtl8723bu_set_coex_with_type(priv, 4);
5453             } else if ((btcoex->has_a2dp && btcoex->has_pan) ||
5454                    (btcoex->has_hid && btcoex->has_a2dp &&
5455                     btcoex->has_pan)) {
5456                 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21,
5457                               0x3, 0x10, 0x10);
5458                 rtl8723bu_set_coex_with_type(priv, 4);
5459             } else if (btcoex->has_hid && btcoex->has_a2dp) {
5460                 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21,
5461                               0x3, 0x10, 0x10);
5462                 rtl8723bu_set_coex_with_type(priv, 3);
5463             } else {
5464                 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35,
5465                               0x3, 0x11, 0x11);
5466                 rtl8723bu_set_coex_with_type(priv, 4);
5467             }
5468         } else {
5469             rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
5470             if (high_prio_tx + high_prio_rx <= 60)
5471                 rtl8723bu_set_coex_with_type(priv, 2);
5472             else
5473                 rtl8723bu_set_coex_with_type(priv, 7);
5474         }
5475     } else {
5476         rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
5477         rtl8723bu_set_coex_with_type(priv, 0);
5478     }
5479 }
5480 
5481 static void rtl8xxxu_c2hcmd_callback(struct work_struct *work)
5482 {
5483     struct rtl8xxxu_priv *priv;
5484     struct rtl8723bu_c2h *c2h;
5485     struct sk_buff *skb = NULL;
5486     u8 bt_info = 0;
5487     struct rtl8xxxu_btcoex *btcoex;
5488     struct rtl8xxxu_ra_report *rarpt;
5489     u8 rate, sgi, bw;
5490     u32 bit_rate;
5491     u8 mcs = 0, nss = 0;
5492 
5493     priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work);
5494     btcoex = &priv->bt_coex;
5495     rarpt = &priv->ra_report;
5496 
5497     if (priv->rf_paths > 1)
5498         goto out;
5499 
5500     while (!skb_queue_empty(&priv->c2hcmd_queue)) {
5501         skb = skb_dequeue(&priv->c2hcmd_queue);
5502 
5503         c2h = (struct rtl8723bu_c2h *)skb->data;
5504 
5505         switch (c2h->id) {
5506         case C2H_8723B_BT_INFO:
5507             bt_info = c2h->bt_info.bt_info;
5508 
5509             rtl8723bu_update_bt_link_info(priv, bt_info);
5510             if (btcoex->c2h_bt_inquiry) {
5511                 rtl8723bu_handle_bt_inquiry(priv);
5512                 break;
5513             }
5514             rtl8723bu_handle_bt_info(priv);
5515             break;
5516         case C2H_8723B_RA_REPORT:
5517             rarpt->txrate.flags = 0;
5518             rate = c2h->ra_report.rate;
5519             sgi = c2h->ra_report.sgi;
5520             bw = c2h->ra_report.bw;
5521 
5522             if (rate < DESC_RATE_MCS0) {
5523                 rarpt->txrate.legacy =
5524                     rtl8xxxu_legacy_ratetable[rate].bitrate;
5525             } else {
5526                 rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss);
5527                 rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS;
5528 
5529                 rarpt->txrate.mcs = mcs;
5530                 rarpt->txrate.nss = nss;
5531 
5532                 if (sgi) {
5533                     rarpt->txrate.flags |=
5534                         RATE_INFO_FLAGS_SHORT_GI;
5535                 }
5536 
5537                 if (bw == RATE_INFO_BW_20)
5538                     rarpt->txrate.bw |= RATE_INFO_BW_20;
5539             }
5540             bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate);
5541             rarpt->bit_rate = bit_rate;
5542             rarpt->desc_rate = rate;
5543             break;
5544         default:
5545             break;
5546         }
5547     }
5548 
5549 out:
5550     dev_kfree_skb(skb);
5551 }
5552 
5553 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
5554                  struct sk_buff *skb)
5555 {
5556     struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
5557     struct device *dev = &priv->udev->dev;
5558     int len;
5559 
5560     len = skb->len - 2;
5561 
5562     dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
5563         c2h->id, c2h->seq, len, c2h->bt_info.response_source);
5564 
5565     switch(c2h->id) {
5566     case C2H_8723B_BT_INFO:
5567         if (c2h->bt_info.response_source >
5568             BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
5569             dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
5570         else
5571             dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
5572 
5573         if (c2h->bt_info.bt_has_reset)
5574             dev_dbg(dev, "BT has been reset\n");
5575         if (c2h->bt_info.tx_rx_mask)
5576             dev_dbg(dev, "BT TRx mask\n");
5577 
5578         break;
5579     case C2H_8723B_BT_MP_INFO:
5580         dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
5581             c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
5582         break;
5583     case C2H_8723B_RA_REPORT:
5584         dev_dbg(dev,
5585             "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
5586             c2h->ra_report.rate, c2h->ra_report.sgi,
5587             c2h->ra_report.macid, c2h->ra_report.noisy_state);
5588         break;
5589     default:
5590         dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
5591              c2h->id, c2h->seq);
5592         print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
5593                    16, 1, c2h->raw.payload, len, false);
5594         break;
5595     }
5596 
5597     skb_queue_tail(&priv->c2hcmd_queue, skb);
5598 
5599     schedule_work(&priv->c2hcmd_work);
5600 }
5601 
5602 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
5603 {
5604     struct ieee80211_hw *hw = priv->hw;
5605     struct ieee80211_rx_status *rx_status;
5606     struct rtl8xxxu_rxdesc16 *rx_desc;
5607     struct rtl8723au_phy_stats *phy_stats;
5608     struct sk_buff *next_skb = NULL;
5609     __le32 *_rx_desc_le;
5610     u32 *_rx_desc;
5611     int drvinfo_sz, desc_shift;
5612     int i, pkt_cnt, pkt_len, urb_len, pkt_offset;
5613 
5614     urb_len = skb->len;
5615     pkt_cnt = 0;
5616 
5617     if (urb_len < sizeof(struct rtl8xxxu_rxdesc16)) {
5618         kfree_skb(skb);
5619         return RX_TYPE_ERROR;
5620     }
5621 
5622     do {
5623         rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data;
5624         _rx_desc_le = (__le32 *)skb->data;
5625         _rx_desc = (u32 *)skb->data;
5626 
5627         for (i = 0;
5628              i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)
5629             _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5630 
5631         /*
5632          * Only read pkt_cnt from the header if we're parsing the
5633          * first packet
5634          */
5635         if (!pkt_cnt)
5636             pkt_cnt = rx_desc->pkt_cnt;
5637         pkt_len = rx_desc->pktlen;
5638 
5639         drvinfo_sz = rx_desc->drvinfo_sz * 8;
5640         desc_shift = rx_desc->shift;
5641         pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
5642                      sizeof(struct rtl8xxxu_rxdesc16), 128);
5643 
5644         /*
5645          * Only clone the skb if there's enough data at the end to
5646          * at least cover the rx descriptor
5647          */
5648         if (pkt_cnt > 1 &&
5649             urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16)))
5650             next_skb = skb_clone(skb, GFP_ATOMIC);
5651 
5652         rx_status = IEEE80211_SKB_RXCB(skb);
5653         memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5654 
5655         skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));
5656 
5657         phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5658 
5659         skb_pull(skb, drvinfo_sz + desc_shift);
5660 
5661         skb_trim(skb, pkt_len);
5662 
5663         if (rx_desc->phy_stats)
5664             rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
5665                            rx_desc->rxmcs);
5666 
5667         rx_status->mactime = rx_desc->tsfl;
5668         rx_status->flag |= RX_FLAG_MACTIME_START;
5669 
5670         if (!rx_desc->swdec)
5671             rx_status->flag |= RX_FLAG_DECRYPTED;
5672         if (rx_desc->crc32)
5673             rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5674         if (rx_desc->bw)
5675             rx_status->bw = RATE_INFO_BW_40;
5676 
5677         if (rx_desc->rxht) {
5678             rx_status->encoding = RX_ENC_HT;
5679             rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5680         } else {
5681             rx_status->rate_idx = rx_desc->rxmcs;
5682         }
5683 
5684         rx_status->freq = hw->conf.chandef.chan->center_freq;
5685         rx_status->band = hw->conf.chandef.chan->band;
5686 
5687         ieee80211_rx_irqsafe(hw, skb);
5688 
5689         skb = next_skb;
5690         if (skb)
5691             skb_pull(next_skb, pkt_offset);
5692 
5693         pkt_cnt--;
5694         urb_len -= pkt_offset;
5695         next_skb = NULL;
5696     } while (skb && pkt_cnt > 0 &&
5697          urb_len >= sizeof(struct rtl8xxxu_rxdesc16));
5698 
5699     return RX_TYPE_DATA_PKT;
5700 }
5701 
5702 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
5703 {
5704     struct ieee80211_hw *hw = priv->hw;
5705     struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5706     struct rtl8xxxu_rxdesc24 *rx_desc =
5707         (struct rtl8xxxu_rxdesc24 *)skb->data;
5708     struct rtl8723au_phy_stats *phy_stats;
5709     __le32 *_rx_desc_le = (__le32 *)skb->data;
5710     u32 *_rx_desc = (u32 *)skb->data;
5711     int drvinfo_sz, desc_shift;
5712     int i;
5713 
5714     for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
5715         _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5716 
5717     memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5718 
5719     skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
5720 
5721     phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5722 
5723     drvinfo_sz = rx_desc->drvinfo_sz * 8;
5724     desc_shift = rx_desc->shift;
5725     skb_pull(skb, drvinfo_sz + desc_shift);
5726 
5727     if (rx_desc->rpt_sel) {
5728         struct device *dev = &priv->udev->dev;
5729         dev_dbg(dev, "%s: C2H packet\n", __func__);
5730         rtl8723bu_handle_c2h(priv, skb);
5731         return RX_TYPE_C2H;
5732     }
5733 
5734     if (rx_desc->phy_stats)
5735         rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
5736                        rx_desc->rxmcs);
5737 
5738     rx_status->mactime = rx_desc->tsfl;
5739     rx_status->flag |= RX_FLAG_MACTIME_START;
5740 
5741     if (!rx_desc->swdec)
5742         rx_status->flag |= RX_FLAG_DECRYPTED;
5743     if (rx_desc->crc32)
5744         rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5745     if (rx_desc->bw)
5746         rx_status->bw = RATE_INFO_BW_40;
5747 
5748     if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
5749         rx_status->encoding = RX_ENC_HT;
5750         rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5751     } else {
5752         rx_status->rate_idx = rx_desc->rxmcs;
5753     }
5754 
5755     rx_status->freq = hw->conf.chandef.chan->center_freq;
5756     rx_status->band = hw->conf.chandef.chan->band;
5757 
5758     ieee80211_rx_irqsafe(hw, skb);
5759     return RX_TYPE_DATA_PKT;
5760 }
5761 
5762 static void rtl8xxxu_rx_complete(struct urb *urb)
5763 {
5764     struct rtl8xxxu_rx_urb *rx_urb =
5765         container_of(urb, struct rtl8xxxu_rx_urb, urb);
5766     struct ieee80211_hw *hw = rx_urb->hw;
5767     struct rtl8xxxu_priv *priv = hw->priv;
5768     struct sk_buff *skb = (struct sk_buff *)urb->context;
5769     struct device *dev = &priv->udev->dev;
5770 
5771     skb_put(skb, urb->actual_length);
5772 
5773     if (urb->status == 0) {
5774         priv->fops->parse_rx_desc(priv, skb);
5775 
5776         skb = NULL;
5777         rx_urb->urb.context = NULL;
5778         rtl8xxxu_queue_rx_urb(priv, rx_urb);
5779     } else {
5780         dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5781         goto cleanup;
5782     }
5783     return;
5784 
5785 cleanup:
5786     usb_free_urb(urb);
5787     dev_kfree_skb(skb);
5788     return;
5789 }
5790 
5791 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5792                   struct rtl8xxxu_rx_urb *rx_urb)
5793 {
5794     struct rtl8xxxu_fileops *fops = priv->fops;
5795     struct sk_buff *skb;
5796     int skb_size;
5797     int ret, rx_desc_sz;
5798 
5799     rx_desc_sz = fops->rx_desc_size;
5800 
5801     if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) {
5802         skb_size = fops->rx_agg_buf_size;
5803         skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats));
5804     } else {
5805         skb_size = IEEE80211_MAX_FRAME_LEN;
5806     }
5807 
5808     skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5809     if (!skb)
5810         return -ENOMEM;
5811 
5812     memset(skb->data, 0, rx_desc_sz);
5813     usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5814               skb_size, rtl8xxxu_rx_complete, skb);
5815     usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5816     ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5817     if (ret)
5818         usb_unanchor_urb(&rx_urb->urb);
5819     return ret;
5820 }
5821 
5822 static void rtl8xxxu_int_complete(struct urb *urb)
5823 {
5824     struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5825     struct device *dev = &priv->udev->dev;
5826     int ret;
5827 
5828     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT)
5829         dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5830     if (urb->status == 0) {
5831         usb_anchor_urb(urb, &priv->int_anchor);
5832         ret = usb_submit_urb(urb, GFP_ATOMIC);
5833         if (ret)
5834             usb_unanchor_urb(urb);
5835     } else {
5836         dev_dbg(dev, "%s: Error %i\n", __func__, urb->status);
5837     }
5838 }
5839 
5840 
5841 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5842 {
5843     struct rtl8xxxu_priv *priv = hw->priv;
5844     struct urb *urb;
5845     u32 val32;
5846     int ret;
5847 
5848     urb = usb_alloc_urb(0, GFP_KERNEL);
5849     if (!urb)
5850         return -ENOMEM;
5851 
5852     usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5853              priv->int_buf, USB_INTR_CONTENT_LENGTH,
5854              rtl8xxxu_int_complete, priv, 1);
5855     usb_anchor_urb(urb, &priv->int_anchor);
5856     ret = usb_submit_urb(urb, GFP_KERNEL);
5857     if (ret) {
5858         usb_unanchor_urb(urb);
5859         goto error;
5860     }
5861 
5862     val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5863     val32 |= USB_HIMR_CPWM;
5864     rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5865 
5866 error:
5867     usb_free_urb(urb);
5868     return ret;
5869 }
5870 
5871 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5872                   struct ieee80211_vif *vif)
5873 {
5874     struct rtl8xxxu_priv *priv = hw->priv;
5875     int ret;
5876     u8 val8;
5877 
5878     switch (vif->type) {
5879     case NL80211_IFTYPE_STATION:
5880         if (!priv->vif)
5881             priv->vif = vif;
5882         else
5883             return -EOPNOTSUPP;
5884         rtl8xxxu_stop_tx_beacon(priv);
5885 
5886         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5887         val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5888             BEACON_DISABLE_TSF_UPDATE;
5889         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5890         ret = 0;
5891         break;
5892     default:
5893         ret = -EOPNOTSUPP;
5894     }
5895 
5896     rtl8xxxu_set_linktype(priv, vif->type);
5897 
5898     return ret;
5899 }
5900 
5901 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5902                       struct ieee80211_vif *vif)
5903 {
5904     struct rtl8xxxu_priv *priv = hw->priv;
5905 
5906     dev_dbg(&priv->udev->dev, "%s\n", __func__);
5907 
5908     if (priv->vif)
5909         priv->vif = NULL;
5910 }
5911 
5912 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5913 {
5914     struct rtl8xxxu_priv *priv = hw->priv;
5915     struct device *dev = &priv->udev->dev;
5916     u16 val16;
5917     int ret = 0, channel;
5918     bool ht40;
5919 
5920     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5921         dev_info(dev,
5922              "%s: channel: %i (changed %08x chandef.width %02x)\n",
5923              __func__, hw->conf.chandef.chan->hw_value,
5924              changed, hw->conf.chandef.width);
5925 
5926     if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5927         val16 = ((hw->conf.long_frame_max_tx_count <<
5928               RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5929             ((hw->conf.short_frame_max_tx_count <<
5930               RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5931         rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5932     }
5933 
5934     if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5935         switch (hw->conf.chandef.width) {
5936         case NL80211_CHAN_WIDTH_20_NOHT:
5937         case NL80211_CHAN_WIDTH_20:
5938             ht40 = false;
5939             break;
5940         case NL80211_CHAN_WIDTH_40:
5941             ht40 = true;
5942             break;
5943         default:
5944             ret = -ENOTSUPP;
5945             goto exit;
5946         }
5947 
5948         channel = hw->conf.chandef.chan->hw_value;
5949 
5950         priv->fops->set_tx_power(priv, channel, ht40);
5951 
5952         priv->fops->config_channel(hw);
5953     }
5954 
5955 exit:
5956     return ret;
5957 }
5958 
5959 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5960                 struct ieee80211_vif *vif,
5961                 unsigned int link_id, u16 queue,
5962                 const struct ieee80211_tx_queue_params *param)
5963 {
5964     struct rtl8xxxu_priv *priv = hw->priv;
5965     struct device *dev = &priv->udev->dev;
5966     u32 val32;
5967     u8 aifs, acm_ctrl, acm_bit;
5968 
5969     aifs = param->aifs;
5970 
5971     val32 = aifs |
5972         fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5973         fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5974         (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5975 
5976     acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5977     dev_dbg(dev,
5978         "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5979         __func__, queue, val32, param->acm, acm_ctrl);
5980 
5981     switch (queue) {
5982     case IEEE80211_AC_VO:
5983         acm_bit = ACM_HW_CTRL_VO;
5984         rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5985         break;
5986     case IEEE80211_AC_VI:
5987         acm_bit = ACM_HW_CTRL_VI;
5988         rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5989         break;
5990     case IEEE80211_AC_BE:
5991         acm_bit = ACM_HW_CTRL_BE;
5992         rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5993         break;
5994     case IEEE80211_AC_BK:
5995         acm_bit = ACM_HW_CTRL_BK;
5996         rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5997         break;
5998     default:
5999         acm_bit = 0;
6000         break;
6001     }
6002 
6003     if (param->acm)
6004         acm_ctrl |= acm_bit;
6005     else
6006         acm_ctrl &= ~acm_bit;
6007     rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
6008 
6009     return 0;
6010 }
6011 
6012 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
6013                       unsigned int changed_flags,
6014                       unsigned int *total_flags, u64 multicast)
6015 {
6016     struct rtl8xxxu_priv *priv = hw->priv;
6017     u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
6018 
6019     dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
6020         __func__, changed_flags, *total_flags);
6021 
6022     /*
6023      * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
6024      */
6025 
6026     if (*total_flags & FIF_FCSFAIL)
6027         rcr |= RCR_ACCEPT_CRC32;
6028     else
6029         rcr &= ~RCR_ACCEPT_CRC32;
6030 
6031     /*
6032      * FIF_PLCPFAIL not supported?
6033      */
6034 
6035     if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
6036         rcr &= ~RCR_CHECK_BSSID_BEACON;
6037     else
6038         rcr |= RCR_CHECK_BSSID_BEACON;
6039 
6040     if (*total_flags & FIF_CONTROL)
6041         rcr |= RCR_ACCEPT_CTRL_FRAME;
6042     else
6043         rcr &= ~RCR_ACCEPT_CTRL_FRAME;
6044 
6045     if (*total_flags & FIF_OTHER_BSS) {
6046         rcr |= RCR_ACCEPT_AP;
6047         rcr &= ~RCR_CHECK_BSSID_MATCH;
6048     } else {
6049         rcr &= ~RCR_ACCEPT_AP;
6050         rcr |= RCR_CHECK_BSSID_MATCH;
6051     }
6052 
6053     if (*total_flags & FIF_PSPOLL)
6054         rcr |= RCR_ACCEPT_PM;
6055     else
6056         rcr &= ~RCR_ACCEPT_PM;
6057 
6058     /*
6059      * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
6060      */
6061 
6062     rtl8xxxu_write32(priv, REG_RCR, rcr);
6063 
6064     *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
6065              FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
6066              FIF_PROBE_REQ);
6067 }
6068 
6069 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
6070 {
6071     if (rts > 2347)
6072         return -EINVAL;
6073 
6074     return 0;
6075 }
6076 
6077 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6078                 struct ieee80211_vif *vif,
6079                 struct ieee80211_sta *sta,
6080                 struct ieee80211_key_conf *key)
6081 {
6082     struct rtl8xxxu_priv *priv = hw->priv;
6083     struct device *dev = &priv->udev->dev;
6084     u8 mac_addr[ETH_ALEN];
6085     u8 val8;
6086     u16 val16;
6087     u32 val32;
6088     int retval = -EOPNOTSUPP;
6089 
6090     dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
6091         __func__, cmd, key->cipher, key->keyidx);
6092 
6093     if (vif->type != NL80211_IFTYPE_STATION)
6094         return -EOPNOTSUPP;
6095 
6096     if (key->keyidx > 3)
6097         return -EOPNOTSUPP;
6098 
6099     switch (key->cipher) {
6100     case WLAN_CIPHER_SUITE_WEP40:
6101     case WLAN_CIPHER_SUITE_WEP104:
6102 
6103         break;
6104     case WLAN_CIPHER_SUITE_CCMP:
6105         key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6106         break;
6107     case WLAN_CIPHER_SUITE_TKIP:
6108         key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
6109         break;
6110     default:
6111         return -EOPNOTSUPP;
6112     }
6113 
6114     if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
6115         dev_dbg(dev, "%s: pairwise key\n", __func__);
6116         ether_addr_copy(mac_addr, sta->addr);
6117     } else {
6118         dev_dbg(dev, "%s: group key\n", __func__);
6119         eth_broadcast_addr(mac_addr);
6120     }
6121 
6122     val16 = rtl8xxxu_read16(priv, REG_CR);
6123     val16 |= CR_SECURITY_ENABLE;
6124     rtl8xxxu_write16(priv, REG_CR, val16);
6125 
6126     val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
6127         SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
6128     val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
6129     rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
6130 
6131     switch (cmd) {
6132     case SET_KEY:
6133         key->hw_key_idx = key->keyidx;
6134         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
6135         rtl8xxxu_cam_write(priv, key, mac_addr);
6136         retval = 0;
6137         break;
6138     case DISABLE_KEY:
6139         rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
6140         val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
6141             key->keyidx << CAM_CMD_KEY_SHIFT;
6142         rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
6143         retval = 0;
6144         break;
6145     default:
6146         dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
6147     }
6148 
6149     return retval;
6150 }
6151 
6152 static int
6153 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6154               struct ieee80211_ampdu_params *params)
6155 {
6156     struct rtl8xxxu_priv *priv = hw->priv;
6157     struct device *dev = &priv->udev->dev;
6158     u8 ampdu_factor, ampdu_density;
6159     struct ieee80211_sta *sta = params->sta;
6160     u16 tid = params->tid;
6161     enum ieee80211_ampdu_mlme_action action = params->action;
6162 
6163     switch (action) {
6164     case IEEE80211_AMPDU_TX_START:
6165         dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
6166         ampdu_factor = sta->deflink.ht_cap.ampdu_factor;
6167         ampdu_density = sta->deflink.ht_cap.ampdu_density;
6168         rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
6169         rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
6170         dev_dbg(dev,
6171             "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
6172             ampdu_factor, ampdu_density);
6173         return IEEE80211_AMPDU_TX_START_IMMEDIATE;
6174     case IEEE80211_AMPDU_TX_STOP_CONT:
6175     case IEEE80211_AMPDU_TX_STOP_FLUSH:
6176     case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6177         dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP\n", __func__);
6178         rtl8xxxu_set_ampdu_factor(priv, 0);
6179         rtl8xxxu_set_ampdu_min_space(priv, 0);
6180         clear_bit(tid, priv->tx_aggr_started);
6181         clear_bit(tid, priv->tid_tx_operational);
6182         ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6183         break;
6184     case IEEE80211_AMPDU_TX_OPERATIONAL:
6185         dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_OPERATIONAL\n", __func__);
6186         set_bit(tid, priv->tid_tx_operational);
6187         break;
6188     case IEEE80211_AMPDU_RX_START:
6189         dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
6190         break;
6191     case IEEE80211_AMPDU_RX_STOP:
6192         dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
6193         break;
6194     default:
6195         break;
6196     }
6197     return 0;
6198 }
6199 
6200 static void
6201 rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6202             struct ieee80211_sta *sta, struct station_info *sinfo)
6203 {
6204     struct rtl8xxxu_priv *priv = hw->priv;
6205 
6206     sinfo->txrate = priv->ra_report.txrate;
6207     sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
6208 }
6209 
6210 static u8 rtl8xxxu_signal_to_snr(int signal)
6211 {
6212     if (signal < RTL8XXXU_NOISE_FLOOR_MIN)
6213         signal = RTL8XXXU_NOISE_FLOOR_MIN;
6214     else if (signal > 0)
6215         signal = 0;
6216     return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN);
6217 }
6218 
6219 static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv,
6220                        int signal, struct ieee80211_sta *sta)
6221 {
6222     struct ieee80211_hw *hw = priv->hw;
6223     u16 wireless_mode;
6224     u8 rssi_level, ratr_idx;
6225     u8 txbw_40mhz;
6226     u8 snr, snr_thresh_high, snr_thresh_low;
6227     u8 go_up_gap = 5;
6228 
6229     rssi_level = priv->rssi_level;
6230     snr = rtl8xxxu_signal_to_snr(signal);
6231     snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH;
6232     snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW;
6233     txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0;
6234 
6235     switch (rssi_level) {
6236     case RTL8XXXU_RATR_STA_MID:
6237         snr_thresh_high += go_up_gap;
6238         break;
6239     case RTL8XXXU_RATR_STA_LOW:
6240         snr_thresh_high += go_up_gap;
6241         snr_thresh_low += go_up_gap;
6242         break;
6243     default:
6244         break;
6245     }
6246 
6247     if (snr > snr_thresh_high)
6248         rssi_level = RTL8XXXU_RATR_STA_HIGH;
6249     else if (snr > snr_thresh_low)
6250         rssi_level = RTL8XXXU_RATR_STA_MID;
6251     else
6252         rssi_level = RTL8XXXU_RATR_STA_LOW;
6253 
6254     if (rssi_level != priv->rssi_level) {
6255         int sgi = 0;
6256         u32 rate_bitmap = 0;
6257 
6258         rcu_read_lock();
6259         rate_bitmap = (sta->deflink.supp_rates[0] & 0xfff) |
6260                 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12) |
6261                 (sta->deflink.ht_cap.mcs.rx_mask[1] << 20);
6262         if (sta->deflink.ht_cap.cap &
6263             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6264             sgi = 1;
6265         rcu_read_unlock();
6266 
6267         wireless_mode = rtl8xxxu_wireless_mode(hw, sta);
6268         switch (wireless_mode) {
6269         case WIRELESS_MODE_B:
6270             ratr_idx = RATEID_IDX_B;
6271             if (rate_bitmap & 0x0000000c)
6272                 rate_bitmap &= 0x0000000d;
6273             else
6274                 rate_bitmap &= 0x0000000f;
6275             break;
6276         case WIRELESS_MODE_A:
6277         case WIRELESS_MODE_G:
6278             ratr_idx = RATEID_IDX_G;
6279             if (rssi_level == RTL8XXXU_RATR_STA_HIGH)
6280                 rate_bitmap &= 0x00000f00;
6281             else
6282                 rate_bitmap &= 0x00000ff0;
6283             break;
6284         case (WIRELESS_MODE_B | WIRELESS_MODE_G):
6285             ratr_idx = RATEID_IDX_BG;
6286             if (rssi_level == RTL8XXXU_RATR_STA_HIGH)
6287                 rate_bitmap &= 0x00000f00;
6288             else if (rssi_level == RTL8XXXU_RATR_STA_MID)
6289                 rate_bitmap &= 0x00000ff0;
6290             else
6291                 rate_bitmap &= 0x00000ff5;
6292             break;
6293         case WIRELESS_MODE_N_24G:
6294         case WIRELESS_MODE_N_5G:
6295         case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G):
6296         case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G):
6297             if (priv->tx_paths == 2 && priv->rx_paths == 2)
6298                 ratr_idx = RATEID_IDX_GN_N2SS;
6299             else
6300                 ratr_idx = RATEID_IDX_GN_N1SS;
6301             break;
6302         case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G):
6303         case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G):
6304             if (txbw_40mhz) {
6305                 if (priv->tx_paths == 2 && priv->rx_paths == 2)
6306                     ratr_idx = RATEID_IDX_BGN_40M_2SS;
6307                 else
6308                     ratr_idx = RATEID_IDX_BGN_40M_1SS;
6309             } else {
6310                 if (priv->tx_paths == 2 && priv->rx_paths == 2)
6311                     ratr_idx = RATEID_IDX_BGN_20M_2SS_BN;
6312                 else
6313                     ratr_idx = RATEID_IDX_BGN_20M_1SS_BN;
6314             }
6315 
6316             if (priv->tx_paths == 2 && priv->rx_paths == 2) {
6317                 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) {
6318                     rate_bitmap &= 0x0f8f0000;
6319                 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) {
6320                     rate_bitmap &= 0x0f8ff000;
6321                 } else {
6322                     if (txbw_40mhz)
6323                         rate_bitmap &= 0x0f8ff015;
6324                     else
6325                         rate_bitmap &= 0x0f8ff005;
6326                 }
6327             } else {
6328                 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) {
6329                     rate_bitmap &= 0x000f0000;
6330                 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) {
6331                     rate_bitmap &= 0x000ff000;
6332                 } else {
6333                     if (txbw_40mhz)
6334                         rate_bitmap &= 0x000ff015;
6335                     else
6336                         rate_bitmap &= 0x000ff005;
6337                 }
6338             }
6339             break;
6340         default:
6341             ratr_idx = RATEID_IDX_BGN_40M_2SS;
6342             rate_bitmap &= 0x0fffffff;
6343             break;
6344         }
6345 
6346         priv->rssi_level = rssi_level;
6347         priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi);
6348     }
6349 }
6350 
6351 static void rtl8xxxu_watchdog_callback(struct work_struct *work)
6352 {
6353     struct ieee80211_vif *vif;
6354     struct rtl8xxxu_priv *priv;
6355 
6356     priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work);
6357     vif = priv->vif;
6358 
6359     if (vif && vif->type == NL80211_IFTYPE_STATION) {
6360         int signal;
6361         struct ieee80211_sta *sta;
6362 
6363         rcu_read_lock();
6364         sta = ieee80211_find_sta(vif, vif->bss_conf.bssid);
6365         if (!sta) {
6366             struct device *dev = &priv->udev->dev;
6367 
6368             dev_dbg(dev, "%s: no sta found\n", __func__);
6369             rcu_read_unlock();
6370             goto out;
6371         }
6372         rcu_read_unlock();
6373 
6374         signal = ieee80211_ave_rssi(vif);
6375         rtl8xxxu_refresh_rate_mask(priv, signal, sta);
6376     }
6377 
6378 out:
6379     schedule_delayed_work(&priv->ra_watchdog, 2 * HZ);
6380 }
6381 
6382 static int rtl8xxxu_start(struct ieee80211_hw *hw)
6383 {
6384     struct rtl8xxxu_priv *priv = hw->priv;
6385     struct rtl8xxxu_rx_urb *rx_urb;
6386     struct rtl8xxxu_tx_urb *tx_urb;
6387     struct sk_buff *skb;
6388     unsigned long flags;
6389     int ret, i;
6390 
6391     ret = 0;
6392 
6393     init_usb_anchor(&priv->rx_anchor);
6394     init_usb_anchor(&priv->tx_anchor);
6395     init_usb_anchor(&priv->int_anchor);
6396 
6397     priv->fops->enable_rf(priv);
6398     if (priv->usb_interrupts) {
6399         ret = rtl8xxxu_submit_int_urb(hw);
6400         if (ret)
6401             goto exit;
6402     }
6403 
6404     for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
6405         tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
6406         if (!tx_urb) {
6407             if (!i)
6408                 ret = -ENOMEM;
6409 
6410             goto error_out;
6411         }
6412         usb_init_urb(&tx_urb->urb);
6413         INIT_LIST_HEAD(&tx_urb->list);
6414         tx_urb->hw = hw;
6415         list_add(&tx_urb->list, &priv->tx_urb_free_list);
6416         priv->tx_urb_free_count++;
6417     }
6418 
6419     priv->tx_stopped = false;
6420 
6421     spin_lock_irqsave(&priv->rx_urb_lock, flags);
6422     priv->shutdown = false;
6423     spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6424 
6425     for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
6426         rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
6427         if (!rx_urb) {
6428             if (!i)
6429                 ret = -ENOMEM;
6430 
6431             goto error_out;
6432         }
6433         usb_init_urb(&rx_urb->urb);
6434         INIT_LIST_HEAD(&rx_urb->list);
6435         rx_urb->hw = hw;
6436 
6437         ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
6438         if (ret) {
6439             if (ret != -ENOMEM) {
6440                 skb = (struct sk_buff *)rx_urb->urb.context;
6441                 dev_kfree_skb(skb);
6442             }
6443             rtl8xxxu_queue_rx_urb(priv, rx_urb);
6444         }
6445     }
6446 
6447     schedule_delayed_work(&priv->ra_watchdog, 2 * HZ);
6448 exit:
6449     /*
6450      * Accept all data and mgmt frames
6451      */
6452     rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
6453     rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
6454 
6455     rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
6456 
6457     return ret;
6458 
6459 error_out:
6460     rtl8xxxu_free_tx_resources(priv);
6461     /*
6462      * Disable all data and mgmt frames
6463      */
6464     rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
6465     rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
6466 
6467     return ret;
6468 }
6469 
6470 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
6471 {
6472     struct rtl8xxxu_priv *priv = hw->priv;
6473     unsigned long flags;
6474 
6475     rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6476 
6477     rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
6478     rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
6479 
6480     spin_lock_irqsave(&priv->rx_urb_lock, flags);
6481     priv->shutdown = true;
6482     spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6483 
6484     usb_kill_anchored_urbs(&priv->rx_anchor);
6485     usb_kill_anchored_urbs(&priv->tx_anchor);
6486     if (priv->usb_interrupts)
6487         usb_kill_anchored_urbs(&priv->int_anchor);
6488 
6489     rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6490 
6491     priv->fops->disable_rf(priv);
6492 
6493     /*
6494      * Disable interrupts
6495      */
6496     if (priv->usb_interrupts)
6497         rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
6498 
6499     cancel_delayed_work_sync(&priv->ra_watchdog);
6500 
6501     rtl8xxxu_free_rx_resources(priv);
6502     rtl8xxxu_free_tx_resources(priv);
6503 }
6504 
6505 static const struct ieee80211_ops rtl8xxxu_ops = {
6506     .tx = rtl8xxxu_tx,
6507     .add_interface = rtl8xxxu_add_interface,
6508     .remove_interface = rtl8xxxu_remove_interface,
6509     .config = rtl8xxxu_config,
6510     .conf_tx = rtl8xxxu_conf_tx,
6511     .bss_info_changed = rtl8xxxu_bss_info_changed,
6512     .configure_filter = rtl8xxxu_configure_filter,
6513     .set_rts_threshold = rtl8xxxu_set_rts_threshold,
6514     .start = rtl8xxxu_start,
6515     .stop = rtl8xxxu_stop,
6516     .sw_scan_start = rtl8xxxu_sw_scan_start,
6517     .sw_scan_complete = rtl8xxxu_sw_scan_complete,
6518     .set_key = rtl8xxxu_set_key,
6519     .ampdu_action = rtl8xxxu_ampdu_action,
6520     .sta_statistics = rtl8xxxu_sta_statistics,
6521     .get_antenna = rtl8xxxu_get_antenna,
6522 };
6523 
6524 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
6525                   struct usb_interface *interface)
6526 {
6527     struct usb_interface_descriptor *interface_desc;
6528     struct usb_host_interface *host_interface;
6529     struct usb_endpoint_descriptor *endpoint;
6530     struct device *dev = &priv->udev->dev;
6531     int i, j = 0, endpoints;
6532     u8 dir, xtype, num;
6533     int ret = 0;
6534 
6535     host_interface = interface->cur_altsetting;
6536     interface_desc = &host_interface->desc;
6537     endpoints = interface_desc->bNumEndpoints;
6538 
6539     for (i = 0; i < endpoints; i++) {
6540         endpoint = &host_interface->endpoint[i].desc;
6541 
6542         dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
6543         num = usb_endpoint_num(endpoint);
6544         xtype = usb_endpoint_type(endpoint);
6545         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6546             dev_dbg(dev,
6547                 "%s: endpoint: dir %02x, # %02x, type %02x\n",
6548                 __func__, dir, num, xtype);
6549         if (usb_endpoint_dir_in(endpoint) &&
6550             usb_endpoint_xfer_bulk(endpoint)) {
6551             if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6552                 dev_dbg(dev, "%s: in endpoint num %i\n",
6553                     __func__, num);
6554 
6555             if (priv->pipe_in) {
6556                 dev_warn(dev,
6557                      "%s: Too many IN pipes\n", __func__);
6558                 ret = -EINVAL;
6559                 goto exit;
6560             }
6561 
6562             priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
6563         }
6564 
6565         if (usb_endpoint_dir_in(endpoint) &&
6566             usb_endpoint_xfer_int(endpoint)) {
6567             if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6568                 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
6569                     __func__, num);
6570 
6571             if (priv->pipe_interrupt) {
6572                 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
6573                      __func__);
6574                 ret = -EINVAL;
6575                 goto exit;
6576             }
6577 
6578             priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
6579         }
6580 
6581         if (usb_endpoint_dir_out(endpoint) &&
6582             usb_endpoint_xfer_bulk(endpoint)) {
6583             if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6584                 dev_dbg(dev, "%s: out endpoint num %i\n",
6585                     __func__, num);
6586             if (j >= RTL8XXXU_OUT_ENDPOINTS) {
6587                 dev_warn(dev,
6588                      "%s: Too many OUT pipes\n", __func__);
6589                 ret = -EINVAL;
6590                 goto exit;
6591             }
6592             priv->out_ep[j++] = num;
6593         }
6594     }
6595 exit:
6596     priv->nr_out_eps = j;
6597     return ret;
6598 }
6599 
6600 static int rtl8xxxu_probe(struct usb_interface *interface,
6601               const struct usb_device_id *id)
6602 {
6603     struct rtl8xxxu_priv *priv;
6604     struct ieee80211_hw *hw;
6605     struct usb_device *udev;
6606     struct ieee80211_supported_band *sband;
6607     int ret;
6608     int untested = 1;
6609 
6610     udev = usb_get_dev(interface_to_usbdev(interface));
6611 
6612     switch (id->idVendor) {
6613     case USB_VENDOR_ID_REALTEK:
6614         switch(id->idProduct) {
6615         case 0x1724:
6616         case 0x8176:
6617         case 0x8178:
6618         case 0x817f:
6619         case 0x818b:
6620             untested = 0;
6621             break;
6622         }
6623         break;
6624     case 0x7392:
6625         if (id->idProduct == 0x7811 || id->idProduct == 0xa611)
6626             untested = 0;
6627         break;
6628     case 0x050d:
6629         if (id->idProduct == 0x1004)
6630             untested = 0;
6631         break;
6632     case 0x20f4:
6633         if (id->idProduct == 0x648b)
6634             untested = 0;
6635         break;
6636     case 0x2001:
6637         if (id->idProduct == 0x3308)
6638             untested = 0;
6639         break;
6640     case 0x2357:
6641         if (id->idProduct == 0x0109)
6642             untested = 0;
6643         break;
6644     default:
6645         break;
6646     }
6647 
6648     if (untested) {
6649         rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
6650         dev_info(&udev->dev,
6651              "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
6652              id->idVendor, id->idProduct);
6653         dev_info(&udev->dev,
6654              "Please report results to Jes.Sorensen@gmail.com\n");
6655     }
6656 
6657     hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
6658     if (!hw) {
6659         ret = -ENOMEM;
6660         priv = NULL;
6661         goto err_put_dev;
6662     }
6663 
6664     priv = hw->priv;
6665     priv->hw = hw;
6666     priv->udev = udev;
6667     priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
6668     mutex_init(&priv->usb_buf_mutex);
6669     mutex_init(&priv->h2c_mutex);
6670     INIT_LIST_HEAD(&priv->tx_urb_free_list);
6671     spin_lock_init(&priv->tx_urb_lock);
6672     INIT_LIST_HEAD(&priv->rx_urb_pending_list);
6673     spin_lock_init(&priv->rx_urb_lock);
6674     INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
6675     INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback);
6676     INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback);
6677     skb_queue_head_init(&priv->c2hcmd_queue);
6678 
6679     usb_set_intfdata(interface, hw);
6680 
6681     ret = rtl8xxxu_parse_usb(priv, interface);
6682     if (ret)
6683         goto err_set_intfdata;
6684 
6685     ret = rtl8xxxu_identify_chip(priv);
6686     if (ret) {
6687         dev_err(&udev->dev, "Fatal - failed to identify chip\n");
6688         goto err_set_intfdata;
6689     }
6690 
6691     ret = rtl8xxxu_read_efuse(priv);
6692     if (ret) {
6693         dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
6694         goto err_set_intfdata;
6695     }
6696 
6697     ret = priv->fops->parse_efuse(priv);
6698     if (ret) {
6699         dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
6700         goto err_set_intfdata;
6701     }
6702 
6703     rtl8xxxu_print_chipinfo(priv);
6704 
6705     ret = priv->fops->load_firmware(priv);
6706     if (ret) {
6707         dev_err(&udev->dev, "Fatal - failed to load firmware\n");
6708         goto err_set_intfdata;
6709     }
6710 
6711     ret = rtl8xxxu_init_device(hw);
6712     if (ret)
6713         goto err_set_intfdata;
6714 
6715     hw->wiphy->max_scan_ssids = 1;
6716     hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
6717     hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
6718     hw->queues = 4;
6719 
6720     sband = &rtl8xxxu_supported_band;
6721     sband->ht_cap.ht_supported = true;
6722     sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
6723     sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
6724     sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
6725     memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
6726     sband->ht_cap.mcs.rx_mask[0] = 0xff;
6727     sband->ht_cap.mcs.rx_mask[4] = 0x01;
6728     if (priv->rf_paths > 1) {
6729         sband->ht_cap.mcs.rx_mask[1] = 0xff;
6730         sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
6731     }
6732     sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
6733     /*
6734      * Some APs will negotiate HT20_40 in a noisy environment leading
6735      * to miserable performance. Rather than defaulting to this, only
6736      * enable it if explicitly requested at module load time.
6737      */
6738     if (rtl8xxxu_ht40_2g) {
6739         dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
6740         sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
6741     }
6742     hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
6743 
6744     hw->wiphy->rts_threshold = 2347;
6745 
6746     SET_IEEE80211_DEV(priv->hw, &interface->dev);
6747     SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
6748 
6749     hw->extra_tx_headroom = priv->fops->tx_desc_size;
6750     ieee80211_hw_set(hw, SIGNAL_DBM);
6751     /*
6752      * The firmware handles rate control
6753      */
6754     ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6755     ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6756 
6757     wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
6758 
6759     ret = ieee80211_register_hw(priv->hw);
6760     if (ret) {
6761         dev_err(&udev->dev, "%s: Failed to register: %i\n",
6762             __func__, ret);
6763         goto err_set_intfdata;
6764     }
6765 
6766     return 0;
6767 
6768 err_set_intfdata:
6769     usb_set_intfdata(interface, NULL);
6770 
6771     if (priv) {
6772         kfree(priv->fw_data);
6773         mutex_destroy(&priv->usb_buf_mutex);
6774         mutex_destroy(&priv->h2c_mutex);
6775     }
6776 
6777     ieee80211_free_hw(hw);
6778 err_put_dev:
6779     usb_put_dev(udev);
6780 
6781     return ret;
6782 }
6783 
6784 static void rtl8xxxu_disconnect(struct usb_interface *interface)
6785 {
6786     struct rtl8xxxu_priv *priv;
6787     struct ieee80211_hw *hw;
6788 
6789     hw = usb_get_intfdata(interface);
6790     priv = hw->priv;
6791 
6792     ieee80211_unregister_hw(hw);
6793 
6794     priv->fops->power_off(priv);
6795 
6796     usb_set_intfdata(interface, NULL);
6797 
6798     dev_info(&priv->udev->dev, "disconnecting\n");
6799 
6800     kfree(priv->fw_data);
6801     mutex_destroy(&priv->usb_buf_mutex);
6802     mutex_destroy(&priv->h2c_mutex);
6803 
6804     if (priv->udev->state != USB_STATE_NOTATTACHED) {
6805         dev_info(&priv->udev->dev,
6806              "Device still attached, trying to reset\n");
6807         usb_reset_device(priv->udev);
6808     }
6809     usb_put_dev(priv->udev);
6810     ieee80211_free_hw(hw);
6811 }
6812 
6813 static const struct usb_device_id dev_table[] = {
6814 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
6815     .driver_info = (unsigned long)&rtl8723au_fops},
6816 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
6817     .driver_info = (unsigned long)&rtl8723au_fops},
6818 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
6819     .driver_info = (unsigned long)&rtl8723au_fops},
6820 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
6821     .driver_info = (unsigned long)&rtl8192eu_fops},
6822 /* TP-Link TL-WN822N v4 */
6823 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff),
6824     .driver_info = (unsigned long)&rtl8192eu_fops},
6825 /* D-Link DWA-131 rev E1, tested by David Patiño */
6826 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff),
6827     .driver_info = (unsigned long)&rtl8192eu_fops},
6828 /* Tested by Myckel Habets */
6829 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff),
6830     .driver_info = (unsigned long)&rtl8192eu_fops},
6831 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
6832     .driver_info = (unsigned long)&rtl8723bu_fops},
6833 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff),
6834     .driver_info = (unsigned long)&rtl8723bu_fops},
6835 #ifdef CONFIG_RTL8XXXU_UNTESTED
6836 /* Still supported by rtlwifi */
6837 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
6838     .driver_info = (unsigned long)&rtl8192cu_fops},
6839 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
6840     .driver_info = (unsigned long)&rtl8192cu_fops},
6841 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
6842     .driver_info = (unsigned long)&rtl8192cu_fops},
6843 /* Tested by Larry Finger */
6844 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
6845     .driver_info = (unsigned long)&rtl8192cu_fops},
6846 /* Tested by Andrea Merello */
6847 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
6848     .driver_info = (unsigned long)&rtl8192cu_fops},
6849 /* Tested by Jocelyn Mayer */
6850 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
6851     .driver_info = (unsigned long)&rtl8192cu_fops},
6852 /* Tested by Stefano Bravi */
6853 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
6854     .driver_info = (unsigned long)&rtl8192cu_fops},
6855 /* Currently untested 8188 series devices */
6856 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff),
6857     .driver_info = (unsigned long)&rtl8192cu_fops},
6858 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
6859     .driver_info = (unsigned long)&rtl8192cu_fops},
6860 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
6861     .driver_info = (unsigned long)&rtl8192cu_fops},
6862 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
6863     .driver_info = (unsigned long)&rtl8192cu_fops},
6864 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
6865     .driver_info = (unsigned long)&rtl8192cu_fops},
6866 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
6867     .driver_info = (unsigned long)&rtl8192cu_fops},
6868 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
6869     .driver_info = (unsigned long)&rtl8192cu_fops},
6870 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
6871     .driver_info = (unsigned long)&rtl8192cu_fops},
6872 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
6873     .driver_info = (unsigned long)&rtl8192cu_fops},
6874 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
6875     .driver_info = (unsigned long)&rtl8192cu_fops},
6876 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
6877     .driver_info = (unsigned long)&rtl8192cu_fops},
6878 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
6879     .driver_info = (unsigned long)&rtl8192cu_fops},
6880 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
6881     .driver_info = (unsigned long)&rtl8192cu_fops},
6882 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
6883     .driver_info = (unsigned long)&rtl8192cu_fops},
6884 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
6885     .driver_info = (unsigned long)&rtl8192cu_fops},
6886 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
6887     .driver_info = (unsigned long)&rtl8192cu_fops},
6888 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
6889     .driver_info = (unsigned long)&rtl8192cu_fops},
6890 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
6891     .driver_info = (unsigned long)&rtl8192cu_fops},
6892 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
6893     .driver_info = (unsigned long)&rtl8192cu_fops},
6894 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
6895     .driver_info = (unsigned long)&rtl8192cu_fops},
6896 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
6897     .driver_info = (unsigned long)&rtl8192cu_fops},
6898 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
6899     .driver_info = (unsigned long)&rtl8192cu_fops},
6900 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
6901     .driver_info = (unsigned long)&rtl8192cu_fops},
6902 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
6903     .driver_info = (unsigned long)&rtl8192cu_fops},
6904 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
6905     .driver_info = (unsigned long)&rtl8192cu_fops},
6906 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
6907     .driver_info = (unsigned long)&rtl8192cu_fops},
6908 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
6909     .driver_info = (unsigned long)&rtl8192cu_fops},
6910 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
6911     .driver_info = (unsigned long)&rtl8192cu_fops},
6912 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
6913     .driver_info = (unsigned long)&rtl8192cu_fops},
6914 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
6915     .driver_info = (unsigned long)&rtl8192cu_fops},
6916 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
6917     .driver_info = (unsigned long)&rtl8192cu_fops},
6918 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
6919     .driver_info = (unsigned long)&rtl8192cu_fops},
6920 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
6921     .driver_info = (unsigned long)&rtl8192cu_fops},
6922 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
6923     .driver_info = (unsigned long)&rtl8192cu_fops},
6924 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
6925     .driver_info = (unsigned long)&rtl8192cu_fops},
6926 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
6927     .driver_info = (unsigned long)&rtl8192cu_fops},
6928 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
6929     .driver_info = (unsigned long)&rtl8192cu_fops},
6930 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
6931     .driver_info = (unsigned long)&rtl8192cu_fops},
6932 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
6933     .driver_info = (unsigned long)&rtl8192cu_fops},
6934 /* Currently untested 8192 series devices */
6935 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
6936     .driver_info = (unsigned long)&rtl8192cu_fops},
6937 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
6938     .driver_info = (unsigned long)&rtl8192cu_fops},
6939 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
6940     .driver_info = (unsigned long)&rtl8192cu_fops},
6941 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
6942     .driver_info = (unsigned long)&rtl8192cu_fops},
6943 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
6944     .driver_info = (unsigned long)&rtl8192cu_fops},
6945 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
6946     .driver_info = (unsigned long)&rtl8192cu_fops},
6947 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
6948     .driver_info = (unsigned long)&rtl8192cu_fops},
6949 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
6950     .driver_info = (unsigned long)&rtl8192cu_fops},
6951 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
6952     .driver_info = (unsigned long)&rtl8192cu_fops},
6953 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
6954     .driver_info = (unsigned long)&rtl8192cu_fops},
6955 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
6956     .driver_info = (unsigned long)&rtl8192cu_fops},
6957 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
6958     .driver_info = (unsigned long)&rtl8192cu_fops},
6959 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
6960     .driver_info = (unsigned long)&rtl8192cu_fops},
6961 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
6962     .driver_info = (unsigned long)&rtl8192cu_fops},
6963 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
6964     .driver_info = (unsigned long)&rtl8192cu_fops},
6965 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
6966     .driver_info = (unsigned long)&rtl8192cu_fops},
6967 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6968     .driver_info = (unsigned long)&rtl8192cu_fops},
6969 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6970     .driver_info = (unsigned long)&rtl8192cu_fops},
6971 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6972     .driver_info = (unsigned long)&rtl8192cu_fops},
6973 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6974     .driver_info = (unsigned long)&rtl8192cu_fops},
6975 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6976     .driver_info = (unsigned long)&rtl8192cu_fops},
6977 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6978     .driver_info = (unsigned long)&rtl8192cu_fops},
6979 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6980     .driver_info = (unsigned long)&rtl8192cu_fops},
6981 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6982     .driver_info = (unsigned long)&rtl8192cu_fops},
6983 /* found in rtl8192eu vendor driver */
6984 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff),
6985     .driver_info = (unsigned long)&rtl8192eu_fops},
6986 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff),
6987     .driver_info = (unsigned long)&rtl8192eu_fops},
6988 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff),
6989     .driver_info = (unsigned long)&rtl8192eu_fops},
6990 #endif
6991 { }
6992 };
6993 
6994 static struct usb_driver rtl8xxxu_driver = {
6995     .name = DRIVER_NAME,
6996     .probe = rtl8xxxu_probe,
6997     .disconnect = rtl8xxxu_disconnect,
6998     .id_table = dev_table,
6999     .no_dynamic_id = 1,
7000     .disable_hub_initiated_lpm = 1,
7001 };
7002 
7003 static int __init rtl8xxxu_module_init(void)
7004 {
7005     int res;
7006 
7007     res = usb_register(&rtl8xxxu_driver);
7008     if (res < 0)
7009         pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
7010 
7011     return res;
7012 }
7013 
7014 static void __exit rtl8xxxu_module_exit(void)
7015 {
7016     usb_deregister(&rtl8xxxu_driver);
7017 }
7018 
7019 
7020 MODULE_DEVICE_TABLE(usb, dev_table);
7021 
7022 module_init(rtl8xxxu_module_init);
7023 module_exit(rtl8xxxu_module_exit);
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