realtek/rtl8xxxu/rtl8xxxu_8723a.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * RTL8XXXU mac80211 USB driver - 8723a specific subdriver
0004  *
0005  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
0006  *
0007  * Portions, notably calibration code:
0008  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
0009  *
0010  * This driver was written as a replacement for the vendor provided
0011  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
0012  * their programming interface, I have started adding support for
0013  * additional 8xxx chips like the 8192cu, 8188cus, etc.
0014  */
0015
0016 #include <linux/init.h>
0017 #include <linux/kernel.h>
0018 #include <linux/sched.h>
0019 #include <linux/errno.h>
0020 #include <linux/slab.h>
0021 #include <linux/module.h>
0022 #include <linux/spinlock.h>
0023 #include <linux/list.h>
0024 #include <linux/usb.h>
0025 #include <linux/netdevice.h>
0026 #include <linux/etherdevice.h>
0027 #include <linux/ethtool.h>
0028 #include <linux/wireless.h>
0029 #include <linux/firmware.h>
0030 #include <linux/moduleparam.h>
0031 #include <net/mac80211.h>
0032 #include "rtl8xxxu.h"
0033 #include "rtl8xxxu_regs.h"
0034
0035 static struct rtl8xxxu_power_base rtl8723a_power_base = {
0036     .reg_0e00 = 0x0a0c0c0c,
0037     .reg_0e04 = 0x02040608,
0038     .reg_0e08 = 0x00000000,
0039     .reg_086c = 0x00000000,
0040
0041     .reg_0e10 = 0x0a0c0d0e,
0042     .reg_0e14 = 0x02040608,
0043     .reg_0e18 = 0x0a0c0d0e,
0044     .reg_0e1c = 0x02040608,
0045
0046     .reg_0830 = 0x0a0c0c0c,
0047     .reg_0834 = 0x02040608,
0048     .reg_0838 = 0x00000000,
0049     .reg_086c_2 = 0x00000000,
0050
0051     .reg_083c = 0x0a0c0d0e,
0052     .reg_0848 = 0x02040608,
0053     .reg_084c = 0x0a0c0d0e,
0054     .reg_0868 = 0x02040608,
0055 };
0056
0057 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
0058     {0x00, 0x00030159}, {0x01, 0x00031284},
0059     {0x02, 0x00098000}, {0x03, 0x00039c63},
0060     {0x04, 0x000210e7}, {0x09, 0x0002044f},
0061     {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
0062     {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
0063     {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
0064     {0x19, 0x00000000}, {0x1a, 0x00030355},
0065     {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
0066     {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
0067     {0x1f, 0x00000000}, {0x20, 0x0000b614},
0068     {0x21, 0x0006c000}, {0x22, 0x00000000},
0069     {0x23, 0x00001558}, {0x24, 0x00000060},
0070     {0x25, 0x00000483}, {0x26, 0x0004f000},
0071     {0x27, 0x000ec7d9}, {0x28, 0x00057730},
0072     {0x29, 0x00004783}, {0x2a, 0x00000001},
0073     {0x2b, 0x00021334}, {0x2a, 0x00000000},
0074     {0x2b, 0x00000054}, {0x2a, 0x00000001},
0075     {0x2b, 0x00000808}, {0x2b, 0x00053333},
0076     {0x2c, 0x0000000c}, {0x2a, 0x00000002},
0077     {0x2b, 0x00000808}, {0x2b, 0x0005b333},
0078     {0x2c, 0x0000000d}, {0x2a, 0x00000003},
0079     {0x2b, 0x00000808}, {0x2b, 0x00063333},
0080     {0x2c, 0x0000000d}, {0x2a, 0x00000004},
0081     {0x2b, 0x00000808}, {0x2b, 0x0006b333},
0082     {0x2c, 0x0000000d}, {0x2a, 0x00000005},
0083     {0x2b, 0x00000808}, {0x2b, 0x00073333},
0084     {0x2c, 0x0000000d}, {0x2a, 0x00000006},
0085     {0x2b, 0x00000709}, {0x2b, 0x0005b333},
0086     {0x2c, 0x0000000d}, {0x2a, 0x00000007},
0087     {0x2b, 0x00000709}, {0x2b, 0x00063333},
0088     {0x2c, 0x0000000d}, {0x2a, 0x00000008},
0089     {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
0090     {0x2c, 0x0000000d}, {0x2a, 0x00000009},
0091     {0x2b, 0x0000060a}, {0x2b, 0x00053333},
0092     {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
0093     {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
0094     {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
0095     {0x2b, 0x0000060a}, {0x2b, 0x00063333},
0096     {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
0097     {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
0098     {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
0099     {0x2b, 0x0000060a}, {0x2b, 0x00073333},
0100     {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
0101     {0x2b, 0x0000050b}, {0x2b, 0x00066666},
0102     {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
0103     {0x10, 0x0004000f}, {0x11, 0x000e31fc},
0104     {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
0105     {0x10, 0x0002000f}, {0x11, 0x000203f9},
0106     {0x10, 0x0003000f}, {0x11, 0x000ff500},
0107     {0x10, 0x00000000}, {0x11, 0x00000000},
0108     {0x10, 0x0008000f}, {0x11, 0x0003f100},
0109     {0x10, 0x0009000f}, {0x11, 0x00023100},
0110     {0x12, 0x00032000}, {0x12, 0x00071000},
0111     {0x12, 0x000b0000}, {0x12, 0x000fc000},
0112     {0x13, 0x000287b3}, {0x13, 0x000244b7},
0113     {0x13, 0x000204ab}, {0x13, 0x0001c49f},
0114     {0x13, 0x00018493}, {0x13, 0x0001429b},
0115     {0x13, 0x00010299}, {0x13, 0x0000c29c},
0116     {0x13, 0x000081a0}, {0x13, 0x000040ac},
0117     {0x13, 0x00000020}, {0x14, 0x0001944c},
0118     {0x14, 0x00059444}, {0x14, 0x0009944c},
0119     {0x14, 0x000d9444}, {0x15, 0x0000f474},
0120     {0x15, 0x0004f477}, {0x15, 0x0008f455},
0121     {0x15, 0x000cf455}, {0x16, 0x00000339},
0122     {0x16, 0x00040339}, {0x16, 0x00080339},
0123     {0x16, 0x000c0366}, {0x00, 0x00010159},
0124     {0x18, 0x0000f401}, {0xfe, 0x00000000},
0125     {0xfe, 0x00000000}, {0x1f, 0x00000003},
0126     {0xfe, 0x00000000}, {0xfe, 0x00000000},
0127     {0x1e, 0x00000247}, {0x1f, 0x00000000},
0128     {0x00, 0x00030159},
0129     {0xff, 0xffffffff}
0130 };
0131
0132 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
0133 {
0134     struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
0135
0136     if (efuse->rtl_id != cpu_to_le16(0x8129))
0137         return -EINVAL;
0138
0139     ether_addr_copy(priv->mac_addr, efuse->mac_addr);
0140
0141     memcpy(priv->cck_tx_power_index_A,
0142            efuse->cck_tx_power_index_A,
0143            sizeof(efuse->cck_tx_power_index_A));
0144     memcpy(priv->cck_tx_power_index_B,
0145            efuse->cck_tx_power_index_B,
0146            sizeof(efuse->cck_tx_power_index_B));
0147
0148     memcpy(priv->ht40_1s_tx_power_index_A,
0149            efuse->ht40_1s_tx_power_index_A,
0150            sizeof(efuse->ht40_1s_tx_power_index_A));
0151     memcpy(priv->ht40_1s_tx_power_index_B,
0152            efuse->ht40_1s_tx_power_index_B,
0153            sizeof(efuse->ht40_1s_tx_power_index_B));
0154
0155     memcpy(priv->ht20_tx_power_index_diff,
0156            efuse->ht20_tx_power_index_diff,
0157            sizeof(efuse->ht20_tx_power_index_diff));
0158     memcpy(priv->ofdm_tx_power_index_diff,
0159            efuse->ofdm_tx_power_index_diff,
0160            sizeof(efuse->ofdm_tx_power_index_diff));
0161
0162     memcpy(priv->ht40_max_power_offset,
0163            efuse->ht40_max_power_offset,
0164            sizeof(efuse->ht40_max_power_offset));
0165     memcpy(priv->ht20_max_power_offset,
0166            efuse->ht20_max_power_offset,
0167            sizeof(efuse->ht20_max_power_offset));
0168
0169     if (priv->efuse_wifi.efuse8723.version >= 0x01) {
0170         priv->has_xtalk = 1;
0171         priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
0172     }
0173
0174     priv->power_base = &rtl8723a_power_base;
0175
0176     dev_info(&priv->udev->dev, "Vendor: %.7s\n",
0177          efuse->vendor_name);
0178     dev_info(&priv->udev->dev, "Product: %.41s\n",
0179          efuse->device_name);
0180     return 0;
0181 }
0182
0183 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
0184 {
0185     char *fw_name;
0186     int ret;
0187
0188     switch (priv->chip_cut) {
0189     case 0:
0190         fw_name = "rtlwifi/rtl8723aufw_A.bin";
0191         break;
0192     case 1:
0193         if (priv->enable_bluetooth)
0194             fw_name = "rtlwifi/rtl8723aufw_B.bin";
0195         else
0196             fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
0197
0198         break;
0199     default:
0200         return -EINVAL;
0201     }
0202
0203     ret = rtl8xxxu_load_firmware(priv, fw_name);
0204     return ret;
0205 }
0206
0207 static int rtl8723au_init_phy_rf(struct rtl8xxxu_priv *priv)
0208 {
0209     int ret;
0210
0211     ret = rtl8xxxu_init_phy_rf(priv, rtl8723au_radioa_1t_init_table, RF_A);
0212
0213     /* Reduce 80M spur */
0214     rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
0215     rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
0216     rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
0217     rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
0218
0219     return ret;
0220 }
0221
0222 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
0223 {
0224     u8 val8;
0225     u32 val32;
0226     int count, ret = 0;
0227
0228     /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
0229     val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
0230     val8 |= LDOA15_ENABLE;
0231     rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
0232
0233     /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
0234     val8 = rtl8xxxu_read8(priv, 0x0067);
0235     val8 &= ~BIT(4);
0236     rtl8xxxu_write8(priv, 0x0067, val8);
0237
0238     mdelay(1);
0239
0240     /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
0241     val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
0242     val8 &= ~SYS_ISO_ANALOG_IPS;
0243     rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
0244
0245     /* disable SW LPS 0x04[10]= 0 */
0246     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
0247     val8 &= ~BIT(2);
0248     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
0249
0250     /* wait till 0x04[17] = 1 power ready*/
0251     for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
0252         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
0253         if (val32 & BIT(17))
0254             break;
0255
0256         udelay(10);
0257     }
0258
0259     if (!count) {
0260         ret = -EBUSY;
0261         goto exit;
0262     }
0263
0264     /* We should be able to optimize the following three entries into one */
0265
0266     /* release WLON reset 0x04[16]= 1*/
0267     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
0268     val8 |= BIT(0);
0269     rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
0270
0271     /* disable HWPDN 0x04[15]= 0*/
0272     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
0273     val8 &= ~BIT(7);
0274     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
0275
0276     /* disable WL suspend*/
0277     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
0278     val8 &= ~(BIT(3) | BIT(4));
0279     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
0280
0281     /* set, then poll until 0 */
0282     val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
0283     val32 |= APS_FSMCO_MAC_ENABLE;
0284     rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
0285
0286     for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
0287         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
0288         if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
0289             ret = 0;
0290             break;
0291         }
0292         udelay(10);
0293     }
0294
0295     if (!count) {
0296         ret = -EBUSY;
0297         goto exit;
0298     }
0299
0300     /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
0301     /*
0302      * Note: Vendor driver actually clears this bit, despite the
0303      * documentation claims it's being set!
0304      */
0305     val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
0306     val8 |= LEDCFG2_DPDT_SELECT;
0307     val8 &= ~LEDCFG2_DPDT_SELECT;
0308     rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
0309
0310 exit:
0311     return ret;
0312 }
0313
0314 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
0315 {
0316     u8 val8;
0317     u16 val16;
0318     u32 val32;
0319     int ret;
0320
0321     /*
0322      * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
0323      */
0324     rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
0325
0326     rtl8xxxu_disabled_to_emu(priv);
0327
0328     ret = rtl8723a_emu_to_active(priv);
0329     if (ret)
0330         goto exit;
0331
0332     /*
0333      * 0x0004[19] = 1, reset 8051
0334      */
0335     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
0336     val8 |= BIT(3);
0337     rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
0338
0339     /*
0340      * Enable MAC DMA/WMAC/SCHEDULE/SEC block
0341      * Set CR bit10 to enable 32k calibration.
0342      */
0343     val16 = rtl8xxxu_read16(priv, REG_CR);
0344     val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
0345           CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
0346           CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
0347           CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
0348           CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
0349     rtl8xxxu_write16(priv, REG_CR, val16);
0350
0351     /* For EFuse PG */
0352     val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
0353     val32 &= ~(BIT(28) | BIT(29) | BIT(30));
0354     val32 |= (0x06 << 28);
0355     rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
0356 exit:
0357     return ret;
0358 }
0359
0360 struct rtl8xxxu_fileops rtl8723au_fops = {
0361     .parse_efuse = rtl8723au_parse_efuse,
0362     .load_firmware = rtl8723au_load_firmware,
0363     .power_on = rtl8723au_power_on,
0364     .power_off = rtl8xxxu_power_off,
0365     .reset_8051 = rtl8xxxu_reset_8051,
0366     .llt_init = rtl8xxxu_init_llt_table,
0367     .init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
0368     .init_phy_rf = rtl8723au_init_phy_rf,
0369     .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
0370     .config_channel = rtl8xxxu_gen1_config_channel,
0371     .parse_rx_desc = rtl8xxxu_parse_rxdesc16,
0372     .init_aggregation = rtl8xxxu_gen1_init_aggregation,
0373     .enable_rf = rtl8xxxu_gen1_enable_rf,
0374     .disable_rf = rtl8xxxu_gen1_disable_rf,
0375     .usb_quirks = rtl8xxxu_gen1_usb_quirks,
0376     .set_tx_power = rtl8xxxu_gen1_set_tx_power,
0377     .update_rate_mask = rtl8xxxu_update_rate_mask,
0378     .report_connect = rtl8xxxu_gen1_report_connect,
0379     .fill_txdesc = rtl8xxxu_fill_txdesc_v1,
0380     .writeN_block_size = 1024,
0381     .rx_agg_buf_size = 16000,
0382     .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
0383     .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
0384     .adda_1t_init = 0x0b1b25a0,
0385     .adda_1t_path_on = 0x0bdb25a0,
0386     .adda_2t_path_on_a = 0x04db25a4,
0387     .adda_2t_path_on_b = 0x0b1b25a4,
0388     .trxff_boundary = 0x27ff,
0389     .pbp_rx = PBP_PAGE_SIZE_128,
0390     .pbp_tx = PBP_PAGE_SIZE_128,
0391     .mactable = rtl8xxxu_gen1_mac_init_table,
0392     .total_page_num = TX_TOTAL_PAGE_NUM,
0393     .page_num_hi = TX_PAGE_NUM_HI_PQ,
0394     .page_num_lo = TX_PAGE_NUM_LO_PQ,
0395     .page_num_norm = TX_PAGE_NUM_NORM_PQ,
0396 };