realtek/rtl8xxxu/rtl8xxxu_8192e.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * RTL8XXXU mac80211 USB driver - 8192e specific subdriver
0004  *
0005  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
0006  *
0007  * Portions, notably calibration code:
0008  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
0009  *
0010  * This driver was written as a replacement for the vendor provided
0011  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
0012  * their programming interface, I have started adding support for
0013  * additional 8xxx chips like the 8192cu, 8188cus, etc.
0014  */
0015
0016 #include <linux/init.h>
0017 #include <linux/kernel.h>
0018 #include <linux/sched.h>
0019 #include <linux/errno.h>
0020 #include <linux/slab.h>
0021 #include <linux/module.h>
0022 #include <linux/spinlock.h>
0023 #include <linux/list.h>
0024 #include <linux/usb.h>
0025 #include <linux/netdevice.h>
0026 #include <linux/etherdevice.h>
0027 #include <linux/ethtool.h>
0028 #include <linux/wireless.h>
0029 #include <linux/firmware.h>
0030 #include <linux/moduleparam.h>
0031 #include <net/mac80211.h>
0032 #include "rtl8xxxu.h"
0033 #include "rtl8xxxu_regs.h"
0034
0035 static struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = {
0036     {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
0037     {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
0038     {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
0039     {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
0040     {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
0041     {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
0042     {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
0043     {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
0044     {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
0045     {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
0046     {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},
0047     {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f},
0048     {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e},
0049     {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e},
0050     {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00},
0051     {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a},
0052     {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10},
0053     {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff},
0054     {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff},
0055     {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff},
0056     {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50},
0057     {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e},
0058     {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8},
0059     {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},
0060     {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65},
0061     {0x70b, 0x87},
0062     {0xffff, 0xff},
0063 };
0064
0065 static struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = {
0066     {0x800, 0x80040000}, {0x804, 0x00000003},
0067     {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
0068     {0x810, 0x10001331}, {0x814, 0x020c3d10},
0069     {0x818, 0x02220385}, {0x81c, 0x00000000},
0070     {0x820, 0x01000100}, {0x824, 0x00390204},
0071     {0x828, 0x01000100}, {0x82c, 0x00390204},
0072     {0x830, 0x32323232}, {0x834, 0x30303030},
0073     {0x838, 0x30303030}, {0x83c, 0x30303030},
0074     {0x840, 0x00010000}, {0x844, 0x00010000},
0075     {0x848, 0x28282828}, {0x84c, 0x28282828},
0076     {0x850, 0x00000000}, {0x854, 0x00000000},
0077     {0x858, 0x009a009a}, {0x85c, 0x01000014},
0078     {0x860, 0x66f60000}, {0x864, 0x061f0000},
0079     {0x868, 0x30303030}, {0x86c, 0x30303030},
0080     {0x870, 0x00000000}, {0x874, 0x55004200},
0081     {0x878, 0x08080808}, {0x87c, 0x00000000},
0082     {0x880, 0xb0000c1c}, {0x884, 0x00000001},
0083     {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
0084     {0x890, 0x00000800}, {0x894, 0xfffffffe},
0085     {0x898, 0x40302010}, {0x900, 0x00000000},
0086     {0x904, 0x00000023}, {0x908, 0x00000000},
0087     {0x90c, 0x81121313}, {0x910, 0x806c0001},
0088     {0x914, 0x00000001}, {0x918, 0x00000000},
0089     {0x91c, 0x00010000}, {0x924, 0x00000001},
0090     {0x928, 0x00000000}, {0x92c, 0x00000000},
0091     {0x930, 0x00000000}, {0x934, 0x00000000},
0092     {0x938, 0x00000000}, {0x93c, 0x00000000},
0093     {0x940, 0x00000000}, {0x944, 0x00000000},
0094     {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8},
0095     {0xa04, 0x81ff000c}, {0xa08, 0x8c838300},
0096     {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78},
0097     {0xa14, 0x1114d028}, {0xa18, 0x00881117},
0098     {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000},
0099     {0xa24, 0x090e1317}, {0xa28, 0x00000204},
0100     {0xa2c, 0x00d30000}, {0xa70, 0x101fff00},
0101     {0xa74, 0x00000007}, {0xa78, 0x00000900},
0102     {0xa7c, 0x225b0606}, {0xa80, 0x218075b1},
0103     {0xb38, 0x00000000}, {0xc00, 0x48071d40},
0104     {0xc04, 0x03a05633}, {0xc08, 0x000000e4},
0105     {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
0106     {0xc14, 0x40000100}, {0xc18, 0x08800000},
0107     {0xc1c, 0x40000100}, {0xc20, 0x00000000},
0108     {0xc24, 0x00000000}, {0xc28, 0x00000000},
0109     {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47},
0110     {0xc34, 0x469652af}, {0xc38, 0x49795994},
0111     {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
0112     {0xc44, 0x000100b7}, {0xc48, 0xec020107},
0113     {0xc4c, 0x007f037f},
0114 #ifdef EXT_PA_8192EU
0115     /* External PA or external LNA */
0116     {0xc50, 0x00340220},
0117 #else
0118     {0xc50, 0x00340020},
0119 #endif
0120     {0xc54, 0x0080801f},
0121 #ifdef EXT_PA_8192EU
0122     /* External PA or external LNA */
0123     {0xc58, 0x00000220},
0124 #else
0125     {0xc58, 0x00000020},
0126 #endif
0127     {0xc5c, 0x00248492}, {0xc60, 0x00000000},
0128     {0xc64, 0x7112848b}, {0xc68, 0x47c00bff},
0129     {0xc6c, 0x00000036}, {0xc70, 0x00000600},
0130     {0xc74, 0x02013169}, {0xc78, 0x0000001f},
0131     {0xc7c, 0x00b91612},
0132 #ifdef EXT_PA_8192EU
0133     /* External PA or external LNA */
0134     {0xc80, 0x2d4000b5},
0135 #else
0136     {0xc80, 0x40000100},
0137 #endif
0138     {0xc84, 0x21f60000},
0139 #ifdef EXT_PA_8192EU
0140     /* External PA or external LNA */
0141     {0xc88, 0x2d4000b5},
0142 #else
0143     {0xc88, 0x40000100},
0144 #endif
0145     {0xc8c, 0xa0e40000}, {0xc90, 0x00121820},
0146     {0xc94, 0x00000000}, {0xc98, 0x00121820},
0147     {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
0148     {0xca4, 0x000300a0}, {0xca8, 0x00000000},
0149     {0xcac, 0x00000000}, {0xcb0, 0x00000000},
0150     {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
0151     {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
0152     {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
0153     {0xccc, 0x00000000}, {0xcd0, 0x00000000},
0154     {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
0155     {0xcdc, 0x00766932}, {0xce0, 0x00222222},
0156     {0xce4, 0x00040000}, {0xce8, 0x77644302},
0157     {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
0158     {0xd04, 0x00020403}, {0xd08, 0x0000907f},
0159     {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
0160     {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
0161     {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975},
0162     {0xd30, 0x00000000}, {0xd34, 0x80608000},
0163     {0xd38, 0x00000000}, {0xd3c, 0x00127353},
0164     {0xd40, 0x00000000}, {0xd44, 0x00000000},
0165     {0xd48, 0x00000000}, {0xd4c, 0x00000000},
0166     {0xd50, 0x6437140a}, {0xd54, 0x00000000},
0167     {0xd58, 0x00000282}, {0xd5c, 0x30032064},
0168     {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
0169     {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
0170     {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
0171     {0xd78, 0x000e3c24}, {0xd80, 0x01081008},
0172     {0xd84, 0x00000800}, {0xd88, 0xf0b50000},
0173     {0xe00, 0x30303030}, {0xe04, 0x30303030},
0174     {0xe08, 0x03903030}, {0xe10, 0x30303030},
0175     {0xe14, 0x30303030}, {0xe18, 0x30303030},
0176     {0xe1c, 0x30303030}, {0xe28, 0x00000000},
0177     {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
0178     {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
0179     {0xe40, 0x01007c00}, {0xe44, 0x01004800},
0180     {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
0181     {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
0182     {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
0183     {0xe60, 0x00000008}, {0xe68, 0x0fc05656},
0184     {0xe6c, 0x03c09696}, {0xe70, 0x03c09696},
0185     {0xe74, 0x0c005656}, {0xe78, 0x0c005656},
0186     {0xe7c, 0x0c005656}, {0xe80, 0x0c005656},
0187     {0xe84, 0x03c09696}, {0xe88, 0x0c005656},
0188     {0xe8c, 0x03c09696}, {0xed0, 0x03c09696},
0189     {0xed4, 0x03c09696}, {0xed8, 0x03c09696},
0190     {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6},
0191     {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c},
0192     {0xee8, 0x00000001}, {0xf14, 0x00000003},
0193     {0xf4c, 0x00000000}, {0xf00, 0x00000300},
0194     {0xffff, 0xffffffff},
0195 };
0196
0197 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = {
0198     {0xc78, 0xfb000001}, {0xc78, 0xfb010001},
0199     {0xc78, 0xfb020001}, {0xc78, 0xfb030001},
0200     {0xc78, 0xfb040001}, {0xc78, 0xfb050001},
0201     {0xc78, 0xfa060001}, {0xc78, 0xf9070001},
0202     {0xc78, 0xf8080001}, {0xc78, 0xf7090001},
0203     {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001},
0204     {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001},
0205     {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001},
0206     {0xc78, 0xf0100001}, {0xc78, 0xef110001},
0207     {0xc78, 0xee120001}, {0xc78, 0xed130001},
0208     {0xc78, 0xec140001}, {0xc78, 0xeb150001},
0209     {0xc78, 0xea160001}, {0xc78, 0xe9170001},
0210     {0xc78, 0xe8180001}, {0xc78, 0xe7190001},
0211     {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001},
0212     {0xc78, 0xc61c0001}, {0xc78, 0x071d0001},
0213     {0xc78, 0x061e0001}, {0xc78, 0x051f0001},
0214     {0xc78, 0x04200001}, {0xc78, 0x03210001},
0215     {0xc78, 0xaa220001}, {0xc78, 0xa9230001},
0216     {0xc78, 0xa8240001}, {0xc78, 0xa7250001},
0217     {0xc78, 0xa6260001}, {0xc78, 0x85270001},
0218     {0xc78, 0x84280001}, {0xc78, 0x83290001},
0219     {0xc78, 0x252a0001}, {0xc78, 0x242b0001},
0220     {0xc78, 0x232c0001}, {0xc78, 0x222d0001},
0221     {0xc78, 0x672e0001}, {0xc78, 0x662f0001},
0222     {0xc78, 0x65300001}, {0xc78, 0x64310001},
0223     {0xc78, 0x63320001}, {0xc78, 0x62330001},
0224     {0xc78, 0x61340001}, {0xc78, 0x45350001},
0225     {0xc78, 0x44360001}, {0xc78, 0x43370001},
0226     {0xc78, 0x42380001}, {0xc78, 0x41390001},
0227     {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
0228     {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
0229     {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
0230     {0xc78, 0xfb400001}, {0xc78, 0xfb410001},
0231     {0xc78, 0xfb420001}, {0xc78, 0xfb430001},
0232     {0xc78, 0xfb440001}, {0xc78, 0xfb450001},
0233     {0xc78, 0xfa460001}, {0xc78, 0xf9470001},
0234     {0xc78, 0xf8480001}, {0xc78, 0xf7490001},
0235     {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001},
0236     {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001},
0237     {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001},
0238     {0xc78, 0xf0500001}, {0xc78, 0xef510001},
0239     {0xc78, 0xee520001}, {0xc78, 0xed530001},
0240     {0xc78, 0xec540001}, {0xc78, 0xeb550001},
0241     {0xc78, 0xea560001}, {0xc78, 0xe9570001},
0242     {0xc78, 0xe8580001}, {0xc78, 0xe7590001},
0243     {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001},
0244     {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001},
0245     {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001},
0246     {0xc78, 0x8a600001}, {0xc78, 0x89610001},
0247     {0xc78, 0x88620001}, {0xc78, 0x87630001},
0248     {0xc78, 0x86640001}, {0xc78, 0x85650001},
0249     {0xc78, 0x84660001}, {0xc78, 0x83670001},
0250     {0xc78, 0x82680001}, {0xc78, 0x6b690001},
0251     {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001},
0252     {0xc78, 0x686c0001}, {0xc78, 0x676d0001},
0253     {0xc78, 0x666e0001}, {0xc78, 0x656f0001},
0254     {0xc78, 0x64700001}, {0xc78, 0x63710001},
0255     {0xc78, 0x62720001}, {0xc78, 0x61730001},
0256     {0xc78, 0x49740001}, {0xc78, 0x48750001},
0257     {0xc78, 0x47760001}, {0xc78, 0x46770001},
0258     {0xc78, 0x45780001}, {0xc78, 0x44790001},
0259     {0xc78, 0x437a0001}, {0xc78, 0x427b0001},
0260     {0xc78, 0x417c0001}, {0xc78, 0x407d0001},
0261     {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
0262     {0xc50, 0x00040022}, {0xc50, 0x00040020},
0263     {0xffff, 0xffffffff}
0264 };
0265
0266 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = {
0267     {0xc78, 0xfa000001}, {0xc78, 0xf9010001},
0268     {0xc78, 0xf8020001}, {0xc78, 0xf7030001},
0269     {0xc78, 0xf6040001}, {0xc78, 0xf5050001},
0270     {0xc78, 0xf4060001}, {0xc78, 0xf3070001},
0271     {0xc78, 0xf2080001}, {0xc78, 0xf1090001},
0272     {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001},
0273     {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001},
0274     {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001},
0275     {0xc78, 0xea100001}, {0xc78, 0xe9110001},
0276     {0xc78, 0xe8120001}, {0xc78, 0xe7130001},
0277     {0xc78, 0xe6140001}, {0xc78, 0xe5150001},
0278     {0xc78, 0xe4160001}, {0xc78, 0xe3170001},
0279     {0xc78, 0xe2180001}, {0xc78, 0xe1190001},
0280     {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001},
0281     {0xc78, 0x881c0001}, {0xc78, 0x871d0001},
0282     {0xc78, 0x861e0001}, {0xc78, 0x851f0001},
0283     {0xc78, 0x84200001}, {0xc78, 0x83210001},
0284     {0xc78, 0x82220001}, {0xc78, 0x6a230001},
0285     {0xc78, 0x69240001}, {0xc78, 0x68250001},
0286     {0xc78, 0x67260001}, {0xc78, 0x66270001},
0287     {0xc78, 0x65280001}, {0xc78, 0x64290001},
0288     {0xc78, 0x632a0001}, {0xc78, 0x622b0001},
0289     {0xc78, 0x612c0001}, {0xc78, 0x602d0001},
0290     {0xc78, 0x472e0001}, {0xc78, 0x462f0001},
0291     {0xc78, 0x45300001}, {0xc78, 0x44310001},
0292     {0xc78, 0x43320001}, {0xc78, 0x42330001},
0293     {0xc78, 0x41340001}, {0xc78, 0x40350001},
0294     {0xc78, 0x40360001}, {0xc78, 0x40370001},
0295     {0xc78, 0x40380001}, {0xc78, 0x40390001},
0296     {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
0297     {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
0298     {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
0299     {0xc78, 0xfa400001}, {0xc78, 0xf9410001},
0300     {0xc78, 0xf8420001}, {0xc78, 0xf7430001},
0301     {0xc78, 0xf6440001}, {0xc78, 0xf5450001},
0302     {0xc78, 0xf4460001}, {0xc78, 0xf3470001},
0303     {0xc78, 0xf2480001}, {0xc78, 0xf1490001},
0304     {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001},
0305     {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001},
0306     {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001},
0307     {0xc78, 0xea500001}, {0xc78, 0xe9510001},
0308     {0xc78, 0xe8520001}, {0xc78, 0xe7530001},
0309     {0xc78, 0xe6540001}, {0xc78, 0xe5550001},
0310     {0xc78, 0xe4560001}, {0xc78, 0xe3570001},
0311     {0xc78, 0xe2580001}, {0xc78, 0xe1590001},
0312     {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001},
0313     {0xc78, 0x885c0001}, {0xc78, 0x875d0001},
0314     {0xc78, 0x865e0001}, {0xc78, 0x855f0001},
0315     {0xc78, 0x84600001}, {0xc78, 0x83610001},
0316     {0xc78, 0x82620001}, {0xc78, 0x6a630001},
0317     {0xc78, 0x69640001}, {0xc78, 0x68650001},
0318     {0xc78, 0x67660001}, {0xc78, 0x66670001},
0319     {0xc78, 0x65680001}, {0xc78, 0x64690001},
0320     {0xc78, 0x636a0001}, {0xc78, 0x626b0001},
0321     {0xc78, 0x616c0001}, {0xc78, 0x606d0001},
0322     {0xc78, 0x476e0001}, {0xc78, 0x466f0001},
0323     {0xc78, 0x45700001}, {0xc78, 0x44710001},
0324     {0xc78, 0x43720001}, {0xc78, 0x42730001},
0325     {0xc78, 0x41740001}, {0xc78, 0x40750001},
0326     {0xc78, 0x40760001}, {0xc78, 0x40770001},
0327     {0xc78, 0x40780001}, {0xc78, 0x40790001},
0328     {0xc78, 0x407a0001}, {0xc78, 0x407b0001},
0329     {0xc78, 0x407c0001}, {0xc78, 0x407d0001},
0330     {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
0331     {0xc50, 0x00040222}, {0xc50, 0x00040220},
0332     {0xffff, 0xffffffff}
0333 };
0334
0335 static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = {
0336     {0x7f, 0x00000082}, {0x81, 0x0003fc00},
0337     {0x00, 0x00030000}, {0x08, 0x00008400},
0338     {0x18, 0x00000407}, {0x19, 0x00000012},
0339     {0x1b, 0x00000064}, {0x1e, 0x00080009},
0340     {0x1f, 0x00000880}, {0x2f, 0x0001a060},
0341     {0x3f, 0x00000000}, {0x42, 0x000060c0},
0342     {0x57, 0x000d0000}, {0x58, 0x000be180},
0343     {0x67, 0x00001552}, {0x83, 0x00000000},
0344     {0xb0, 0x000ff9f1}, {0xb1, 0x00055418},
0345     {0xb2, 0x0008cc00}, {0xb4, 0x00043083},
0346     {0xb5, 0x00008166}, {0xb6, 0x0000803e},
0347     {0xb7, 0x0001c69f}, {0xb8, 0x0000407f},
0348     {0xb9, 0x00080001}, {0xba, 0x00040001},
0349     {0xbb, 0x00000400}, {0xbf, 0x000c0000},
0350     {0xc2, 0x00002400}, {0xc3, 0x00000009},
0351     {0xc4, 0x00040c91}, {0xc5, 0x00099999},
0352     {0xc6, 0x000000a3}, {0xc7, 0x00088820},
0353     {0xc8, 0x00076c06}, {0xc9, 0x00000000},
0354     {0xca, 0x00080000}, {0xdf, 0x00000180},
0355     {0xef, 0x000001a0}, {0x51, 0x00069545},
0356     {0x52, 0x0007e45e}, {0x53, 0x00000071},
0357     {0x56, 0x00051ff3}, {0x35, 0x000000a8},
0358     {0x35, 0x000001e2}, {0x35, 0x000002a8},
0359     {0x36, 0x00001c24}, {0x36, 0x00009c24},
0360     {0x36, 0x00011c24}, {0x36, 0x00019c24},
0361     {0x18, 0x00000c07}, {0x5a, 0x00048000},
0362     {0x19, 0x000739d0},
0363 #ifdef EXT_PA_8192EU
0364     /* External PA or external LNA */
0365     {0x34, 0x0000a093}, {0x34, 0x0000908f},
0366     {0x34, 0x0000808c}, {0x34, 0x0000704d},
0367     {0x34, 0x0000604a}, {0x34, 0x00005047},
0368     {0x34, 0x0000400a}, {0x34, 0x00003007},
0369     {0x34, 0x00002004}, {0x34, 0x00001001},
0370     {0x34, 0x00000000},
0371 #else
0372     /* Regular */
0373     {0x34, 0x0000add7}, {0x34, 0x00009dd4},
0374     {0x34, 0x00008dd1}, {0x34, 0x00007dce},
0375     {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
0376     {0x34, 0x00004dc5}, {0x34, 0x000034cc},
0377     {0x34, 0x0000244f}, {0x34, 0x0000144c},
0378     {0x34, 0x00000014},
0379 #endif
0380     {0x00, 0x00030159},
0381     {0x84, 0x00068180},
0382     {0x86, 0x0000014e},
0383     {0x87, 0x00048e00},
0384     {0x8e, 0x00065540},
0385     {0x8f, 0x00088000},
0386     {0xef, 0x000020a0},
0387 #ifdef EXT_PA_8192EU
0388     /* External PA or external LNA */
0389     {0x3b, 0x000f07b0},
0390 #else
0391     {0x3b, 0x000f02b0},
0392 #endif
0393     {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
0394     {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
0395     {0x3b, 0x000a0080}, {0x3b, 0x00090080},
0396     {0x3b, 0x0008f780},
0397 #ifdef EXT_PA_8192EU
0398     /* External PA or external LNA */
0399     {0x3b, 0x000787b0},
0400 #else
0401     {0x3b, 0x00078730},
0402 #endif
0403     {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
0404     {0x3b, 0x00040620}, {0x3b, 0x00037090},
0405     {0x3b, 0x00020080}, {0x3b, 0x0001f060},
0406     {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
0407     {0xfe, 0x00000000}, {0x18, 0x0000fc07},
0408     {0xfe, 0x00000000}, {0xfe, 0x00000000},
0409     {0xfe, 0x00000000}, {0xfe, 0x00000000},
0410     {0x1e, 0x00000001}, {0x1f, 0x00080000},
0411     {0x00, 0x00033e70},
0412     {0xff, 0xffffffff}
0413 };
0414
0415 static struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = {
0416     {0x7f, 0x00000082}, {0x81, 0x0003fc00},
0417     {0x00, 0x00030000}, {0x08, 0x00008400},
0418     {0x18, 0x00000407}, {0x19, 0x00000012},
0419     {0x1b, 0x00000064}, {0x1e, 0x00080009},
0420     {0x1f, 0x00000880}, {0x2f, 0x0001a060},
0421     {0x3f, 0x00000000}, {0x42, 0x000060c0},
0422     {0x57, 0x000d0000}, {0x58, 0x000be180},
0423     {0x67, 0x00001552}, {0x7f, 0x00000082},
0424     {0x81, 0x0003f000}, {0x83, 0x00000000},
0425     {0xdf, 0x00000180}, {0xef, 0x000001a0},
0426     {0x51, 0x00069545}, {0x52, 0x0007e42e},
0427     {0x53, 0x00000071}, {0x56, 0x00051ff3},
0428     {0x35, 0x000000a8}, {0x35, 0x000001e0},
0429     {0x35, 0x000002a8}, {0x36, 0x00001ca8},
0430     {0x36, 0x00009c24}, {0x36, 0x00011c24},
0431     {0x36, 0x00019c24}, {0x18, 0x00000c07},
0432     {0x5a, 0x00048000}, {0x19, 0x000739d0},
0433 #ifdef EXT_PA_8192EU
0434     /* External PA or external LNA */
0435     {0x34, 0x0000a093}, {0x34, 0x0000908f},
0436     {0x34, 0x0000808c}, {0x34, 0x0000704d},
0437     {0x34, 0x0000604a}, {0x34, 0x00005047},
0438     {0x34, 0x0000400a}, {0x34, 0x00003007},
0439     {0x34, 0x00002004}, {0x34, 0x00001001},
0440     {0x34, 0x00000000},
0441 #else
0442     {0x34, 0x0000add7}, {0x34, 0x00009dd4},
0443     {0x34, 0x00008dd1}, {0x34, 0x00007dce},
0444     {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
0445     {0x34, 0x00004dc5}, {0x34, 0x000034cc},
0446     {0x34, 0x0000244f}, {0x34, 0x0000144c},
0447     {0x34, 0x00000014},
0448 #endif
0449     {0x00, 0x00030159}, {0x84, 0x00068180},
0450     {0x86, 0x000000ce}, {0x87, 0x00048a00},
0451     {0x8e, 0x00065540}, {0x8f, 0x00088000},
0452     {0xef, 0x000020a0},
0453 #ifdef EXT_PA_8192EU
0454     /* External PA or external LNA */
0455     {0x3b, 0x000f07b0},
0456 #else
0457     {0x3b, 0x000f02b0},
0458 #endif
0459
0460     {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
0461     {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
0462     {0x3b, 0x000a0080}, {0x3b, 0x00090080},
0463     {0x3b, 0x0008f780},
0464 #ifdef EXT_PA_8192EU
0465     /* External PA or external LNA */
0466     {0x3b, 0x000787b0},
0467 #else
0468     {0x3b, 0x00078730},
0469 #endif
0470     {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
0471     {0x3b, 0x00040620}, {0x3b, 0x00037090},
0472     {0x3b, 0x00020080}, {0x3b, 0x0001f060},
0473     {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
0474     {0x00, 0x00010159}, {0xfe, 0x00000000},
0475     {0xfe, 0x00000000}, {0xfe, 0x00000000},
0476     {0xfe, 0x00000000}, {0x1e, 0x00000001},
0477     {0x1f, 0x00080000}, {0x00, 0x00033e70},
0478     {0xff, 0xffffffff}
0479 };
0480
0481 static void
0482 rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
0483 {
0484     u32 val32, ofdm, mcs;
0485     u8 cck, ofdmbase, mcsbase;
0486     int group, tx_idx;
0487
0488     tx_idx = 0;
0489     group = rtl8xxxu_gen2_channel_to_group(channel);
0490
0491     cck = priv->cck_tx_power_index_A[group];
0492
0493     val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
0494     val32 &= 0xffff00ff;
0495     val32 |= (cck << 8);
0496     rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
0497
0498     val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
0499     val32 &= 0xff;
0500     val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
0501     rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
0502
0503     ofdmbase = priv->ht40_1s_tx_power_index_A[group];
0504     ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a;
0505     ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
0506
0507     rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
0508     rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
0509
0510     mcsbase = priv->ht40_1s_tx_power_index_A[group];
0511     if (ht40)
0512         mcsbase += priv->ht40_tx_power_diff[tx_idx++].a;
0513     else
0514         mcsbase += priv->ht20_tx_power_diff[tx_idx++].a;
0515     mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
0516
0517     rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
0518     rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
0519     rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs);
0520     rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs);
0521
0522     if (priv->tx_paths > 1) {
0523         cck = priv->cck_tx_power_index_B[group];
0524
0525         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
0526         val32 &= 0xff;
0527         val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
0528         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
0529
0530         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
0531         val32 &= 0xffffff00;
0532         val32 |= cck;
0533         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
0534
0535         ofdmbase = priv->ht40_1s_tx_power_index_B[group];
0536         ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
0537         ofdm = ofdmbase | ofdmbase << 8 |
0538             ofdmbase << 16 | ofdmbase << 24;
0539
0540         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm);
0541         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm);
0542
0543         mcsbase = priv->ht40_1s_tx_power_index_B[group];
0544         if (ht40)
0545             mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
0546         else
0547             mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
0548         mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
0549
0550         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs);
0551         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs);
0552         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs);
0553         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs);
0554     }
0555 }
0556
0557 static void rtl8192eu_log_next_device_info(struct rtl8xxxu_priv *priv,
0558                        char *record_name,
0559                        char *device_info,
0560                        unsigned int *record_offset)
0561 {
0562     char *record = device_info + *record_offset;
0563
0564     /* A record is [ total length | 0x03 | value ] */
0565     unsigned char l = record[0];
0566
0567     /*
0568      * The whole device info section seems to be 80 characters, make sure
0569      * we don't read further.
0570      */
0571     if (*record_offset + l > 80) {
0572         dev_warn(&priv->udev->dev,
0573              "invalid record length %d while parsing \"%s\" at offset %u.\n",
0574              l, record_name, *record_offset);
0575         return;
0576     }
0577
0578     if (l >= 2) {
0579         char value[80];
0580
0581         memcpy(value, &record[2], l - 2);
0582         value[l - 2] = '\0';
0583         dev_info(&priv->udev->dev, "%s: %s\n", record_name, value);
0584         *record_offset = *record_offset + l;
0585     } else {
0586         dev_info(&priv->udev->dev, "%s not available.\n", record_name);
0587     }
0588 }
0589
0590 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
0591 {
0592     struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
0593     unsigned int record_offset;
0594     int i;
0595
0596     if (efuse->rtl_id != cpu_to_le16(0x8129))
0597         return -EINVAL;
0598
0599     ether_addr_copy(priv->mac_addr, efuse->mac_addr);
0600
0601     memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
0602            sizeof(efuse->tx_power_index_A.cck_base));
0603     memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
0604            sizeof(efuse->tx_power_index_B.cck_base));
0605
0606     memcpy(priv->ht40_1s_tx_power_index_A,
0607            efuse->tx_power_index_A.ht40_base,
0608            sizeof(efuse->tx_power_index_A.ht40_base));
0609     memcpy(priv->ht40_1s_tx_power_index_B,
0610            efuse->tx_power_index_B.ht40_base,
0611            sizeof(efuse->tx_power_index_B.ht40_base));
0612
0613     priv->ht20_tx_power_diff[0].a =
0614         efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
0615     priv->ht20_tx_power_diff[0].b =
0616         efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
0617
0618     priv->ht40_tx_power_diff[0].a = 0;
0619     priv->ht40_tx_power_diff[0].b = 0;
0620
0621     for (i = 1; i < RTL8723B_TX_COUNT; i++) {
0622         priv->ofdm_tx_power_diff[i].a =
0623             efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
0624         priv->ofdm_tx_power_diff[i].b =
0625             efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
0626
0627         priv->ht20_tx_power_diff[i].a =
0628             efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
0629         priv->ht20_tx_power_diff[i].b =
0630             efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
0631
0632         priv->ht40_tx_power_diff[i].a =
0633             efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
0634         priv->ht40_tx_power_diff[i].b =
0635             efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
0636     }
0637
0638     priv->has_xtalk = 1;
0639     priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
0640
0641     /*
0642      * device_info section seems to be laid out as records
0643      * [ total length | 0x03 | value ] so:
0644      * - vendor length + 2
0645      * - 0x03
0646      * - vendor string (not null terminated)
0647      * - product length + 2
0648      * - 0x03
0649      * - product string (not null terminated)
0650      * Then there is one or 2 0x00 on all the 4 devices I own or found
0651      * dumped online.
0652      * As previous version of the code handled an optional serial
0653      * string, I now assume there may be a third record if the
0654      * length is not 0.
0655      */
0656     record_offset = 0;
0657     rtl8192eu_log_next_device_info(priv, "Vendor", efuse->device_info, &record_offset);
0658     rtl8192eu_log_next_device_info(priv, "Product", efuse->device_info, &record_offset);
0659     rtl8192eu_log_next_device_info(priv, "Serial", efuse->device_info, &record_offset);
0660
0661     if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
0662         unsigned char *raw = priv->efuse_wifi.raw;
0663
0664         dev_info(&priv->udev->dev,
0665              "%s: dumping efuse (0x%02zx bytes):\n",
0666              __func__, sizeof(struct rtl8192eu_efuse));
0667         for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8)
0668             dev_info(&priv->udev->dev, "%02x: %8ph\n", i, &raw[i]);
0669     }
0670     return 0;
0671 }
0672
0673 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
0674 {
0675     char *fw_name;
0676     int ret;
0677
0678     fw_name = "rtlwifi/rtl8192eu_nic.bin";
0679
0680     ret = rtl8xxxu_load_firmware(priv, fw_name);
0681
0682     return ret;
0683 }
0684
0685 static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv)
0686 {
0687     u8 val8;
0688     u16 val16;
0689
0690     val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
0691     val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
0692     rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
0693
0694     /* 6. 0x1f[7:0] = 0x07 */
0695     val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
0696     rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
0697
0698     val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
0699     val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF |
0700           SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB);
0701     rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
0702     val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
0703     rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
0704     rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table);
0705
0706     if (priv->hi_pa)
0707         rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table);
0708     else
0709         rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table);
0710 }
0711
0712 static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv)
0713 {
0714     int ret;
0715
0716     ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A);
0717     if (ret)
0718         goto exit;
0719
0720     ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B);
0721
0722 exit:
0723     return ret;
0724 }
0725
0726 static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv)
0727 {
0728     u32 reg_eac, reg_e94, reg_e9c;
0729     int result = 0;
0730
0731     /*
0732      * TX IQK
0733      * PA/PAD controlled by 0x0
0734      */
0735     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
0736     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180);
0737     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
0738
0739     /* Path A IQK setting */
0740     rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
0741     rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
0742     rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
0743     rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
0744
0745     rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303);
0746     rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000);
0747
0748     /* LO calibration setting */
0749     rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
0750
0751     /* One shot, path A LOK & IQK */
0752     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
0753     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
0754
0755     mdelay(10);
0756
0757     /* Check failed */
0758     reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
0759     reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
0760     reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
0761
0762     if (!(reg_eac & BIT(28)) &&
0763         ((reg_e94 & 0x03ff0000) != 0x01420000) &&
0764         ((reg_e9c & 0x03ff0000) != 0x00420000))
0765         result |= 0x01;
0766
0767     return result;
0768 }
0769
0770 static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
0771 {
0772     u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32;
0773     int result = 0;
0774
0775     /* Leave IQK mode */
0776     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00);
0777
0778     /* Enable path A PA in TX IQK mode */
0779     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
0780     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
0781     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
0782     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b);
0783
0784     /* PA/PAD control by 0x56, and set = 0x0 */
0785     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
0786     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
0787
0788     /* Enter IQK mode */
0789     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
0790
0791     /* TX IQK setting */
0792     rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
0793     rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
0794
0795     /* path-A IQK setting */
0796     rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
0797     rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
0798     rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
0799     rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
0800
0801     rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
0802     rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160c1f);
0803
0804     /* LO calibration setting */
0805     rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
0806
0807     /* One shot, path A LOK & IQK */
0808     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
0809     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
0810
0811     mdelay(10);
0812
0813     /* Check failed */
0814     reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
0815     reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
0816     reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
0817
0818     if (!(reg_eac & BIT(28)) &&
0819         ((reg_e94 & 0x03ff0000) != 0x01420000) &&
0820         ((reg_e9c & 0x03ff0000) != 0x00420000)) {
0821         result |= 0x01;
0822     } else {
0823         /* PA/PAD controlled by 0x0 */
0824         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
0825         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
0826         goto out;
0827     }
0828
0829     val32 = 0x80007c00 |
0830         (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff);
0831     rtl8xxxu_write32(priv, REG_TX_IQK, val32);
0832
0833     /* Modify RX IQK mode table */
0834     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
0835
0836     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
0837     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
0838     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
0839     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa);
0840
0841     /* PA/PAD control by 0x56, and set = 0x0 */
0842     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
0843     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
0844
0845     /* Enter IQK mode */
0846     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
0847
0848     /* IQK setting */
0849     rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
0850
0851     /* Path A IQK setting */
0852     rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
0853     rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
0854     rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
0855     rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
0856
0857     rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
0858     rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);
0859
0860     /* LO calibration setting */
0861     rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
0862
0863     /* One shot, path A LOK & IQK */
0864     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
0865     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
0866
0867     mdelay(10);
0868
0869     reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
0870     reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
0871
0872     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
0873     rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
0874
0875     if (!(reg_eac & BIT(27)) &&
0876         ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
0877         ((reg_eac & 0x03ff0000) != 0x00360000))
0878         result |= 0x02;
0879     else
0880         dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
0881              __func__);
0882
0883 out:
0884     return result;
0885 }
0886
0887 static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv)
0888 {
0889     u32 reg_eac, reg_eb4, reg_ebc;
0890     int result = 0;
0891
0892     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
0893     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180);
0894     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
0895
0896     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
0897     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
0898
0899     /* Path B IQK setting */
0900     rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
0901     rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
0902     rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
0903     rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
0904
0905     rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x821403e2);
0906     rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000);
0907
0908     /* LO calibration setting */
0909     rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00492911);
0910
0911     /* One shot, path A LOK & IQK */
0912     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
0913     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
0914
0915     mdelay(1);
0916
0917     /* Check failed */
0918     reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
0919     reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
0920     reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
0921
0922     if (!(reg_eac & BIT(31)) &&
0923         ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
0924         ((reg_ebc & 0x03ff0000) != 0x00420000))
0925         result |= 0x01;
0926     else
0927         dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n",
0928              __func__);
0929
0930     return result;
0931 }
0932
0933 static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv)
0934 {
0935     u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32;
0936     int result = 0;
0937
0938     /* Leave IQK mode */
0939     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
0940
0941     /* Enable path A PA in TX IQK mode */
0942     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
0943     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
0944     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
0945     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf117b);
0946
0947     /* PA/PAD control by 0x56, and set = 0x0 */
0948     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
0949     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);
0950
0951     /* Enter IQK mode */
0952     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
0953
0954     /* TX IQK setting */
0955     rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
0956     rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
0957
0958     /* path-A IQK setting */
0959     rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
0960     rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
0961     rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
0962     rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
0963
0964     rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160c1f);
0965     rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160c1f);
0966
0967     /* LO calibration setting */
0968     rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
0969
0970     /* One shot, path A LOK & IQK */
0971     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
0972     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
0973
0974     mdelay(10);
0975
0976     /* Check failed */
0977     reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
0978     reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
0979     reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
0980
0981     if (!(reg_eac & BIT(31)) &&
0982         ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
0983         ((reg_ebc & 0x03ff0000) != 0x00420000)) {
0984         result |= 0x01;
0985     } else {
0986         /*
0987          * PA/PAD controlled by 0x0
0988          * Vendor driver restores RF_A here which I believe is a bug
0989          */
0990         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
0991         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
0992         goto out;
0993     }
0994
0995     val32 = 0x80007c00 |
0996         (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff);
0997     rtl8xxxu_write32(priv, REG_TX_IQK, val32);
0998
0999     /* Modify RX IQK mode table */
1000     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1001
1002     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
1003     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
1004     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
1005     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ffa);
1006
1007     /* PA/PAD control by 0x56, and set = 0x0 */
1008     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
1009     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);
1010
1011     /* Enter IQK mode */
1012     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1013
1014     /* IQK setting */
1015     rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1016
1017     /* Path A IQK setting */
1018     rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
1019     rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
1020     rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
1021     rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c);
1022
1023     rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
1024     rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);
1025
1026     /* LO calibration setting */
1027     rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
1028
1029     /* One shot, path A LOK & IQK */
1030     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
1031     rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
1032
1033     mdelay(10);
1034
1035     reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
1036     reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
1037     reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
1038
1039     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1040     rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
1041
1042     if (!(reg_eac & BIT(30)) &&
1043         ((reg_ec4 & 0x03ff0000) != 0x01320000) &&
1044         ((reg_ecc & 0x03ff0000) != 0x00360000))
1045         result |= 0x02;
1046     else
1047         dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
1048              __func__);
1049
1050 out:
1051     return result;
1052 }
1053
1054 static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
1055                       int result[][8], int t)
1056 {
1057     struct device *dev = &priv->udev->dev;
1058     u32 i, val32;
1059     int path_a_ok, path_b_ok;
1060     int retry = 2;
1061     static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
1062         REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
1063         REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
1064         REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
1065         REG_TX_OFDM_BBON, REG_TX_TO_RX,
1066         REG_TX_TO_TX, REG_RX_CCK,
1067         REG_RX_OFDM, REG_RX_WAIT_RIFS,
1068         REG_RX_TO_RX, REG_STANDBY,
1069         REG_SLEEP, REG_PMPD_ANAEN
1070     };
1071     static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
1072         REG_TXPAUSE, REG_BEACON_CTRL,
1073         REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
1074     };
1075     static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
1076         REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
1077         REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
1078         REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
1079         REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING
1080     };
1081     u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
1082     u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
1083
1084     /*
1085      * Note: IQ calibration must be performed after loading
1086      *       PHY_REG.txt , and radio_a, radio_b.txt
1087      */
1088
1089     if (t == 0) {
1090         /* Save ADDA parameters, turn Path A ADDA on */
1091         rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
1092                    RTL8XXXU_ADDA_REGS);
1093         rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1094         rtl8xxxu_save_regs(priv, iqk_bb_regs,
1095                    priv->bb_backup, RTL8XXXU_BB_REGS);
1096     }
1097
1098     rtl8xxxu_path_adda_on(priv, adda_regs, true);
1099
1100     /* MAC settings */
1101     rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
1102
1103     val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
1104     val32 |= 0x0f000000;
1105     rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
1106
1107     rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
1108     rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
1109     rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200);
1110
1111     val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
1112     val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
1113     rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
1114
1115     val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
1116     val32 |= BIT(10);
1117     rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
1118     val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
1119     val32 |= BIT(10);
1120     rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
1121
1122     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1123     rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
1124     rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1125
1126     for (i = 0; i < retry; i++) {
1127         path_a_ok = rtl8192eu_iqk_path_a(priv);
1128         if (path_a_ok == 0x01) {
1129             val32 = rtl8xxxu_read32(priv,
1130                         REG_TX_POWER_BEFORE_IQK_A);
1131             result[t][0] = (val32 >> 16) & 0x3ff;
1132             val32 = rtl8xxxu_read32(priv,
1133                         REG_TX_POWER_AFTER_IQK_A);
1134             result[t][1] = (val32 >> 16) & 0x3ff;
1135
1136             break;
1137         }
1138     }
1139
1140     if (!path_a_ok)
1141         dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
1142
1143     for (i = 0; i < retry; i++) {
1144         path_a_ok = rtl8192eu_rx_iqk_path_a(priv);
1145         if (path_a_ok == 0x03) {
1146             val32 = rtl8xxxu_read32(priv,
1147                         REG_RX_POWER_BEFORE_IQK_A_2);
1148             result[t][2] = (val32 >> 16) & 0x3ff;
1149             val32 = rtl8xxxu_read32(priv,
1150                         REG_RX_POWER_AFTER_IQK_A_2);
1151             result[t][3] = (val32 >> 16) & 0x3ff;
1152
1153             break;
1154         }
1155     }
1156
1157     if (!path_a_ok)
1158         dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
1159
1160     if (priv->rf_paths > 1) {
1161         /* Path A into standby */
1162         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1163         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
1164         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1165
1166         /* Turn Path B ADDA on */
1167         rtl8xxxu_path_adda_on(priv, adda_regs, false);
1168
1169         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1170         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
1171         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1172
1173         for (i = 0; i < retry; i++) {
1174             path_b_ok = rtl8192eu_iqk_path_b(priv);
1175             if (path_b_ok == 0x01) {
1176                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
1177                 result[t][4] = (val32 >> 16) & 0x3ff;
1178                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
1179                 result[t][5] = (val32 >> 16) & 0x3ff;
1180                 break;
1181             }
1182         }
1183
1184         if (!path_b_ok)
1185             dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
1186
1187         for (i = 0; i < retry; i++) {
1188             path_b_ok = rtl8192eu_rx_iqk_path_b(priv);
1189             if (path_b_ok == 0x03) {
1190                 val32 = rtl8xxxu_read32(priv,
1191                             REG_RX_POWER_BEFORE_IQK_B_2);
1192                 result[t][6] = (val32 >> 16) & 0x3ff;
1193                 val32 = rtl8xxxu_read32(priv,
1194                             REG_RX_POWER_AFTER_IQK_B_2);
1195                 result[t][7] = (val32 >> 16) & 0x3ff;
1196                 break;
1197             }
1198         }
1199
1200         if (!path_b_ok)
1201             dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
1202     }
1203
1204     /* Back to BB mode, load original value */
1205     rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1206
1207     if (t) {
1208         /* Reload ADDA power saving parameters */
1209         rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
1210                       RTL8XXXU_ADDA_REGS);
1211
1212         /* Reload MAC parameters */
1213         rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1214
1215         /* Reload BB parameters */
1216         rtl8xxxu_restore_regs(priv, iqk_bb_regs,
1217                       priv->bb_backup, RTL8XXXU_BB_REGS);
1218
1219         /* Restore RX initial gain */
1220         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1221         val32 &= 0xffffff00;
1222         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
1223         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
1224
1225         if (priv->rf_paths > 1) {
1226             val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
1227             val32 &= 0xffffff00;
1228             rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1229                      val32 | 0x50);
1230             rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1231                      val32 | xb_agc);
1232         }
1233
1234         /* Load 0xe30 IQC default value */
1235         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
1236         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
1237     }
1238 }
1239
1240 static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
1241 {
1242     struct device *dev = &priv->udev->dev;
1243     int result[4][8];   /* last is final result */
1244     int i, candidate;
1245     bool path_a_ok, path_b_ok;
1246     u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
1247     u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1248     bool simu;
1249
1250     memset(result, 0, sizeof(result));
1251     candidate = -1;
1252
1253     path_a_ok = false;
1254     path_b_ok = false;
1255
1256     for (i = 0; i < 3; i++) {
1257         rtl8192eu_phy_iqcalibrate(priv, result, i);
1258
1259         if (i == 1) {
1260             simu = rtl8xxxu_gen2_simularity_compare(priv,
1261                                 result, 0, 1);
1262             if (simu) {
1263                 candidate = 0;
1264                 break;
1265             }
1266         }
1267
1268         if (i == 2) {
1269             simu = rtl8xxxu_gen2_simularity_compare(priv,
1270                                 result, 0, 2);
1271             if (simu) {
1272                 candidate = 0;
1273                 break;
1274             }
1275
1276             simu = rtl8xxxu_gen2_simularity_compare(priv,
1277                                 result, 1, 2);
1278             if (simu)
1279                 candidate = 1;
1280             else
1281                 candidate = 3;
1282         }
1283     }
1284
1285     for (i = 0; i < 4; i++) {
1286         reg_e94 = result[i][0];
1287         reg_e9c = result[i][1];
1288         reg_ea4 = result[i][2];
1289         reg_eb4 = result[i][4];
1290         reg_ebc = result[i][5];
1291         reg_ec4 = result[i][6];
1292     }
1293
1294     if (candidate >= 0) {
1295         reg_e94 = result[candidate][0];
1296         priv->rege94 =  reg_e94;
1297         reg_e9c = result[candidate][1];
1298         priv->rege9c = reg_e9c;
1299         reg_ea4 = result[candidate][2];
1300         reg_eac = result[candidate][3];
1301         reg_eb4 = result[candidate][4];
1302         priv->regeb4 = reg_eb4;
1303         reg_ebc = result[candidate][5];
1304         priv->regebc = reg_ebc;
1305         reg_ec4 = result[candidate][6];
1306         reg_ecc = result[candidate][7];
1307         dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
1308         dev_dbg(dev,
1309             "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
1310             __func__, reg_e94, reg_e9c,
1311             reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
1312         path_a_ok = true;
1313         path_b_ok = true;
1314     } else {
1315         reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
1316         reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
1317     }
1318
1319     if (reg_e94 && candidate >= 0)
1320         rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
1321                        candidate, (reg_ea4 == 0));
1322
1323     if (priv->rf_paths > 1)
1324         rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
1325                        candidate, (reg_ec4 == 0));
1326
1327     rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
1328                priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
1329 }
1330
1331 /*
1332  * This is needed for 8723bu as well, presumable
1333  */
1334 static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv)
1335 {
1336     u8 val8;
1337     u32 val32;
1338
1339     /*
1340      * 40Mhz crystal source, MAC 0x28[2]=0
1341      */
1342     val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
1343     val8 &= 0xfb;
1344     rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
1345
1346     val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
1347     val32 &= 0xfffffc7f;
1348     rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
1349
1350     /*
1351      * 92e AFE parameter
1352      * AFE PLL KVCO selection, MAC 0x28[6]=1
1353      */
1354     val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
1355     val8 &= 0xbf;
1356     rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
1357
1358     /*
1359      * AFE PLL KVCO selection, MAC 0x78[21]=0
1360      */
1361     val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
1362     val32 &= 0xffdfffff;
1363     rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
1364 }
1365
1366 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
1367 {
1368     u8 val8;
1369
1370     /* Clear suspend enable and power down enable*/
1371     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1372     val8 &= ~(BIT(3) | BIT(4));
1373     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1374 }
1375
1376 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
1377 {
1378     u8 val8;
1379     u32 val32;
1380     int count, ret = 0;
1381
1382     /* disable HWPDN 0x04[15]=0*/
1383     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1384     val8 &= ~BIT(7);
1385     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1386
1387     /* disable SW LPS 0x04[10]= 0 */
1388     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1389     val8 &= ~BIT(2);
1390     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1391
1392     /* disable WL suspend*/
1393     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1394     val8 &= ~(BIT(3) | BIT(4));
1395     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1396
1397     /* wait till 0x04[17] = 1 power ready*/
1398     for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1399         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1400         if (val32 & BIT(17))
1401             break;
1402
1403         udelay(10);
1404     }
1405
1406     if (!count) {
1407         ret = -EBUSY;
1408         goto exit;
1409     }
1410
1411     /* We should be able to optimize the following three entries into one */
1412
1413     /* release WLON reset 0x04[16]= 1*/
1414     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
1415     val8 |= BIT(0);
1416     rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
1417
1418     /* set, then poll until 0 */
1419     val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1420     val32 |= APS_FSMCO_MAC_ENABLE;
1421     rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1422
1423     for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1424         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1425         if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
1426             ret = 0;
1427             break;
1428         }
1429         udelay(10);
1430     }
1431
1432     if (!count) {
1433         ret = -EBUSY;
1434         goto exit;
1435     }
1436
1437 exit:
1438     return ret;
1439 }
1440
1441 static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv)
1442 {
1443     struct device *dev = &priv->udev->dev;
1444     u8 val8;
1445     u16 val16;
1446     u32 val32;
1447     int retry, retval;
1448
1449     rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1450
1451     retry = 100;
1452     retval = -EBUSY;
1453     /*
1454      * Poll 32 bit wide 0x05f8 for 0x00000000 to ensure no TX is pending.
1455      */
1456     do {
1457         val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);
1458         if (!val32) {
1459             retval = 0;
1460             break;
1461         }
1462     } while (retry--);
1463
1464     if (!retry) {
1465         dev_warn(dev, "Failed to flush TX queue\n");
1466         retval = -EBUSY;
1467         goto out;
1468     }
1469
1470     /* Disable CCK and OFDM, clock gated */
1471     val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1472     val8 &= ~SYS_FUNC_BBRSTB;
1473     rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1474
1475     udelay(2);
1476
1477     /* Reset whole BB */
1478     val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1479     val8 &= ~SYS_FUNC_BB_GLB_RSTN;
1480     rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1481
1482     /* Reset MAC TRX */
1483     val16 = rtl8xxxu_read16(priv, REG_CR);
1484     val16 &= 0xff00;
1485     val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE);
1486     rtl8xxxu_write16(priv, REG_CR, val16);
1487
1488     val16 = rtl8xxxu_read16(priv, REG_CR);
1489     val16 &= ~CR_SECURITY_ENABLE;
1490     rtl8xxxu_write16(priv, REG_CR, val16);
1491
1492     val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
1493     val8 |= DUAL_TSF_TX_OK;
1494     rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
1495
1496 out:
1497     return retval;
1498 }
1499
1500 static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv)
1501 {
1502     u8 val8;
1503     int count, ret = 0;
1504
1505     /* Turn off RF */
1506     val8 = rtl8xxxu_read8(priv, REG_RF_CTRL);
1507     val8 &= ~RF_ENABLE;
1508     rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
1509
1510     /* Switch DPDT_SEL_P output from register 0x65[2] */
1511     val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
1512     val8 &= ~LEDCFG2_DPDT_SELECT;
1513     rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
1514
1515     /* 0x0005[1] = 1 turn off MAC by HW state machine*/
1516     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1517     val8 |= BIT(1);
1518     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1519
1520     for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1521         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1522         if ((val8 & BIT(1)) == 0)
1523             break;
1524         udelay(10);
1525     }
1526
1527     if (!count) {
1528         dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
1529              __func__);
1530         ret = -EBUSY;
1531         goto exit;
1532     }
1533
1534 exit:
1535     return ret;
1536 }
1537
1538 static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv)
1539 {
1540     u8 val8;
1541
1542     /* 0x04[12:11] = 01 enable WL suspend */
1543     val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1544     val8 &= ~(BIT(3) | BIT(4));
1545     val8 |= BIT(3);
1546     rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1547
1548     return 0;
1549 }
1550
1551 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
1552 {
1553     u16 val16;
1554     u32 val32;
1555     int ret;
1556
1557     val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1558     if (val32 & SYS_CFG_SPS_LDO_SEL) {
1559         rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
1560     } else {
1561         /*
1562          * Raise 1.2V voltage
1563          */
1564         val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
1565         val32 &= 0xff0fffff;
1566         val32 |= 0x00500000;
1567         rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
1568         rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
1569     }
1570
1571     /*
1572      * Adjust AFE before enabling PLL
1573      */
1574     rtl8192e_crystal_afe_adjust(priv);
1575     rtl8192e_disabled_to_emu(priv);
1576
1577     ret = rtl8192e_emu_to_active(priv);
1578     if (ret)
1579         goto exit;
1580
1581     rtl8xxxu_write16(priv, REG_CR, 0x0000);
1582
1583     /*
1584      * Enable MAC DMA/WMAC/SCHEDULE/SEC block
1585      * Set CR bit10 to enable 32k calibration.
1586      */
1587     val16 = rtl8xxxu_read16(priv, REG_CR);
1588     val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
1589           CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
1590           CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
1591           CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
1592           CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
1593     rtl8xxxu_write16(priv, REG_CR, val16);
1594
1595 exit:
1596     return ret;
1597 }
1598
1599 static void rtl8192eu_power_off(struct rtl8xxxu_priv *priv)
1600 {
1601     u8 val8;
1602     u16 val16;
1603
1604     rtl8xxxu_flush_fifo(priv);
1605
1606     val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
1607     val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
1608     rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
1609
1610     /* Turn off RF */
1611     rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
1612
1613     rtl8192eu_active_to_lps(priv);
1614
1615     /* Reset Firmware if running in RAM */
1616     if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
1617         rtl8xxxu_firmware_self_reset(priv);
1618
1619     /* Reset MCU */
1620     val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1621     val16 &= ~SYS_FUNC_CPU_ENABLE;
1622     rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1623
1624     /* Reset MCU ready status */
1625     rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
1626
1627     rtl8xxxu_reset_8051(priv);
1628
1629     rtl8192eu_active_to_emu(priv);
1630     rtl8192eu_emu_to_disabled(priv);
1631 }
1632
1633 static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv)
1634 {
1635     u32 val32;
1636     u8 val8;
1637
1638     val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
1639     val32 |= (BIT(22) | BIT(23));
1640     rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
1641
1642     val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
1643     val8 |= BIT(5);
1644     rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
1645
1646     /*
1647      * WLAN action by PTA
1648      */
1649     rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
1650
1651     val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
1652     val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
1653     rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
1654
1655     val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
1656     val32 |= (BIT(0) | BIT(1));
1657     rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
1658
1659     rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
1660
1661     val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
1662     val32 &= ~BIT(24);
1663     val32 |= BIT(23);
1664     rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
1665
1666     /*
1667      * Fix external switch Main->S1, Aux->S0
1668      */
1669     val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1670     val8 &= ~BIT(0);
1671     rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1672 }
1673
1674 struct rtl8xxxu_fileops rtl8192eu_fops = {
1675     .parse_efuse = rtl8192eu_parse_efuse,
1676     .load_firmware = rtl8192eu_load_firmware,
1677     .power_on = rtl8192eu_power_on,
1678     .power_off = rtl8192eu_power_off,
1679     .reset_8051 = rtl8xxxu_reset_8051,
1680     .llt_init = rtl8xxxu_auto_llt_table,
1681     .init_phy_bb = rtl8192eu_init_phy_bb,
1682     .init_phy_rf = rtl8192eu_init_phy_rf,
1683     .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate,
1684     .config_channel = rtl8xxxu_gen2_config_channel,
1685     .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
1686     .enable_rf = rtl8192e_enable_rf,
1687     .disable_rf = rtl8xxxu_gen2_disable_rf,
1688     .usb_quirks = rtl8xxxu_gen2_usb_quirks,
1689     .set_tx_power = rtl8192e_set_tx_power,
1690     .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
1691     .report_connect = rtl8xxxu_gen2_report_connect,
1692     .fill_txdesc = rtl8xxxu_fill_txdesc_v2,
1693     .writeN_block_size = 128,
1694     .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
1695     .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
1696     .has_s0s1 = 0,
1697     .gen2_thermal_meter = 1,
1698     .adda_1t_init = 0x0fc01616,
1699     .adda_1t_path_on = 0x0fc01616,
1700     .adda_2t_path_on_a = 0x0fc01616,
1701     .adda_2t_path_on_b = 0x0fc01616,
1702     .trxff_boundary = 0x3cff,
1703     .mactable = rtl8192e_mac_init_table,
1704     .total_page_num = TX_TOTAL_PAGE_NUM_8192E,
1705     .page_num_hi = TX_PAGE_NUM_HI_PQ_8192E,
1706     .page_num_lo = TX_PAGE_NUM_LO_PQ_8192E,
1707     .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192E,
1708 };