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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003     Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
0004     <http://rt2x00.serialmonkey.com>
0005 
0006  */
0007 
0008 /*
0009     Module: rt73usb
0010     Abstract: Data structures and registers for the rt73usb module.
0011     Supported chipsets: rt2571W & rt2671.
0012  */
0013 
0014 #ifndef RT73USB_H
0015 #define RT73USB_H
0016 
0017 /*
0018  * RF chip defines.
0019  */
0020 #define RF5226              0x0001
0021 #define RF2528              0x0002
0022 #define RF5225              0x0003
0023 #define RF2527              0x0004
0024 
0025 /*
0026  * Signal information.
0027  * Default offset is required for RSSI <-> dBm conversion.
0028  */
0029 #define DEFAULT_RSSI_OFFSET     120
0030 
0031 /*
0032  * Register layout information.
0033  */
0034 #define CSR_REG_BASE            0x3000
0035 #define CSR_REG_SIZE            0x04b0
0036 #define EEPROM_BASE         0x0000
0037 #define EEPROM_SIZE         0x0100
0038 #define BBP_BASE            0x0000
0039 #define BBP_SIZE            0x0080
0040 #define RF_BASE             0x0004
0041 #define RF_SIZE             0x0010
0042 
0043 /*
0044  * Number of TX queues.
0045  */
0046 #define NUM_TX_QUEUES           4
0047 
0048 /*
0049  * USB registers.
0050  */
0051 
0052 /*
0053  * MCU_LEDCS: LED control for MCU Mailbox.
0054  */
0055 #define MCU_LEDCS_LED_MODE      FIELD16(0x001f)
0056 #define MCU_LEDCS_RADIO_STATUS      FIELD16(0x0020)
0057 #define MCU_LEDCS_LINK_BG_STATUS    FIELD16(0x0040)
0058 #define MCU_LEDCS_LINK_A_STATUS     FIELD16(0x0080)
0059 #define MCU_LEDCS_POLARITY_GPIO_0   FIELD16(0x0100)
0060 #define MCU_LEDCS_POLARITY_GPIO_1   FIELD16(0x0200)
0061 #define MCU_LEDCS_POLARITY_GPIO_2   FIELD16(0x0400)
0062 #define MCU_LEDCS_POLARITY_GPIO_3   FIELD16(0x0800)
0063 #define MCU_LEDCS_POLARITY_GPIO_4   FIELD16(0x1000)
0064 #define MCU_LEDCS_POLARITY_ACT      FIELD16(0x2000)
0065 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
0066 #define MCU_LEDCS_POLARITY_READY_A  FIELD16(0x8000)
0067 
0068 /*
0069  * 8051 firmware image.
0070  */
0071 #define FIRMWARE_RT2571         "rt73.bin"
0072 #define FIRMWARE_IMAGE_BASE     0x0800
0073 
0074 /*
0075  * Security key table memory.
0076  * 16 entries 32-byte for shared key table
0077  * 64 entries 32-byte for pairwise key table
0078  * 64 entries 8-byte for pairwise ta key table
0079  */
0080 #define SHARED_KEY_TABLE_BASE       0x1000
0081 #define PAIRWISE_KEY_TABLE_BASE     0x1200
0082 #define PAIRWISE_TA_TABLE_BASE      0x1a00
0083 
0084 #define SHARED_KEY_ENTRY(__idx) \
0085     ( SHARED_KEY_TABLE_BASE + \
0086         ((__idx) * sizeof(struct hw_key_entry)) )
0087 #define PAIRWISE_KEY_ENTRY(__idx) \
0088     ( PAIRWISE_KEY_TABLE_BASE + \
0089         ((__idx) * sizeof(struct hw_key_entry)) )
0090 #define PAIRWISE_TA_ENTRY(__idx) \
0091     ( PAIRWISE_TA_TABLE_BASE + \
0092         ((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
0093 
0094 struct hw_key_entry {
0095     u8 key[16];
0096     u8 tx_mic[8];
0097     u8 rx_mic[8];
0098 } __packed;
0099 
0100 struct hw_pairwise_ta_entry {
0101     u8 address[6];
0102     u8 cipher;
0103     u8 reserved;
0104 } __packed;
0105 
0106 /*
0107  * Since NULL frame won't be that long (256 byte),
0108  * We steal 16 tail bytes to save debugging settings.
0109  */
0110 #define HW_DEBUG_SETTING_BASE       0x2bf0
0111 
0112 /*
0113  * On-chip BEACON frame space.
0114  */
0115 #define HW_BEACON_BASE0         0x2400
0116 #define HW_BEACON_BASE1         0x2500
0117 #define HW_BEACON_BASE2         0x2600
0118 #define HW_BEACON_BASE3         0x2700
0119 
0120 #define HW_BEACON_OFFSET(__index) \
0121     ( HW_BEACON_BASE0 + (__index * 0x0100) )
0122 
0123 /*
0124  * MAC Control/Status Registers(CSR).
0125  * Some values are set in TU, whereas 1 TU == 1024 us.
0126  */
0127 
0128 /*
0129  * MAC_CSR0: ASIC revision number.
0130  */
0131 #define MAC_CSR0            0x3000
0132 #define MAC_CSR0_REVISION       FIELD32(0x0000000f)
0133 #define MAC_CSR0_CHIPSET        FIELD32(0x000ffff0)
0134 
0135 /*
0136  * MAC_CSR1: System control register.
0137  * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
0138  * BBP_RESET: Hardware reset BBP.
0139  * HOST_READY: Host is ready after initialization, 1: ready.
0140  */
0141 #define MAC_CSR1            0x3004
0142 #define MAC_CSR1_SOFT_RESET     FIELD32(0x00000001)
0143 #define MAC_CSR1_BBP_RESET      FIELD32(0x00000002)
0144 #define MAC_CSR1_HOST_READY     FIELD32(0x00000004)
0145 
0146 /*
0147  * MAC_CSR2: STA MAC register 0.
0148  */
0149 #define MAC_CSR2            0x3008
0150 #define MAC_CSR2_BYTE0          FIELD32(0x000000ff)
0151 #define MAC_CSR2_BYTE1          FIELD32(0x0000ff00)
0152 #define MAC_CSR2_BYTE2          FIELD32(0x00ff0000)
0153 #define MAC_CSR2_BYTE3          FIELD32(0xff000000)
0154 
0155 /*
0156  * MAC_CSR3: STA MAC register 1.
0157  * UNICAST_TO_ME_MASK:
0158  *  Used to mask off bits from byte 5 of the MAC address
0159  *  to determine the UNICAST_TO_ME bit for RX frames.
0160  *  The full mask is complemented by BSS_ID_MASK:
0161  *      MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
0162  */
0163 #define MAC_CSR3            0x300c
0164 #define MAC_CSR3_BYTE4          FIELD32(0x000000ff)
0165 #define MAC_CSR3_BYTE5          FIELD32(0x0000ff00)
0166 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
0167 
0168 /*
0169  * MAC_CSR4: BSSID register 0.
0170  */
0171 #define MAC_CSR4            0x3010
0172 #define MAC_CSR4_BYTE0          FIELD32(0x000000ff)
0173 #define MAC_CSR4_BYTE1          FIELD32(0x0000ff00)
0174 #define MAC_CSR4_BYTE2          FIELD32(0x00ff0000)
0175 #define MAC_CSR4_BYTE3          FIELD32(0xff000000)
0176 
0177 /*
0178  * MAC_CSR5: BSSID register 1.
0179  * BSS_ID_MASK:
0180  *  This mask is used to mask off bits 0 and 1 of byte 5 of the
0181  *  BSSID. This will make sure that those bits will be ignored
0182  *  when determining the MY_BSS of RX frames.
0183  *      0: 1-BSSID mode (BSS index = 0)
0184  *      1: 2-BSSID mode (BSS index: Byte5, bit 0)
0185  *      2: 2-BSSID mode (BSS index: byte5, bit 1)
0186  *      3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
0187  */
0188 #define MAC_CSR5            0x3014
0189 #define MAC_CSR5_BYTE4          FIELD32(0x000000ff)
0190 #define MAC_CSR5_BYTE5          FIELD32(0x0000ff00)
0191 #define MAC_CSR5_BSS_ID_MASK        FIELD32(0x00ff0000)
0192 
0193 /*
0194  * MAC_CSR6: Maximum frame length register.
0195  */
0196 #define MAC_CSR6            0x3018
0197 #define MAC_CSR6_MAX_FRAME_UNIT     FIELD32(0x00000fff)
0198 
0199 /*
0200  * MAC_CSR7: Reserved
0201  */
0202 #define MAC_CSR7            0x301c
0203 
0204 /*
0205  * MAC_CSR8: SIFS/EIFS register.
0206  * All units are in US.
0207  */
0208 #define MAC_CSR8            0x3020
0209 #define MAC_CSR8_SIFS           FIELD32(0x000000ff)
0210 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
0211 #define MAC_CSR8_EIFS           FIELD32(0xffff0000)
0212 
0213 /*
0214  * MAC_CSR9: Back-Off control register.
0215  * SLOT_TIME: Slot time, default is 20us for 802.11BG.
0216  * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
0217  * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
0218  * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
0219  */
0220 #define MAC_CSR9            0x3024
0221 #define MAC_CSR9_SLOT_TIME      FIELD32(0x000000ff)
0222 #define MAC_CSR9_CWMIN          FIELD32(0x00000f00)
0223 #define MAC_CSR9_CWMAX          FIELD32(0x0000f000)
0224 #define MAC_CSR9_CW_SELECT      FIELD32(0x00010000)
0225 
0226 /*
0227  * MAC_CSR10: Power state configuration.
0228  */
0229 #define MAC_CSR10           0x3028
0230 
0231 /*
0232  * MAC_CSR11: Power saving transition time register.
0233  * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
0234  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
0235  * WAKEUP_LATENCY: In unit of TU.
0236  */
0237 #define MAC_CSR11           0x302c
0238 #define MAC_CSR11_DELAY_AFTER_TBCN  FIELD32(0x000000ff)
0239 #define MAC_CSR11_TBCN_BEFORE_WAKEUP    FIELD32(0x00007f00)
0240 #define MAC_CSR11_AUTOWAKE      FIELD32(0x00008000)
0241 #define MAC_CSR11_WAKEUP_LATENCY    FIELD32(0x000f0000)
0242 
0243 /*
0244  * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
0245  * CURRENT_STATE: 0:sleep, 1:awake.
0246  * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
0247  * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
0248  */
0249 #define MAC_CSR12           0x3030
0250 #define MAC_CSR12_CURRENT_STATE     FIELD32(0x00000001)
0251 #define MAC_CSR12_PUT_TO_SLEEP      FIELD32(0x00000002)
0252 #define MAC_CSR12_FORCE_WAKEUP      FIELD32(0x00000004)
0253 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
0254 
0255 /*
0256  * MAC_CSR13: GPIO.
0257  *  MAC_CSR13_VALx: GPIO value
0258  *  MAC_CSR13_DIRx: GPIO direction: 0 = input; 1 = output
0259  */
0260 #define MAC_CSR13           0x3034
0261 #define MAC_CSR13_VAL0          FIELD32(0x00000001)
0262 #define MAC_CSR13_VAL1          FIELD32(0x00000002)
0263 #define MAC_CSR13_VAL2          FIELD32(0x00000004)
0264 #define MAC_CSR13_VAL3          FIELD32(0x00000008)
0265 #define MAC_CSR13_VAL4          FIELD32(0x00000010)
0266 #define MAC_CSR13_VAL5          FIELD32(0x00000020)
0267 #define MAC_CSR13_VAL6          FIELD32(0x00000040)
0268 #define MAC_CSR13_VAL7          FIELD32(0x00000080)
0269 #define MAC_CSR13_DIR0          FIELD32(0x00000100)
0270 #define MAC_CSR13_DIR1          FIELD32(0x00000200)
0271 #define MAC_CSR13_DIR2          FIELD32(0x00000400)
0272 #define MAC_CSR13_DIR3          FIELD32(0x00000800)
0273 #define MAC_CSR13_DIR4          FIELD32(0x00001000)
0274 #define MAC_CSR13_DIR5          FIELD32(0x00002000)
0275 #define MAC_CSR13_DIR6          FIELD32(0x00004000)
0276 #define MAC_CSR13_DIR7          FIELD32(0x00008000)
0277 
0278 /*
0279  * MAC_CSR14: LED control register.
0280  * ON_PERIOD: On period, default 70ms.
0281  * OFF_PERIOD: Off period, default 30ms.
0282  * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
0283  * SW_LED: s/w LED, 1: ON, 0: OFF.
0284  * HW_LED_POLARITY: 0: active low, 1: active high.
0285  */
0286 #define MAC_CSR14           0x3038
0287 #define MAC_CSR14_ON_PERIOD     FIELD32(0x000000ff)
0288 #define MAC_CSR14_OFF_PERIOD        FIELD32(0x0000ff00)
0289 #define MAC_CSR14_HW_LED        FIELD32(0x00010000)
0290 #define MAC_CSR14_SW_LED        FIELD32(0x00020000)
0291 #define MAC_CSR14_HW_LED_POLARITY   FIELD32(0x00040000)
0292 #define MAC_CSR14_SW_LED2       FIELD32(0x00080000)
0293 
0294 /*
0295  * MAC_CSR15: NAV control.
0296  */
0297 #define MAC_CSR15           0x303c
0298 
0299 /*
0300  * TXRX control registers.
0301  * Some values are set in TU, whereas 1 TU == 1024 us.
0302  */
0303 
0304 /*
0305  * TXRX_CSR0: TX/RX configuration register.
0306  * TSF_OFFSET: Default is 24.
0307  * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
0308  * DISABLE_RX: Disable Rx engine.
0309  * DROP_CRC: Drop CRC error.
0310  * DROP_PHYSICAL: Drop physical error.
0311  * DROP_CONTROL: Drop control frame.
0312  * DROP_NOT_TO_ME: Drop not to me unicast frame.
0313  * DROP_TO_DS: Drop fram ToDs bit is true.
0314  * DROP_VERSION_ERROR: Drop version error frame.
0315  * DROP_MULTICAST: Drop multicast frames.
0316  * DROP_BORADCAST: Drop broadcast frames.
0317  * DROP_ACK_CTS: Drop received ACK and CTS.
0318  */
0319 #define TXRX_CSR0           0x3040
0320 #define TXRX_CSR0_RX_ACK_TIMEOUT    FIELD32(0x000001ff)
0321 #define TXRX_CSR0_TSF_OFFSET        FIELD32(0x00007e00)
0322 #define TXRX_CSR0_AUTO_TX_SEQ       FIELD32(0x00008000)
0323 #define TXRX_CSR0_DISABLE_RX        FIELD32(0x00010000)
0324 #define TXRX_CSR0_DROP_CRC      FIELD32(0x00020000)
0325 #define TXRX_CSR0_DROP_PHYSICAL     FIELD32(0x00040000)
0326 #define TXRX_CSR0_DROP_CONTROL      FIELD32(0x00080000)
0327 #define TXRX_CSR0_DROP_NOT_TO_ME    FIELD32(0x00100000)
0328 #define TXRX_CSR0_DROP_TO_DS        FIELD32(0x00200000)
0329 #define TXRX_CSR0_DROP_VERSION_ERROR    FIELD32(0x00400000)
0330 #define TXRX_CSR0_DROP_MULTICAST    FIELD32(0x00800000)
0331 #define TXRX_CSR0_DROP_BROADCAST    FIELD32(0x01000000)
0332 #define TXRX_CSR0_DROP_ACK_CTS      FIELD32(0x02000000)
0333 #define TXRX_CSR0_TX_WITHOUT_WAITING    FIELD32(0x04000000)
0334 
0335 /*
0336  * TXRX_CSR1
0337  */
0338 #define TXRX_CSR1           0x3044
0339 #define TXRX_CSR1_BBP_ID0       FIELD32(0x0000007f)
0340 #define TXRX_CSR1_BBP_ID0_VALID     FIELD32(0x00000080)
0341 #define TXRX_CSR1_BBP_ID1       FIELD32(0x00007f00)
0342 #define TXRX_CSR1_BBP_ID1_VALID     FIELD32(0x00008000)
0343 #define TXRX_CSR1_BBP_ID2       FIELD32(0x007f0000)
0344 #define TXRX_CSR1_BBP_ID2_VALID     FIELD32(0x00800000)
0345 #define TXRX_CSR1_BBP_ID3       FIELD32(0x7f000000)
0346 #define TXRX_CSR1_BBP_ID3_VALID     FIELD32(0x80000000)
0347 
0348 /*
0349  * TXRX_CSR2
0350  */
0351 #define TXRX_CSR2           0x3048
0352 #define TXRX_CSR2_BBP_ID0       FIELD32(0x0000007f)
0353 #define TXRX_CSR2_BBP_ID0_VALID     FIELD32(0x00000080)
0354 #define TXRX_CSR2_BBP_ID1       FIELD32(0x00007f00)
0355 #define TXRX_CSR2_BBP_ID1_VALID     FIELD32(0x00008000)
0356 #define TXRX_CSR2_BBP_ID2       FIELD32(0x007f0000)
0357 #define TXRX_CSR2_BBP_ID2_VALID     FIELD32(0x00800000)
0358 #define TXRX_CSR2_BBP_ID3       FIELD32(0x7f000000)
0359 #define TXRX_CSR2_BBP_ID3_VALID     FIELD32(0x80000000)
0360 
0361 /*
0362  * TXRX_CSR3
0363  */
0364 #define TXRX_CSR3           0x304c
0365 #define TXRX_CSR3_BBP_ID0       FIELD32(0x0000007f)
0366 #define TXRX_CSR3_BBP_ID0_VALID     FIELD32(0x00000080)
0367 #define TXRX_CSR3_BBP_ID1       FIELD32(0x00007f00)
0368 #define TXRX_CSR3_BBP_ID1_VALID     FIELD32(0x00008000)
0369 #define TXRX_CSR3_BBP_ID2       FIELD32(0x007f0000)
0370 #define TXRX_CSR3_BBP_ID2_VALID     FIELD32(0x00800000)
0371 #define TXRX_CSR3_BBP_ID3       FIELD32(0x7f000000)
0372 #define TXRX_CSR3_BBP_ID3_VALID     FIELD32(0x80000000)
0373 
0374 /*
0375  * TXRX_CSR4: Auto-Responder/Tx-retry register.
0376  * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
0377  * OFDM_TX_RATE_DOWN: 1:enable.
0378  * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
0379  * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
0380  */
0381 #define TXRX_CSR4           0x3050
0382 #define TXRX_CSR4_TX_ACK_TIMEOUT    FIELD32(0x000000ff)
0383 #define TXRX_CSR4_CNTL_ACK_POLICY   FIELD32(0x00000700)
0384 #define TXRX_CSR4_ACK_CTS_PSM       FIELD32(0x00010000)
0385 #define TXRX_CSR4_AUTORESPOND_ENABLE    FIELD32(0x00020000)
0386 #define TXRX_CSR4_AUTORESPOND_PREAMBLE  FIELD32(0x00040000)
0387 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
0388 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
0389 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK  FIELD32(0x00400000)
0390 #define TXRX_CSR4_LONG_RETRY_LIMIT  FIELD32(0x0f000000)
0391 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
0392 
0393 /*
0394  * TXRX_CSR5
0395  */
0396 #define TXRX_CSR5           0x3054
0397 
0398 /*
0399  * TXRX_CSR6: ACK/CTS payload consumed time
0400  */
0401 #define TXRX_CSR6           0x3058
0402 
0403 /*
0404  * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
0405  */
0406 #define TXRX_CSR7           0x305c
0407 #define TXRX_CSR7_ACK_CTS_6MBS      FIELD32(0x000000ff)
0408 #define TXRX_CSR7_ACK_CTS_9MBS      FIELD32(0x0000ff00)
0409 #define TXRX_CSR7_ACK_CTS_12MBS     FIELD32(0x00ff0000)
0410 #define TXRX_CSR7_ACK_CTS_18MBS     FIELD32(0xff000000)
0411 
0412 /*
0413  * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
0414  */
0415 #define TXRX_CSR8           0x3060
0416 #define TXRX_CSR8_ACK_CTS_24MBS     FIELD32(0x000000ff)
0417 #define TXRX_CSR8_ACK_CTS_36MBS     FIELD32(0x0000ff00)
0418 #define TXRX_CSR8_ACK_CTS_48MBS     FIELD32(0x00ff0000)
0419 #define TXRX_CSR8_ACK_CTS_54MBS     FIELD32(0xff000000)
0420 
0421 /*
0422  * TXRX_CSR9: Synchronization control register.
0423  * BEACON_INTERVAL: In unit of 1/16 TU.
0424  * TSF_TICKING: Enable TSF auto counting.
0425  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
0426  * BEACON_GEN: Enable beacon generator.
0427  */
0428 #define TXRX_CSR9           0x3064
0429 #define TXRX_CSR9_BEACON_INTERVAL   FIELD32(0x0000ffff)
0430 #define TXRX_CSR9_TSF_TICKING       FIELD32(0x00010000)
0431 #define TXRX_CSR9_TSF_SYNC      FIELD32(0x00060000)
0432 #define TXRX_CSR9_TBTT_ENABLE       FIELD32(0x00080000)
0433 #define TXRX_CSR9_BEACON_GEN        FIELD32(0x00100000)
0434 #define TXRX_CSR9_TIMESTAMP_COMPENSATE  FIELD32(0xff000000)
0435 
0436 /*
0437  * TXRX_CSR10: BEACON alignment.
0438  */
0439 #define TXRX_CSR10          0x3068
0440 
0441 /*
0442  * TXRX_CSR11: AES mask.
0443  */
0444 #define TXRX_CSR11          0x306c
0445 
0446 /*
0447  * TXRX_CSR12: TSF low 32.
0448  */
0449 #define TXRX_CSR12          0x3070
0450 #define TXRX_CSR12_LOW_TSFTIMER     FIELD32(0xffffffff)
0451 
0452 /*
0453  * TXRX_CSR13: TSF high 32.
0454  */
0455 #define TXRX_CSR13          0x3074
0456 #define TXRX_CSR13_HIGH_TSFTIMER    FIELD32(0xffffffff)
0457 
0458 /*
0459  * TXRX_CSR14: TBTT timer.
0460  */
0461 #define TXRX_CSR14          0x3078
0462 
0463 /*
0464  * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
0465  */
0466 #define TXRX_CSR15          0x307c
0467 
0468 /*
0469  * PHY control registers.
0470  * Some values are set in TU, whereas 1 TU == 1024 us.
0471  */
0472 
0473 /*
0474  * PHY_CSR0: RF/PS control.
0475  */
0476 #define PHY_CSR0            0x3080
0477 #define PHY_CSR0_PA_PE_BG       FIELD32(0x00010000)
0478 #define PHY_CSR0_PA_PE_A        FIELD32(0x00020000)
0479 
0480 /*
0481  * PHY_CSR1
0482  */
0483 #define PHY_CSR1            0x3084
0484 #define PHY_CSR1_RF_RPI         FIELD32(0x00010000)
0485 
0486 /*
0487  * PHY_CSR2: Pre-TX BBP control.
0488  */
0489 #define PHY_CSR2            0x3088
0490 
0491 /*
0492  * PHY_CSR3: BBP serial control register.
0493  * VALUE: Register value to program into BBP.
0494  * REG_NUM: Selected BBP register.
0495  * READ_CONTROL: 0: Write BBP, 1: Read BBP.
0496  * BUSY: 1: ASIC is busy execute BBP programming.
0497  */
0498 #define PHY_CSR3            0x308c
0499 #define PHY_CSR3_VALUE          FIELD32(0x000000ff)
0500 #define PHY_CSR3_REGNUM         FIELD32(0x00007f00)
0501 #define PHY_CSR3_READ_CONTROL       FIELD32(0x00008000)
0502 #define PHY_CSR3_BUSY           FIELD32(0x00010000)
0503 
0504 /*
0505  * PHY_CSR4: RF serial control register
0506  * VALUE: Register value (include register id) serial out to RF/IF chip.
0507  * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
0508  * IF_SELECT: 1: select IF to program, 0: select RF to program.
0509  * PLL_LD: RF PLL_LD status.
0510  * BUSY: 1: ASIC is busy execute RF programming.
0511  */
0512 #define PHY_CSR4            0x3090
0513 #define PHY_CSR4_VALUE          FIELD32(0x00ffffff)
0514 #define PHY_CSR4_NUMBER_OF_BITS     FIELD32(0x1f000000)
0515 #define PHY_CSR4_IF_SELECT      FIELD32(0x20000000)
0516 #define PHY_CSR4_PLL_LD         FIELD32(0x40000000)
0517 #define PHY_CSR4_BUSY           FIELD32(0x80000000)
0518 
0519 /*
0520  * PHY_CSR5: RX to TX signal switch timing control.
0521  */
0522 #define PHY_CSR5            0x3094
0523 #define PHY_CSR5_IQ_FLIP        FIELD32(0x00000004)
0524 
0525 /*
0526  * PHY_CSR6: TX to RX signal timing control.
0527  */
0528 #define PHY_CSR6            0x3098
0529 #define PHY_CSR6_IQ_FLIP        FIELD32(0x00000004)
0530 
0531 /*
0532  * PHY_CSR7: TX DAC switching timing control.
0533  */
0534 #define PHY_CSR7            0x309c
0535 
0536 /*
0537  * Security control register.
0538  */
0539 
0540 /*
0541  * SEC_CSR0: Shared key table control.
0542  */
0543 #define SEC_CSR0            0x30a0
0544 #define SEC_CSR0_BSS0_KEY0_VALID    FIELD32(0x00000001)
0545 #define SEC_CSR0_BSS0_KEY1_VALID    FIELD32(0x00000002)
0546 #define SEC_CSR0_BSS0_KEY2_VALID    FIELD32(0x00000004)
0547 #define SEC_CSR0_BSS0_KEY3_VALID    FIELD32(0x00000008)
0548 #define SEC_CSR0_BSS1_KEY0_VALID    FIELD32(0x00000010)
0549 #define SEC_CSR0_BSS1_KEY1_VALID    FIELD32(0x00000020)
0550 #define SEC_CSR0_BSS1_KEY2_VALID    FIELD32(0x00000040)
0551 #define SEC_CSR0_BSS1_KEY3_VALID    FIELD32(0x00000080)
0552 #define SEC_CSR0_BSS2_KEY0_VALID    FIELD32(0x00000100)
0553 #define SEC_CSR0_BSS2_KEY1_VALID    FIELD32(0x00000200)
0554 #define SEC_CSR0_BSS2_KEY2_VALID    FIELD32(0x00000400)
0555 #define SEC_CSR0_BSS2_KEY3_VALID    FIELD32(0x00000800)
0556 #define SEC_CSR0_BSS3_KEY0_VALID    FIELD32(0x00001000)
0557 #define SEC_CSR0_BSS3_KEY1_VALID    FIELD32(0x00002000)
0558 #define SEC_CSR0_BSS3_KEY2_VALID    FIELD32(0x00004000)
0559 #define SEC_CSR0_BSS3_KEY3_VALID    FIELD32(0x00008000)
0560 
0561 /*
0562  * SEC_CSR1: Shared key table security mode register.
0563  */
0564 #define SEC_CSR1            0x30a4
0565 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG   FIELD32(0x00000007)
0566 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG   FIELD32(0x00000070)
0567 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG   FIELD32(0x00000700)
0568 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG   FIELD32(0x00007000)
0569 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG   FIELD32(0x00070000)
0570 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG   FIELD32(0x00700000)
0571 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG   FIELD32(0x07000000)
0572 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG   FIELD32(0x70000000)
0573 
0574 /*
0575  * Pairwise key table valid bitmap registers.
0576  * SEC_CSR2: pairwise key table valid bitmap 0.
0577  * SEC_CSR3: pairwise key table valid bitmap 1.
0578  */
0579 #define SEC_CSR2            0x30a8
0580 #define SEC_CSR3            0x30ac
0581 
0582 /*
0583  * SEC_CSR4: Pairwise key table lookup control.
0584  */
0585 #define SEC_CSR4            0x30b0
0586 #define SEC_CSR4_ENABLE_BSS0        FIELD32(0x00000001)
0587 #define SEC_CSR4_ENABLE_BSS1        FIELD32(0x00000002)
0588 #define SEC_CSR4_ENABLE_BSS2        FIELD32(0x00000004)
0589 #define SEC_CSR4_ENABLE_BSS3        FIELD32(0x00000008)
0590 
0591 /*
0592  * SEC_CSR5: shared key table security mode register.
0593  */
0594 #define SEC_CSR5            0x30b4
0595 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG   FIELD32(0x00000007)
0596 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG   FIELD32(0x00000070)
0597 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG   FIELD32(0x00000700)
0598 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG   FIELD32(0x00007000)
0599 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG   FIELD32(0x00070000)
0600 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG   FIELD32(0x00700000)
0601 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG   FIELD32(0x07000000)
0602 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG   FIELD32(0x70000000)
0603 
0604 /*
0605  * STA control registers.
0606  */
0607 
0608 /*
0609  * STA_CSR0: RX PLCP error count & RX FCS error count.
0610  */
0611 #define STA_CSR0            0x30c0
0612 #define STA_CSR0_FCS_ERROR      FIELD32(0x0000ffff)
0613 #define STA_CSR0_PLCP_ERROR     FIELD32(0xffff0000)
0614 
0615 /*
0616  * STA_CSR1: RX False CCA count & RX LONG frame count.
0617  */
0618 #define STA_CSR1            0x30c4
0619 #define STA_CSR1_PHYSICAL_ERROR     FIELD32(0x0000ffff)
0620 #define STA_CSR1_FALSE_CCA_ERROR    FIELD32(0xffff0000)
0621 
0622 /*
0623  * STA_CSR2: TX Beacon count and RX FIFO overflow count.
0624  */
0625 #define STA_CSR2            0x30c8
0626 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
0627 #define STA_CSR2_RX_OVERFLOW_COUNT  FIELD32(0xffff0000)
0628 
0629 /*
0630  * STA_CSR3: TX Beacon count.
0631  */
0632 #define STA_CSR3            0x30cc
0633 #define STA_CSR3_TX_BEACON_COUNT    FIELD32(0x0000ffff)
0634 
0635 /*
0636  * STA_CSR4: TX Retry count.
0637  */
0638 #define STA_CSR4            0x30d0
0639 #define STA_CSR4_TX_NO_RETRY_COUNT  FIELD32(0x0000ffff)
0640 #define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)
0641 
0642 /*
0643  * STA_CSR5: TX Retry count.
0644  */
0645 #define STA_CSR5            0x30d4
0646 #define STA_CSR4_TX_MULTI_RETRY_COUNT   FIELD32(0x0000ffff)
0647 #define STA_CSR4_TX_RETRY_FAIL_COUNT    FIELD32(0xffff0000)
0648 
0649 /*
0650  * QOS control registers.
0651  */
0652 
0653 /*
0654  * QOS_CSR1: TXOP holder MAC address register.
0655  */
0656 #define QOS_CSR1            0x30e4
0657 #define QOS_CSR1_BYTE4          FIELD32(0x000000ff)
0658 #define QOS_CSR1_BYTE5          FIELD32(0x0000ff00)
0659 
0660 /*
0661  * QOS_CSR2: TXOP holder timeout register.
0662  */
0663 #define QOS_CSR2            0x30e8
0664 
0665 /*
0666  * RX QOS-CFPOLL MAC address register.
0667  * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
0668  * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
0669  */
0670 #define QOS_CSR3            0x30ec
0671 #define QOS_CSR4            0x30f0
0672 
0673 /*
0674  * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
0675  */
0676 #define QOS_CSR5            0x30f4
0677 
0678 /*
0679  * WMM Scheduler Register
0680  */
0681 
0682 /*
0683  * AIFSN_CSR: AIFSN for each EDCA AC.
0684  * AIFSN0: For AC_VO.
0685  * AIFSN1: For AC_VI.
0686  * AIFSN2: For AC_BE.
0687  * AIFSN3: For AC_BK.
0688  */
0689 #define AIFSN_CSR           0x0400
0690 #define AIFSN_CSR_AIFSN0        FIELD32(0x0000000f)
0691 #define AIFSN_CSR_AIFSN1        FIELD32(0x000000f0)
0692 #define AIFSN_CSR_AIFSN2        FIELD32(0x00000f00)
0693 #define AIFSN_CSR_AIFSN3        FIELD32(0x0000f000)
0694 
0695 /*
0696  * CWMIN_CSR: CWmin for each EDCA AC.
0697  * CWMIN0: For AC_VO.
0698  * CWMIN1: For AC_VI.
0699  * CWMIN2: For AC_BE.
0700  * CWMIN3: For AC_BK.
0701  */
0702 #define CWMIN_CSR           0x0404
0703 #define CWMIN_CSR_CWMIN0        FIELD32(0x0000000f)
0704 #define CWMIN_CSR_CWMIN1        FIELD32(0x000000f0)
0705 #define CWMIN_CSR_CWMIN2        FIELD32(0x00000f00)
0706 #define CWMIN_CSR_CWMIN3        FIELD32(0x0000f000)
0707 
0708 /*
0709  * CWMAX_CSR: CWmax for each EDCA AC.
0710  * CWMAX0: For AC_VO.
0711  * CWMAX1: For AC_VI.
0712  * CWMAX2: For AC_BE.
0713  * CWMAX3: For AC_BK.
0714  */
0715 #define CWMAX_CSR           0x0408
0716 #define CWMAX_CSR_CWMAX0        FIELD32(0x0000000f)
0717 #define CWMAX_CSR_CWMAX1        FIELD32(0x000000f0)
0718 #define CWMAX_CSR_CWMAX2        FIELD32(0x00000f00)
0719 #define CWMAX_CSR_CWMAX3        FIELD32(0x0000f000)
0720 
0721 /*
0722  * AC_TXOP_CSR0: AC_VO/AC_VI TXOP register.
0723  * AC0_TX_OP: For AC_VO, in unit of 32us.
0724  * AC1_TX_OP: For AC_VI, in unit of 32us.
0725  */
0726 #define AC_TXOP_CSR0            0x040c
0727 #define AC_TXOP_CSR0_AC0_TX_OP      FIELD32(0x0000ffff)
0728 #define AC_TXOP_CSR0_AC1_TX_OP      FIELD32(0xffff0000)
0729 
0730 /*
0731  * AC_TXOP_CSR1: AC_BE/AC_BK TXOP register.
0732  * AC2_TX_OP: For AC_BE, in unit of 32us.
0733  * AC3_TX_OP: For AC_BK, in unit of 32us.
0734  */
0735 #define AC_TXOP_CSR1            0x0410
0736 #define AC_TXOP_CSR1_AC2_TX_OP      FIELD32(0x0000ffff)
0737 #define AC_TXOP_CSR1_AC3_TX_OP      FIELD32(0xffff0000)
0738 
0739 /*
0740  * BBP registers.
0741  * The wordsize of the BBP is 8 bits.
0742  */
0743 
0744 /*
0745  * R2
0746  */
0747 #define BBP_R2_BG_MODE          FIELD8(0x20)
0748 
0749 /*
0750  * R3
0751  */
0752 #define BBP_R3_SMART_MODE       FIELD8(0x01)
0753 
0754 /*
0755  * R4: RX antenna control
0756  * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
0757  */
0758 
0759 /*
0760  * ANTENNA_CONTROL semantics (guessed):
0761  * 0x1: Software controlled antenna switching (fixed or SW diversity)
0762  * 0x2: Hardware diversity.
0763  */
0764 #define BBP_R4_RX_ANTENNA_CONTROL   FIELD8(0x03)
0765 #define BBP_R4_RX_FRAME_END     FIELD8(0x20)
0766 
0767 /*
0768  * R77
0769  */
0770 #define BBP_R77_RX_ANTENNA      FIELD8(0x03)
0771 
0772 /*
0773  * RF registers
0774  */
0775 
0776 /*
0777  * RF 3
0778  */
0779 #define RF3_TXPOWER         FIELD32(0x00003e00)
0780 
0781 /*
0782  * RF 4
0783  */
0784 #define RF4_FREQ_OFFSET         FIELD32(0x0003f000)
0785 
0786 /*
0787  * EEPROM content.
0788  * The wordsize of the EEPROM is 16 bits.
0789  */
0790 
0791 /*
0792  * HW MAC address.
0793  */
0794 #define EEPROM_MAC_ADDR_0       0x0002
0795 #define EEPROM_MAC_ADDR_BYTE0       FIELD16(0x00ff)
0796 #define EEPROM_MAC_ADDR_BYTE1       FIELD16(0xff00)
0797 #define EEPROM_MAC_ADDR1        0x0003
0798 #define EEPROM_MAC_ADDR_BYTE2       FIELD16(0x00ff)
0799 #define EEPROM_MAC_ADDR_BYTE3       FIELD16(0xff00)
0800 #define EEPROM_MAC_ADDR_2       0x0004
0801 #define EEPROM_MAC_ADDR_BYTE4       FIELD16(0x00ff)
0802 #define EEPROM_MAC_ADDR_BYTE5       FIELD16(0xff00)
0803 
0804 /*
0805  * EEPROM antenna.
0806  * ANTENNA_NUM: Number of antennas.
0807  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
0808  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
0809  * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
0810  * DYN_TXAGC: Dynamic TX AGC control.
0811  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
0812  * RF_TYPE: Rf_type of this adapter.
0813  */
0814 #define EEPROM_ANTENNA          0x0010
0815 #define EEPROM_ANTENNA_NUM      FIELD16(0x0003)
0816 #define EEPROM_ANTENNA_TX_DEFAULT   FIELD16(0x000c)
0817 #define EEPROM_ANTENNA_RX_DEFAULT   FIELD16(0x0030)
0818 #define EEPROM_ANTENNA_FRAME_TYPE   FIELD16(0x0040)
0819 #define EEPROM_ANTENNA_DYN_TXAGC    FIELD16(0x0200)
0820 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
0821 #define EEPROM_ANTENNA_RF_TYPE      FIELD16(0xf800)
0822 
0823 /*
0824  * EEPROM NIC config.
0825  * EXTERNAL_LNA: External LNA.
0826  */
0827 #define EEPROM_NIC          0x0011
0828 #define EEPROM_NIC_EXTERNAL_LNA     FIELD16(0x0010)
0829 
0830 /*
0831  * EEPROM geography.
0832  * GEO_A: Default geographical setting for 5GHz band
0833  * GEO: Default geographical setting.
0834  */
0835 #define EEPROM_GEOGRAPHY        0x0012
0836 #define EEPROM_GEOGRAPHY_GEO_A      FIELD16(0x00ff)
0837 #define EEPROM_GEOGRAPHY_GEO        FIELD16(0xff00)
0838 
0839 /*
0840  * EEPROM BBP.
0841  */
0842 #define EEPROM_BBP_START        0x0013
0843 #define EEPROM_BBP_SIZE         16
0844 #define EEPROM_BBP_VALUE        FIELD16(0x00ff)
0845 #define EEPROM_BBP_REG_ID       FIELD16(0xff00)
0846 
0847 /*
0848  * EEPROM TXPOWER 802.11G
0849  */
0850 #define EEPROM_TXPOWER_G_START      0x0023
0851 #define EEPROM_TXPOWER_G_SIZE       7
0852 #define EEPROM_TXPOWER_G_1      FIELD16(0x00ff)
0853 #define EEPROM_TXPOWER_G_2      FIELD16(0xff00)
0854 
0855 /*
0856  * EEPROM Frequency
0857  */
0858 #define EEPROM_FREQ         0x002f
0859 #define EEPROM_FREQ_OFFSET      FIELD16(0x00ff)
0860 #define EEPROM_FREQ_SEQ_MASK        FIELD16(0xff00)
0861 #define EEPROM_FREQ_SEQ         FIELD16(0x0300)
0862 
0863 /*
0864  * EEPROM LED.
0865  * POLARITY_RDY_G: Polarity RDY_G setting.
0866  * POLARITY_RDY_A: Polarity RDY_A setting.
0867  * POLARITY_ACT: Polarity ACT setting.
0868  * POLARITY_GPIO_0: Polarity GPIO0 setting.
0869  * POLARITY_GPIO_1: Polarity GPIO1 setting.
0870  * POLARITY_GPIO_2: Polarity GPIO2 setting.
0871  * POLARITY_GPIO_3: Polarity GPIO3 setting.
0872  * POLARITY_GPIO_4: Polarity GPIO4 setting.
0873  * LED_MODE: Led mode.
0874  */
0875 #define EEPROM_LED          0x0030
0876 #define EEPROM_LED_POLARITY_RDY_G   FIELD16(0x0001)
0877 #define EEPROM_LED_POLARITY_RDY_A   FIELD16(0x0002)
0878 #define EEPROM_LED_POLARITY_ACT     FIELD16(0x0004)
0879 #define EEPROM_LED_POLARITY_GPIO_0  FIELD16(0x0008)
0880 #define EEPROM_LED_POLARITY_GPIO_1  FIELD16(0x0010)
0881 #define EEPROM_LED_POLARITY_GPIO_2  FIELD16(0x0020)
0882 #define EEPROM_LED_POLARITY_GPIO_3  FIELD16(0x0040)
0883 #define EEPROM_LED_POLARITY_GPIO_4  FIELD16(0x0080)
0884 #define EEPROM_LED_LED_MODE     FIELD16(0x1f00)
0885 
0886 /*
0887  * EEPROM TXPOWER 802.11A
0888  */
0889 #define EEPROM_TXPOWER_A_START      0x0031
0890 #define EEPROM_TXPOWER_A_SIZE       12
0891 #define EEPROM_TXPOWER_A_1      FIELD16(0x00ff)
0892 #define EEPROM_TXPOWER_A_2      FIELD16(0xff00)
0893 
0894 /*
0895  * EEPROM RSSI offset 802.11BG
0896  */
0897 #define EEPROM_RSSI_OFFSET_BG       0x004d
0898 #define EEPROM_RSSI_OFFSET_BG_1     FIELD16(0x00ff)
0899 #define EEPROM_RSSI_OFFSET_BG_2     FIELD16(0xff00)
0900 
0901 /*
0902  * EEPROM RSSI offset 802.11A
0903  */
0904 #define EEPROM_RSSI_OFFSET_A        0x004e
0905 #define EEPROM_RSSI_OFFSET_A_1      FIELD16(0x00ff)
0906 #define EEPROM_RSSI_OFFSET_A_2      FIELD16(0xff00)
0907 
0908 /*
0909  * DMA descriptor defines.
0910  */
0911 #define TXD_DESC_SIZE           ( 6 * sizeof(__le32) )
0912 #define TXINFO_SIZE         ( 6 * sizeof(__le32) )
0913 #define RXD_DESC_SIZE           ( 6 * sizeof(__le32) )
0914 
0915 /*
0916  * TX descriptor format for TX, PRIO and Beacon Ring.
0917  */
0918 
0919 /*
0920  * Word0
0921  * BURST: Next frame belongs to same "burst" event.
0922  * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
0923  * KEY_TABLE: Use per-client pairwise KEY table.
0924  * KEY_INDEX:
0925  * Key index (0~31) to the pairwise KEY table.
0926  * 0~3 to shared KEY table 0 (BSS0).
0927  * 4~7 to shared KEY table 1 (BSS1).
0928  * 8~11 to shared KEY table 2 (BSS2).
0929  * 12~15 to shared KEY table 3 (BSS3).
0930  * BURST2: For backward compatibility, set to same value as BURST.
0931  */
0932 #define TXD_W0_BURST            FIELD32(0x00000001)
0933 #define TXD_W0_VALID            FIELD32(0x00000002)
0934 #define TXD_W0_MORE_FRAG        FIELD32(0x00000004)
0935 #define TXD_W0_ACK          FIELD32(0x00000008)
0936 #define TXD_W0_TIMESTAMP        FIELD32(0x00000010)
0937 #define TXD_W0_OFDM         FIELD32(0x00000020)
0938 #define TXD_W0_IFS          FIELD32(0x00000040)
0939 #define TXD_W0_RETRY_MODE       FIELD32(0x00000080)
0940 #define TXD_W0_TKIP_MIC         FIELD32(0x00000100)
0941 #define TXD_W0_KEY_TABLE        FIELD32(0x00000200)
0942 #define TXD_W0_KEY_INDEX        FIELD32(0x0000fc00)
0943 #define TXD_W0_DATABYTE_COUNT       FIELD32(0x0fff0000)
0944 #define TXD_W0_BURST2           FIELD32(0x10000000)
0945 #define TXD_W0_CIPHER_ALG       FIELD32(0xe0000000)
0946 
0947 /*
0948  * Word1
0949  * HOST_Q_ID: EDCA/HCCA queue ID.
0950  * HW_SEQUENCE: MAC overwrites the frame sequence number.
0951  * BUFFER_COUNT: Number of buffers in this TXD.
0952  */
0953 #define TXD_W1_HOST_Q_ID        FIELD32(0x0000000f)
0954 #define TXD_W1_AIFSN            FIELD32(0x000000f0)
0955 #define TXD_W1_CWMIN            FIELD32(0x00000f00)
0956 #define TXD_W1_CWMAX            FIELD32(0x0000f000)
0957 #define TXD_W1_IV_OFFSET        FIELD32(0x003f0000)
0958 #define TXD_W1_HW_SEQUENCE      FIELD32(0x10000000)
0959 #define TXD_W1_BUFFER_COUNT     FIELD32(0xe0000000)
0960 
0961 /*
0962  * Word2: PLCP information
0963  */
0964 #define TXD_W2_PLCP_SIGNAL      FIELD32(0x000000ff)
0965 #define TXD_W2_PLCP_SERVICE     FIELD32(0x0000ff00)
0966 #define TXD_W2_PLCP_LENGTH_LOW      FIELD32(0x00ff0000)
0967 #define TXD_W2_PLCP_LENGTH_HIGH     FIELD32(0xff000000)
0968 
0969 /*
0970  * Word3
0971  */
0972 #define TXD_W3_IV           FIELD32(0xffffffff)
0973 
0974 /*
0975  * Word4
0976  */
0977 #define TXD_W4_EIV          FIELD32(0xffffffff)
0978 
0979 /*
0980  * Word5
0981  * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
0982  * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
0983  * WAITING_DMA_DONE_INT: TXD been filled with data
0984  * and waiting for TxDoneISR housekeeping.
0985  */
0986 #define TXD_W5_FRAME_OFFSET     FIELD32(0x000000ff)
0987 #define TXD_W5_PACKET_ID        FIELD32(0x0000ff00)
0988 #define TXD_W5_TX_POWER         FIELD32(0x00ff0000)
0989 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
0990 
0991 /*
0992  * RX descriptor format for RX Ring.
0993  */
0994 
0995 /*
0996  * Word0
0997  * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
0998  * KEY_INDEX: Decryption key actually used.
0999  */
1000 #define RXD_W0_OWNER_NIC        FIELD32(0x00000001)
1001 #define RXD_W0_DROP         FIELD32(0x00000002)
1002 #define RXD_W0_UNICAST_TO_ME        FIELD32(0x00000004)
1003 #define RXD_W0_MULTICAST        FIELD32(0x00000008)
1004 #define RXD_W0_BROADCAST        FIELD32(0x00000010)
1005 #define RXD_W0_MY_BSS           FIELD32(0x00000020)
1006 #define RXD_W0_CRC_ERROR        FIELD32(0x00000040)
1007 #define RXD_W0_OFDM         FIELD32(0x00000080)
1008 #define RXD_W0_CIPHER_ERROR     FIELD32(0x00000300)
1009 #define RXD_W0_KEY_INDEX        FIELD32(0x0000fc00)
1010 #define RXD_W0_DATABYTE_COUNT       FIELD32(0x0fff0000)
1011 #define RXD_W0_CIPHER_ALG       FIELD32(0xe0000000)
1012 
1013 /*
1014  * WORD1
1015  * SIGNAL: RX raw data rate reported by BBP.
1016  * RSSI: RSSI reported by BBP.
1017  */
1018 #define RXD_W1_SIGNAL           FIELD32(0x000000ff)
1019 #define RXD_W1_RSSI_AGC         FIELD32(0x00001f00)
1020 #define RXD_W1_RSSI_LNA         FIELD32(0x00006000)
1021 #define RXD_W1_FRAME_OFFSET     FIELD32(0x7f000000)
1022 
1023 /*
1024  * Word2
1025  * IV: Received IV of originally encrypted.
1026  */
1027 #define RXD_W2_IV           FIELD32(0xffffffff)
1028 
1029 /*
1030  * Word3
1031  * EIV: Received EIV of originally encrypted.
1032  */
1033 #define RXD_W3_EIV          FIELD32(0xffffffff)
1034 
1035 /*
1036  * Word4
1037  * ICV: Received ICV of originally encrypted.
1038  * NOTE: This is a guess, the official definition is "reserved"
1039  */
1040 #define RXD_W4_ICV          FIELD32(0xffffffff)
1041 
1042 /*
1043  * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1044  * and passed to the HOST driver.
1045  * The following fields are for DMA block and HOST usage only.
1046  * Can't be touched by ASIC MAC block.
1047  */
1048 
1049 /*
1050  * Word5
1051  */
1052 #define RXD_W5_RESERVED         FIELD32(0xffffffff)
1053 
1054 /*
1055  * Macros for converting txpower from EEPROM to mac80211 value
1056  * and from mac80211 value to register value.
1057  */
1058 #define MIN_TXPOWER 0
1059 #define MAX_TXPOWER 31
1060 #define DEFAULT_TXPOWER 24
1061 
1062 #define TXPOWER_FROM_DEV(__txpower) \
1063     (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1064 
1065 #define TXPOWER_TO_DEV(__txpower) \
1066     clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1067 
1068 #endif /* RT73USB_H */
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