ralink/rt2x00/rt2800mmio.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*  Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
0003  *  Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
0004  *  Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
0005  *  Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
0006  *  Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
0007  *  Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
0008  *  Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
0009  *  Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
0010  *  <http://rt2x00.serialmonkey.com>
0011  */
0012
0013 /*  Module: rt2800mmio
0014  *  Abstract: forward declarations for the rt2800mmio module.
0015  */
0016
0017 #ifndef RT2800MMIO_H
0018 #define RT2800MMIO_H
0019
0020 /*
0021  * Queue register offset macros
0022  */
0023 #define TX_QUEUE_REG_OFFSET 0x10
0024 #define TX_BASE_PTR(__x)    (TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET))
0025 #define TX_MAX_CNT(__x)     (TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET))
0026 #define TX_CTX_IDX(__x)     (TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET))
0027 #define TX_DTX_IDX(__x)     (TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET))
0028
0029 /*
0030  * DMA descriptor defines.
0031  */
0032 #define TXD_DESC_SIZE           (4 * sizeof(__le32))
0033 #define RXD_DESC_SIZE           (4 * sizeof(__le32))
0034
0035 /*
0036  * TX descriptor format for TX, PRIO and Beacon Ring.
0037  */
0038
0039 /*
0040  * Word0
0041  */
0042 #define TXD_W0_SD_PTR0          FIELD32(0xffffffff)
0043
0044 /*
0045  * Word1
0046  */
0047 #define TXD_W1_SD_LEN1          FIELD32(0x00003fff)
0048 #define TXD_W1_LAST_SEC1        FIELD32(0x00004000)
0049 #define TXD_W1_BURST            FIELD32(0x00008000)
0050 #define TXD_W1_SD_LEN0          FIELD32(0x3fff0000)
0051 #define TXD_W1_LAST_SEC0        FIELD32(0x40000000)
0052 #define TXD_W1_DMA_DONE         FIELD32(0x80000000)
0053
0054 /*
0055  * Word2
0056  */
0057 #define TXD_W2_SD_PTR1          FIELD32(0xffffffff)
0058
0059 /*
0060  * Word3
0061  * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
0062  * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
0063  *       0:MGMT, 1:HCCA 2:EDCA
0064  */
0065 #define TXD_W3_WIV          FIELD32(0x01000000)
0066 #define TXD_W3_QSEL         FIELD32(0x06000000)
0067 #define TXD_W3_TCO          FIELD32(0x20000000)
0068 #define TXD_W3_UCO          FIELD32(0x40000000)
0069 #define TXD_W3_ICO          FIELD32(0x80000000)
0070
0071 /*
0072  * RX descriptor format for RX Ring.
0073  */
0074
0075 /*
0076  * Word0
0077  */
0078 #define RXD_W0_SDP0         FIELD32(0xffffffff)
0079
0080 /*
0081  * Word1
0082  */
0083 #define RXD_W1_SDL1         FIELD32(0x00003fff)
0084 #define RXD_W1_SDL0         FIELD32(0x3fff0000)
0085 #define RXD_W1_LS0          FIELD32(0x40000000)
0086 #define RXD_W1_DMA_DONE         FIELD32(0x80000000)
0087
0088 /*
0089  * Word2
0090  */
0091 #define RXD_W2_SDP1         FIELD32(0xffffffff)
0092
0093 /*
0094  * Word3
0095  * AMSDU: RX with 802.3 header, not 802.11 header.
0096  * DECRYPTED: This frame is being decrypted.
0097  */
0098 #define RXD_W3_BA           FIELD32(0x00000001)
0099 #define RXD_W3_DATA         FIELD32(0x00000002)
0100 #define RXD_W3_NULLDATA         FIELD32(0x00000004)
0101 #define RXD_W3_FRAG         FIELD32(0x00000008)
0102 #define RXD_W3_UNICAST_TO_ME        FIELD32(0x00000010)
0103 #define RXD_W3_MULTICAST        FIELD32(0x00000020)
0104 #define RXD_W3_BROADCAST        FIELD32(0x00000040)
0105 #define RXD_W3_MY_BSS           FIELD32(0x00000080)
0106 #define RXD_W3_CRC_ERROR        FIELD32(0x00000100)
0107 #define RXD_W3_CIPHER_ERROR     FIELD32(0x00000600)
0108 #define RXD_W3_AMSDU            FIELD32(0x00000800)
0109 #define RXD_W3_HTC          FIELD32(0x00001000)
0110 #define RXD_W3_RSSI         FIELD32(0x00002000)
0111 #define RXD_W3_L2PAD            FIELD32(0x00004000)
0112 #define RXD_W3_AMPDU            FIELD32(0x00008000)
0113 #define RXD_W3_DECRYPTED        FIELD32(0x00010000)
0114 #define RXD_W3_PLCP_SIGNAL      FIELD32(0x00020000)
0115 #define RXD_W3_PLCP_RSSI        FIELD32(0x00040000)
0116
0117 unsigned int rt2800mmio_get_dma_done(struct data_queue *queue);
0118
0119 /* TX descriptor initialization */
0120 __le32 *rt2800mmio_get_txwi(struct queue_entry *entry);
0121 void rt2800mmio_write_tx_desc(struct queue_entry *entry,
0122                   struct txentry_desc *txdesc);
0123
0124 /* RX control handlers */
0125 void rt2800mmio_fill_rxdone(struct queue_entry *entry,
0126                 struct rxdone_entry_desc *rxdesc);
0127
0128 /* Interrupt functions */
0129 void rt2800mmio_txstatus_tasklet(struct tasklet_struct *t);
0130 void rt2800mmio_pretbtt_tasklet(struct tasklet_struct *t);
0131 void rt2800mmio_tbtt_tasklet(struct tasklet_struct *t);
0132 void rt2800mmio_rxdone_tasklet(struct tasklet_struct *t);
0133 void rt2800mmio_autowake_tasklet(struct tasklet_struct *t);
0134 irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance);
0135 void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev,
0136                enum dev_state state);
0137
0138 /* Queue handlers */
0139 void rt2800mmio_start_queue(struct data_queue *queue);
0140 void rt2800mmio_kick_queue(struct data_queue *queue);
0141 void rt2800mmio_flush_queue(struct data_queue *queue, bool drop);
0142 void rt2800mmio_stop_queue(struct data_queue *queue);
0143 void rt2800mmio_queue_init(struct data_queue *queue);
0144
0145 /* Initialization functions */
0146 int rt2800mmio_probe_hw(struct rt2x00_dev *rt2x00dev);
0147 bool rt2800mmio_get_entry_state(struct queue_entry *entry);
0148 void rt2800mmio_clear_entry(struct queue_entry *entry);
0149 int rt2800mmio_init_queues(struct rt2x00_dev *rt2x00dev);
0150 int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev);
0151
0152 /* Device state switch handlers. */
0153 int rt2800mmio_enable_radio(struct rt2x00_dev *rt2x00dev);
0154
0155 #endif /* RT2800MMIO_H */