ralink/rt2x00/rt2500usb.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003     Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
0004     <http://rt2x00.serialmonkey.com>
0005
0006  */
0007
0008 /*
0009     Module: rt2500usb
0010     Abstract: Data structures and registers for the rt2500usb module.
0011     Supported chipsets: RT2570.
0012  */
0013
0014 #ifndef RT2500USB_H
0015 #define RT2500USB_H
0016
0017 /*
0018  * RF chip defines.
0019  */
0020 #define RF2522              0x0000
0021 #define RF2523              0x0001
0022 #define RF2524              0x0002
0023 #define RF2525              0x0003
0024 #define RF2525E             0x0005
0025 #define RF5222              0x0010
0026
0027 /*
0028  * RT2570 version
0029  */
0030 #define RT2570_VERSION_B        2
0031 #define RT2570_VERSION_C        3
0032 #define RT2570_VERSION_D        4
0033
0034 /*
0035  * Signal information.
0036  * Default offset is required for RSSI <-> dBm conversion.
0037  */
0038 #define DEFAULT_RSSI_OFFSET     120
0039
0040 /*
0041  * Register layout information.
0042  */
0043 #define CSR_REG_BASE            0x0400
0044 #define CSR_REG_SIZE            0x0100
0045 #define EEPROM_BASE         0x0000
0046 #define EEPROM_SIZE         0x006e
0047 #define BBP_BASE            0x0000
0048 #define BBP_SIZE            0x0060
0049 #define RF_BASE             0x0004
0050 #define RF_SIZE             0x0010
0051
0052 /*
0053  * Number of TX queues.
0054  */
0055 #define NUM_TX_QUEUES           2
0056
0057 /*
0058  * Control/Status Registers(CSR).
0059  * Some values are set in TU, whereas 1 TU == 1024 us.
0060  */
0061
0062 /*
0063  * MAC_CSR0: ASIC revision number.
0064  */
0065 #define MAC_CSR0            0x0400
0066
0067 /*
0068  * MAC_CSR1: System control.
0069  * SOFT_RESET: Software reset, 1: reset, 0: normal.
0070  * BBP_RESET: Hardware reset, 1: reset, 0, release.
0071  * HOST_READY: Host ready after initialization.
0072  */
0073 #define MAC_CSR1            0x0402
0074 #define MAC_CSR1_SOFT_RESET     FIELD16(0x00000001)
0075 #define MAC_CSR1_BBP_RESET      FIELD16(0x00000002)
0076 #define MAC_CSR1_HOST_READY     FIELD16(0x00000004)
0077
0078 /*
0079  * MAC_CSR2: STA MAC register 0.
0080  */
0081 #define MAC_CSR2            0x0404
0082 #define MAC_CSR2_BYTE0          FIELD16(0x00ff)
0083 #define MAC_CSR2_BYTE1          FIELD16(0xff00)
0084
0085 /*
0086  * MAC_CSR3: STA MAC register 1.
0087  */
0088 #define MAC_CSR3            0x0406
0089 #define MAC_CSR3_BYTE2          FIELD16(0x00ff)
0090 #define MAC_CSR3_BYTE3          FIELD16(0xff00)
0091
0092 /*
0093  * MAC_CSR4: STA MAC register 2.
0094  */
0095 #define MAC_CSR4            0X0408
0096 #define MAC_CSR4_BYTE4          FIELD16(0x00ff)
0097 #define MAC_CSR4_BYTE5          FIELD16(0xff00)
0098
0099 /*
0100  * MAC_CSR5: BSSID register 0.
0101  */
0102 #define MAC_CSR5            0x040a
0103 #define MAC_CSR5_BYTE0          FIELD16(0x00ff)
0104 #define MAC_CSR5_BYTE1          FIELD16(0xff00)
0105
0106 /*
0107  * MAC_CSR6: BSSID register 1.
0108  */
0109 #define MAC_CSR6            0x040c
0110 #define MAC_CSR6_BYTE2          FIELD16(0x00ff)
0111 #define MAC_CSR6_BYTE3          FIELD16(0xff00)
0112
0113 /*
0114  * MAC_CSR7: BSSID register 2.
0115  */
0116 #define MAC_CSR7            0x040e
0117 #define MAC_CSR7_BYTE4          FIELD16(0x00ff)
0118 #define MAC_CSR7_BYTE5          FIELD16(0xff00)
0119
0120 /*
0121  * MAC_CSR8: Max frame length.
0122  */
0123 #define MAC_CSR8            0x0410
0124 #define MAC_CSR8_MAX_FRAME_UNIT     FIELD16(0x0fff)
0125
0126 /*
0127  * Misc MAC_CSR registers.
0128  * MAC_CSR9: Timer control.
0129  * MAC_CSR10: Slot time.
0130  * MAC_CSR11: SIFS.
0131  * MAC_CSR12: EIFS.
0132  * MAC_CSR13: Power mode0.
0133  * MAC_CSR14: Power mode1.
0134  * MAC_CSR15: Power saving transition0
0135  * MAC_CSR16: Power saving transition1
0136  */
0137 #define MAC_CSR9            0x0412
0138 #define MAC_CSR10           0x0414
0139 #define MAC_CSR11           0x0416
0140 #define MAC_CSR12           0x0418
0141 #define MAC_CSR13           0x041a
0142 #define MAC_CSR14           0x041c
0143 #define MAC_CSR15           0x041e
0144 #define MAC_CSR16           0x0420
0145
0146 /*
0147  * MAC_CSR17: Manual power control / status register.
0148  * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
0149  * SET_STATE: Set state. Write 1 to trigger, self cleared.
0150  * BBP_DESIRE_STATE: BBP desired state.
0151  * RF_DESIRE_STATE: RF desired state.
0152  * BBP_CURRENT_STATE: BBP current state.
0153  * RF_CURRENT_STATE: RF current state.
0154  * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
0155  */
0156 #define MAC_CSR17           0x0422
0157 #define MAC_CSR17_SET_STATE     FIELD16(0x0001)
0158 #define MAC_CSR17_BBP_DESIRE_STATE  FIELD16(0x0006)
0159 #define MAC_CSR17_RF_DESIRE_STATE   FIELD16(0x0018)
0160 #define MAC_CSR17_BBP_CURR_STATE    FIELD16(0x0060)
0161 #define MAC_CSR17_RF_CURR_STATE     FIELD16(0x0180)
0162 #define MAC_CSR17_PUT_TO_SLEEP      FIELD16(0x0200)
0163
0164 /*
0165  * MAC_CSR18: Wakeup timer register.
0166  * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
0167  * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
0168  * AUTO_WAKE: Enable auto wakeup / sleep mechanism.
0169  */
0170 #define MAC_CSR18           0x0424
0171 #define MAC_CSR18_DELAY_AFTER_BEACON    FIELD16(0x00ff)
0172 #define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00)
0173 #define MAC_CSR18_AUTO_WAKE     FIELD16(0x8000)
0174
0175 /*
0176  * MAC_CSR19: GPIO control register.
0177  *  MAC_CSR19_VALx: GPIO value
0178  *  MAC_CSR19_DIRx: GPIO direction: 0 = input; 1 = output
0179  */
0180 #define MAC_CSR19           0x0426
0181 #define MAC_CSR19_VAL0          FIELD16(0x0001)
0182 #define MAC_CSR19_VAL1          FIELD16(0x0002)
0183 #define MAC_CSR19_VAL2          FIELD16(0x0004)
0184 #define MAC_CSR19_VAL3          FIELD16(0x0008)
0185 #define MAC_CSR19_VAL4          FIELD16(0x0010)
0186 #define MAC_CSR19_VAL5          FIELD16(0x0020)
0187 #define MAC_CSR19_VAL6          FIELD16(0x0040)
0188 #define MAC_CSR19_VAL7          FIELD16(0x0080)
0189 #define MAC_CSR19_DIR0          FIELD16(0x0100)
0190 #define MAC_CSR19_DIR1          FIELD16(0x0200)
0191 #define MAC_CSR19_DIR2          FIELD16(0x0400)
0192 #define MAC_CSR19_DIR3          FIELD16(0x0800)
0193 #define MAC_CSR19_DIR4          FIELD16(0x1000)
0194 #define MAC_CSR19_DIR5          FIELD16(0x2000)
0195 #define MAC_CSR19_DIR6          FIELD16(0x4000)
0196 #define MAC_CSR19_DIR7          FIELD16(0x8000)
0197
0198 /*
0199  * MAC_CSR20: LED control register.
0200  * ACTIVITY: 0: idle, 1: active.
0201  * LINK: 0: linkoff, 1: linkup.
0202  * ACTIVITY_POLARITY: 0: active low, 1: active high.
0203  */
0204 #define MAC_CSR20           0x0428
0205 #define MAC_CSR20_ACTIVITY      FIELD16(0x0001)
0206 #define MAC_CSR20_LINK          FIELD16(0x0002)
0207 #define MAC_CSR20_ACTIVITY_POLARITY FIELD16(0x0004)
0208
0209 /*
0210  * MAC_CSR21: LED control register.
0211  * ON_PERIOD: On period, default 70ms.
0212  * OFF_PERIOD: Off period, default 30ms.
0213  */
0214 #define MAC_CSR21           0x042a
0215 #define MAC_CSR21_ON_PERIOD     FIELD16(0x00ff)
0216 #define MAC_CSR21_OFF_PERIOD        FIELD16(0xff00)
0217
0218 /*
0219  * MAC_CSR22: Collision window control register.
0220  */
0221 #define MAC_CSR22           0x042c
0222
0223 /*
0224  * Transmit related CSRs.
0225  * Some values are set in TU, whereas 1 TU == 1024 us.
0226  */
0227
0228 /*
0229  * TXRX_CSR0: Security control register.
0230  */
0231 #define TXRX_CSR0           0x0440
0232 #define TXRX_CSR0_ALGORITHM     FIELD16(0x0007)
0233 #define TXRX_CSR0_IV_OFFSET     FIELD16(0x01f8)
0234 #define TXRX_CSR0_KEY_ID        FIELD16(0x1e00)
0235
0236 /*
0237  * TXRX_CSR1: TX configuration.
0238  * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
0239  * TSF_OFFSET: TSF offset in MAC header.
0240  * AUTO_SEQUENCE: Let ASIC control frame sequence number.
0241  */
0242 #define TXRX_CSR1           0x0442
0243 #define TXRX_CSR1_ACK_TIMEOUT       FIELD16(0x00ff)
0244 #define TXRX_CSR1_TSF_OFFSET        FIELD16(0x7f00)
0245 #define TXRX_CSR1_AUTO_SEQUENCE     FIELD16(0x8000)
0246
0247 /*
0248  * TXRX_CSR2: RX control.
0249  * DISABLE_RX: Disable rx engine.
0250  * DROP_CRC: Drop crc error.
0251  * DROP_PHYSICAL: Drop physical error.
0252  * DROP_CONTROL: Drop control frame.
0253  * DROP_NOT_TO_ME: Drop not to me unicast frame.
0254  * DROP_TODS: Drop frame tods bit is true.
0255  * DROP_VERSION_ERROR: Drop version error frame.
0256  * DROP_MCAST: Drop multicast frames.
0257  * DROP_BCAST: Drop broadcast frames.
0258  */
0259 #define TXRX_CSR2           0x0444
0260 #define TXRX_CSR2_DISABLE_RX        FIELD16(0x0001)
0261 #define TXRX_CSR2_DROP_CRC      FIELD16(0x0002)
0262 #define TXRX_CSR2_DROP_PHYSICAL     FIELD16(0x0004)
0263 #define TXRX_CSR2_DROP_CONTROL      FIELD16(0x0008)
0264 #define TXRX_CSR2_DROP_NOT_TO_ME    FIELD16(0x0010)
0265 #define TXRX_CSR2_DROP_TODS     FIELD16(0x0020)
0266 #define TXRX_CSR2_DROP_VERSION_ERROR    FIELD16(0x0040)
0267 #define TXRX_CSR2_DROP_MULTICAST    FIELD16(0x0200)
0268 #define TXRX_CSR2_DROP_BROADCAST    FIELD16(0x0400)
0269
0270 /*
0271  * RX BBP ID registers
0272  * TXRX_CSR3: CCK RX BBP ID.
0273  * TXRX_CSR4: OFDM RX BBP ID.
0274  */
0275 #define TXRX_CSR3           0x0446
0276 #define TXRX_CSR4           0x0448
0277
0278 /*
0279  * TXRX_CSR5: CCK TX BBP ID0.
0280  */
0281 #define TXRX_CSR5           0x044a
0282 #define TXRX_CSR5_BBP_ID0       FIELD16(0x007f)
0283 #define TXRX_CSR5_BBP_ID0_VALID     FIELD16(0x0080)
0284 #define TXRX_CSR5_BBP_ID1       FIELD16(0x7f00)
0285 #define TXRX_CSR5_BBP_ID1_VALID     FIELD16(0x8000)
0286
0287 /*
0288  * TXRX_CSR6: CCK TX BBP ID1.
0289  */
0290 #define TXRX_CSR6           0x044c
0291 #define TXRX_CSR6_BBP_ID0       FIELD16(0x007f)
0292 #define TXRX_CSR6_BBP_ID0_VALID     FIELD16(0x0080)
0293 #define TXRX_CSR6_BBP_ID1       FIELD16(0x7f00)
0294 #define TXRX_CSR6_BBP_ID1_VALID     FIELD16(0x8000)
0295
0296 /*
0297  * TXRX_CSR7: OFDM TX BBP ID0.
0298  */
0299 #define TXRX_CSR7           0x044e
0300 #define TXRX_CSR7_BBP_ID0       FIELD16(0x007f)
0301 #define TXRX_CSR7_BBP_ID0_VALID     FIELD16(0x0080)
0302 #define TXRX_CSR7_BBP_ID1       FIELD16(0x7f00)
0303 #define TXRX_CSR7_BBP_ID1_VALID     FIELD16(0x8000)
0304
0305 /*
0306  * TXRX_CSR8: OFDM TX BBP ID1.
0307  */
0308 #define TXRX_CSR8           0x0450
0309 #define TXRX_CSR8_BBP_ID0       FIELD16(0x007f)
0310 #define TXRX_CSR8_BBP_ID0_VALID     FIELD16(0x0080)
0311 #define TXRX_CSR8_BBP_ID1       FIELD16(0x7f00)
0312 #define TXRX_CSR8_BBP_ID1_VALID     FIELD16(0x8000)
0313
0314 /*
0315  * TXRX_CSR9: TX ACK time-out.
0316  */
0317 #define TXRX_CSR9           0x0452
0318
0319 /*
0320  * TXRX_CSR10: Auto responder control.
0321  */
0322 #define TXRX_CSR10          0x0454
0323 #define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
0324
0325 /*
0326  * TXRX_CSR11: Auto responder basic rate.
0327  */
0328 #define TXRX_CSR11          0x0456
0329
0330 /*
0331  * ACK/CTS time registers.
0332  */
0333 #define TXRX_CSR12          0x0458
0334 #define TXRX_CSR13          0x045a
0335 #define TXRX_CSR14          0x045c
0336 #define TXRX_CSR15          0x045e
0337 #define TXRX_CSR16          0x0460
0338 #define TXRX_CSR17          0x0462
0339
0340 /*
0341  * TXRX_CSR18: Synchronization control register.
0342  */
0343 #define TXRX_CSR18          0x0464
0344 #define TXRX_CSR18_OFFSET       FIELD16(0x000f)
0345 #define TXRX_CSR18_INTERVAL     FIELD16(0xfff0)
0346
0347 /*
0348  * TXRX_CSR19: Synchronization control register.
0349  * TSF_COUNT: Enable TSF auto counting.
0350  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
0351  * TBCN: Enable Tbcn with reload value.
0352  * BEACON_GEN: Enable beacon generator.
0353  */
0354 #define TXRX_CSR19          0x0466
0355 #define TXRX_CSR19_TSF_COUNT        FIELD16(0x0001)
0356 #define TXRX_CSR19_TSF_SYNC     FIELD16(0x0006)
0357 #define TXRX_CSR19_TBCN         FIELD16(0x0008)
0358 #define TXRX_CSR19_BEACON_GEN       FIELD16(0x0010)
0359
0360 /*
0361  * TXRX_CSR20: Tx BEACON offset time control register.
0362  * OFFSET: In units of usec.
0363  * BCN_EXPECT_WINDOW: Default: 2^CWmin
0364  */
0365 #define TXRX_CSR20          0x0468
0366 #define TXRX_CSR20_OFFSET       FIELD16(0x1fff)
0367 #define TXRX_CSR20_BCN_EXPECT_WINDOW    FIELD16(0xe000)
0368
0369 /*
0370  * TXRX_CSR21
0371  */
0372 #define TXRX_CSR21          0x046a
0373
0374 /*
0375  * Encryption related CSRs.
0376  *
0377  */
0378
0379 /*
0380  * SEC_CSR0: Shared key 0, word 0
0381  * SEC_CSR1: Shared key 0, word 1
0382  * SEC_CSR2: Shared key 0, word 2
0383  * SEC_CSR3: Shared key 0, word 3
0384  * SEC_CSR4: Shared key 0, word 4
0385  * SEC_CSR5: Shared key 0, word 5
0386  * SEC_CSR6: Shared key 0, word 6
0387  * SEC_CSR7: Shared key 0, word 7
0388  */
0389 #define SEC_CSR0            0x0480
0390 #define SEC_CSR1            0x0482
0391 #define SEC_CSR2            0x0484
0392 #define SEC_CSR3            0x0486
0393 #define SEC_CSR4            0x0488
0394 #define SEC_CSR5            0x048a
0395 #define SEC_CSR6            0x048c
0396 #define SEC_CSR7            0x048e
0397
0398 /*
0399  * SEC_CSR8: Shared key 1, word 0
0400  * SEC_CSR9: Shared key 1, word 1
0401  * SEC_CSR10: Shared key 1, word 2
0402  * SEC_CSR11: Shared key 1, word 3
0403  * SEC_CSR12: Shared key 1, word 4
0404  * SEC_CSR13: Shared key 1, word 5
0405  * SEC_CSR14: Shared key 1, word 6
0406  * SEC_CSR15: Shared key 1, word 7
0407  */
0408 #define SEC_CSR8            0x0490
0409 #define SEC_CSR9            0x0492
0410 #define SEC_CSR10           0x0494
0411 #define SEC_CSR11           0x0496
0412 #define SEC_CSR12           0x0498
0413 #define SEC_CSR13           0x049a
0414 #define SEC_CSR14           0x049c
0415 #define SEC_CSR15           0x049e
0416
0417 /*
0418  * SEC_CSR16: Shared key 2, word 0
0419  * SEC_CSR17: Shared key 2, word 1
0420  * SEC_CSR18: Shared key 2, word 2
0421  * SEC_CSR19: Shared key 2, word 3
0422  * SEC_CSR20: Shared key 2, word 4
0423  * SEC_CSR21: Shared key 2, word 5
0424  * SEC_CSR22: Shared key 2, word 6
0425  * SEC_CSR23: Shared key 2, word 7
0426  */
0427 #define SEC_CSR16           0x04a0
0428 #define SEC_CSR17           0x04a2
0429 #define SEC_CSR18           0X04A4
0430 #define SEC_CSR19           0x04a6
0431 #define SEC_CSR20           0x04a8
0432 #define SEC_CSR21           0x04aa
0433 #define SEC_CSR22           0x04ac
0434 #define SEC_CSR23           0x04ae
0435
0436 /*
0437  * SEC_CSR24: Shared key 3, word 0
0438  * SEC_CSR25: Shared key 3, word 1
0439  * SEC_CSR26: Shared key 3, word 2
0440  * SEC_CSR27: Shared key 3, word 3
0441  * SEC_CSR28: Shared key 3, word 4
0442  * SEC_CSR29: Shared key 3, word 5
0443  * SEC_CSR30: Shared key 3, word 6
0444  * SEC_CSR31: Shared key 3, word 7
0445  */
0446 #define SEC_CSR24           0x04b0
0447 #define SEC_CSR25           0x04b2
0448 #define SEC_CSR26           0x04b4
0449 #define SEC_CSR27           0x04b6
0450 #define SEC_CSR28           0x04b8
0451 #define SEC_CSR29           0x04ba
0452 #define SEC_CSR30           0x04bc
0453 #define SEC_CSR31           0x04be
0454
0455 #define KEY_ENTRY(__idx) \
0456     ( SEC_CSR0 + ((__idx) * 16) )
0457
0458 /*
0459  * PHY control registers.
0460  */
0461
0462 /*
0463  * PHY_CSR0: RF switching timing control.
0464  */
0465 #define PHY_CSR0            0x04c0
0466
0467 /*
0468  * PHY_CSR1: TX PA configuration.
0469  */
0470 #define PHY_CSR1            0x04c2
0471
0472 /*
0473  * MAC configuration registers.
0474  */
0475
0476 /*
0477  * PHY_CSR2: TX MAC configuration.
0478  * NOTE: Both register fields are complete dummy,
0479  * documentation and legacy drivers are unclear un
0480  * what this register means or what fields exists.
0481  */
0482 #define PHY_CSR2            0x04c4
0483 #define PHY_CSR2_LNA            FIELD16(0x0002)
0484 #define PHY_CSR2_LNA_MODE       FIELD16(0x3000)
0485
0486 /*
0487  * PHY_CSR3: RX MAC configuration.
0488  */
0489 #define PHY_CSR3            0x04c6
0490
0491 /*
0492  * PHY_CSR4: Interface configuration.
0493  */
0494 #define PHY_CSR4            0x04c8
0495 #define PHY_CSR4_LOW_RF_LE      FIELD16(0x0001)
0496
0497 /*
0498  * BBP pre-TX registers.
0499  * PHY_CSR5: BBP pre-TX CCK.
0500  */
0501 #define PHY_CSR5            0x04ca
0502 #define PHY_CSR5_CCK            FIELD16(0x0003)
0503 #define PHY_CSR5_CCK_FLIP       FIELD16(0x0004)
0504
0505 /*
0506  * BBP pre-TX registers.
0507  * PHY_CSR6: BBP pre-TX OFDM.
0508  */
0509 #define PHY_CSR6            0x04cc
0510 #define PHY_CSR6_OFDM           FIELD16(0x0003)
0511 #define PHY_CSR6_OFDM_FLIP      FIELD16(0x0004)
0512
0513 /*
0514  * PHY_CSR7: BBP access register 0.
0515  * BBP_DATA: BBP data.
0516  * BBP_REG_ID: BBP register ID.
0517  * BBP_READ_CONTROL: 0: write, 1: read.
0518  */
0519 #define PHY_CSR7            0x04ce
0520 #define PHY_CSR7_DATA           FIELD16(0x00ff)
0521 #define PHY_CSR7_REG_ID         FIELD16(0x7f00)
0522 #define PHY_CSR7_READ_CONTROL       FIELD16(0x8000)
0523
0524 /*
0525  * PHY_CSR8: BBP access register 1.
0526  * BBP_BUSY: ASIC is busy execute BBP programming.
0527  */
0528 #define PHY_CSR8            0x04d0
0529 #define PHY_CSR8_BUSY           FIELD16(0x0001)
0530
0531 /*
0532  * PHY_CSR9: RF access register.
0533  * RF_VALUE: Register value + id to program into rf/if.
0534  */
0535 #define PHY_CSR9            0x04d2
0536 #define PHY_CSR9_RF_VALUE       FIELD16(0xffff)
0537
0538 /*
0539  * PHY_CSR10: RF access register.
0540  * RF_VALUE: Register value + id to program into rf/if.
0541  * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
0542  * RF_IF_SELECT: Chip to program: 0: rf, 1: if.
0543  * RF_PLL_LD: Rf pll_ld status.
0544  * RF_BUSY: 1: asic is busy execute rf programming.
0545  */
0546 #define PHY_CSR10           0x04d4
0547 #define PHY_CSR10_RF_VALUE      FIELD16(0x00ff)
0548 #define PHY_CSR10_RF_NUMBER_OF_BITS FIELD16(0x1f00)
0549 #define PHY_CSR10_RF_IF_SELECT      FIELD16(0x2000)
0550 #define PHY_CSR10_RF_PLL_LD     FIELD16(0x4000)
0551 #define PHY_CSR10_RF_BUSY       FIELD16(0x8000)
0552
0553 /*
0554  * STA_CSR0: FCS error count.
0555  * FCS_ERROR: FCS error count, cleared when read.
0556  */
0557 #define STA_CSR0            0x04e0
0558 #define STA_CSR0_FCS_ERROR      FIELD16(0xffff)
0559
0560 /*
0561  * STA_CSR1: PLCP error count.
0562  */
0563 #define STA_CSR1            0x04e2
0564
0565 /*
0566  * STA_CSR2: LONG error count.
0567  */
0568 #define STA_CSR2            0x04e4
0569
0570 /*
0571  * STA_CSR3: CCA false alarm.
0572  * FALSE_CCA_ERROR: False CCA error count, cleared when read.
0573  */
0574 #define STA_CSR3            0x04e6
0575 #define STA_CSR3_FALSE_CCA_ERROR    FIELD16(0xffff)
0576
0577 /*
0578  * STA_CSR4: RX FIFO overflow.
0579  */
0580 #define STA_CSR4            0x04e8
0581
0582 /*
0583  * STA_CSR5: Beacon sent counter.
0584  */
0585 #define STA_CSR5            0x04ea
0586
0587 /*
0588  *  Statistics registers
0589  */
0590 #define STA_CSR6            0x04ec
0591 #define STA_CSR7            0x04ee
0592 #define STA_CSR8            0x04f0
0593 #define STA_CSR9            0x04f2
0594 #define STA_CSR10           0x04f4
0595
0596 /*
0597  * BBP registers.
0598  * The wordsize of the BBP is 8 bits.
0599  */
0600
0601 /*
0602  * R2: TX antenna control
0603  */
0604 #define BBP_R2_TX_ANTENNA       FIELD8(0x03)
0605 #define BBP_R2_TX_IQ_FLIP       FIELD8(0x04)
0606
0607 /*
0608  * R14: RX antenna control
0609  */
0610 #define BBP_R14_RX_ANTENNA      FIELD8(0x03)
0611 #define BBP_R14_RX_IQ_FLIP      FIELD8(0x04)
0612
0613 /*
0614  * RF registers.
0615  */
0616
0617 /*
0618  * RF 1
0619  */
0620 #define RF1_TUNER           FIELD32(0x00020000)
0621
0622 /*
0623  * RF 3
0624  */
0625 #define RF3_TUNER           FIELD32(0x00000100)
0626 #define RF3_TXPOWER         FIELD32(0x00003e00)
0627
0628 /*
0629  * EEPROM contents.
0630  */
0631
0632 /*
0633  * HW MAC address.
0634  */
0635 #define EEPROM_MAC_ADDR_0       0x0002
0636 #define EEPROM_MAC_ADDR_BYTE0       FIELD16(0x00ff)
0637 #define EEPROM_MAC_ADDR_BYTE1       FIELD16(0xff00)
0638 #define EEPROM_MAC_ADDR1        0x0003
0639 #define EEPROM_MAC_ADDR_BYTE2       FIELD16(0x00ff)
0640 #define EEPROM_MAC_ADDR_BYTE3       FIELD16(0xff00)
0641 #define EEPROM_MAC_ADDR_2       0x0004
0642 #define EEPROM_MAC_ADDR_BYTE4       FIELD16(0x00ff)
0643 #define EEPROM_MAC_ADDR_BYTE5       FIELD16(0xff00)
0644
0645 /*
0646  * EEPROM antenna.
0647  * ANTENNA_NUM: Number of antenna's.
0648  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
0649  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
0650  * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
0651  * DYN_TXAGC: Dynamic TX AGC control.
0652  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
0653  * RF_TYPE: Rf_type of this adapter.
0654  */
0655 #define EEPROM_ANTENNA          0x000b
0656 #define EEPROM_ANTENNA_NUM      FIELD16(0x0003)
0657 #define EEPROM_ANTENNA_TX_DEFAULT   FIELD16(0x000c)
0658 #define EEPROM_ANTENNA_RX_DEFAULT   FIELD16(0x0030)
0659 #define EEPROM_ANTENNA_LED_MODE     FIELD16(0x01c0)
0660 #define EEPROM_ANTENNA_DYN_TXAGC    FIELD16(0x0200)
0661 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
0662 #define EEPROM_ANTENNA_RF_TYPE      FIELD16(0xf800)
0663
0664 /*
0665  * EEPROM NIC config.
0666  * CARDBUS_ACCEL: 0: enable, 1: disable.
0667  * DYN_BBP_TUNE: 0: enable, 1: disable.
0668  * CCK_TX_POWER: CCK TX power compensation.
0669  */
0670 #define EEPROM_NIC          0x000c
0671 #define EEPROM_NIC_CARDBUS_ACCEL    FIELD16(0x0001)
0672 #define EEPROM_NIC_DYN_BBP_TUNE     FIELD16(0x0002)
0673 #define EEPROM_NIC_CCK_TX_POWER     FIELD16(0x000c)
0674
0675 /*
0676  * EEPROM geography.
0677  * GEO: Default geography setting for device.
0678  */
0679 #define EEPROM_GEOGRAPHY        0x000d
0680 #define EEPROM_GEOGRAPHY_GEO        FIELD16(0x0f00)
0681
0682 /*
0683  * EEPROM BBP.
0684  */
0685 #define EEPROM_BBP_START        0x000e
0686 #define EEPROM_BBP_SIZE         16
0687 #define EEPROM_BBP_VALUE        FIELD16(0x00ff)
0688 #define EEPROM_BBP_REG_ID       FIELD16(0xff00)
0689
0690 /*
0691  * EEPROM TXPOWER
0692  */
0693 #define EEPROM_TXPOWER_START        0x001e
0694 #define EEPROM_TXPOWER_SIZE     7
0695 #define EEPROM_TXPOWER_1        FIELD16(0x00ff)
0696 #define EEPROM_TXPOWER_2        FIELD16(0xff00)
0697
0698 /*
0699  * EEPROM Tuning threshold
0700  */
0701 #define EEPROM_BBPTUNE          0x0030
0702 #define EEPROM_BBPTUNE_THRESHOLD    FIELD16(0x00ff)
0703
0704 /*
0705  * EEPROM BBP R24 Tuning.
0706  */
0707 #define EEPROM_BBPTUNE_R24      0x0031
0708 #define EEPROM_BBPTUNE_R24_LOW      FIELD16(0x00ff)
0709 #define EEPROM_BBPTUNE_R24_HIGH     FIELD16(0xff00)
0710
0711 /*
0712  * EEPROM BBP R25 Tuning.
0713  */
0714 #define EEPROM_BBPTUNE_R25      0x0032
0715 #define EEPROM_BBPTUNE_R25_LOW      FIELD16(0x00ff)
0716 #define EEPROM_BBPTUNE_R25_HIGH     FIELD16(0xff00)
0717
0718 /*
0719  * EEPROM BBP R24 Tuning.
0720  */
0721 #define EEPROM_BBPTUNE_R61      0x0033
0722 #define EEPROM_BBPTUNE_R61_LOW      FIELD16(0x00ff)
0723 #define EEPROM_BBPTUNE_R61_HIGH     FIELD16(0xff00)
0724
0725 /*
0726  * EEPROM BBP VGC Tuning.
0727  */
0728 #define EEPROM_BBPTUNE_VGC      0x0034
0729 #define EEPROM_BBPTUNE_VGCUPPER     FIELD16(0x00ff)
0730 #define EEPROM_BBPTUNE_VGCLOWER     FIELD16(0xff00)
0731
0732 /*
0733  * EEPROM BBP R17 Tuning.
0734  */
0735 #define EEPROM_BBPTUNE_R17      0x0035
0736 #define EEPROM_BBPTUNE_R17_LOW      FIELD16(0x00ff)
0737 #define EEPROM_BBPTUNE_R17_HIGH     FIELD16(0xff00)
0738
0739 /*
0740  * RSSI <-> dBm offset calibration
0741  */
0742 #define EEPROM_CALIBRATE_OFFSET     0x0036
0743 #define EEPROM_CALIBRATE_OFFSET_RSSI    FIELD16(0x00ff)
0744
0745 /*
0746  * DMA descriptor defines.
0747  */
0748 #define TXD_DESC_SIZE           ( 5 * sizeof(__le32) )
0749 #define RXD_DESC_SIZE           ( 4 * sizeof(__le32) )
0750
0751 /*
0752  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
0753  */
0754
0755 /*
0756  * Word0
0757  */
0758 #define TXD_W0_PACKET_ID        FIELD32(0x0000000f)
0759 #define TXD_W0_RETRY_LIMIT      FIELD32(0x000000f0)
0760 #define TXD_W0_MORE_FRAG        FIELD32(0x00000100)
0761 #define TXD_W0_ACK          FIELD32(0x00000200)
0762 #define TXD_W0_TIMESTAMP        FIELD32(0x00000400)
0763 #define TXD_W0_OFDM         FIELD32(0x00000800)
0764 #define TXD_W0_NEW_SEQ          FIELD32(0x00001000)
0765 #define TXD_W0_IFS          FIELD32(0x00006000)
0766 #define TXD_W0_DATABYTE_COUNT       FIELD32(0x0fff0000)
0767 #define TXD_W0_CIPHER           FIELD32(0x20000000)
0768 #define TXD_W0_KEY_ID           FIELD32(0xc0000000)
0769
0770 /*
0771  * Word1
0772  */
0773 #define TXD_W1_IV_OFFSET        FIELD32(0x0000003f)
0774 #define TXD_W1_AIFS         FIELD32(0x000000c0)
0775 #define TXD_W1_CWMIN            FIELD32(0x00000f00)
0776 #define TXD_W1_CWMAX            FIELD32(0x0000f000)
0777
0778 /*
0779  * Word2: PLCP information
0780  */
0781 #define TXD_W2_PLCP_SIGNAL      FIELD32(0x000000ff)
0782 #define TXD_W2_PLCP_SERVICE     FIELD32(0x0000ff00)
0783 #define TXD_W2_PLCP_LENGTH_LOW      FIELD32(0x00ff0000)
0784 #define TXD_W2_PLCP_LENGTH_HIGH     FIELD32(0xff000000)
0785
0786 /*
0787  * Word3
0788  */
0789 #define TXD_W3_IV           FIELD32(0xffffffff)
0790
0791 /*
0792  * Word4
0793  */
0794 #define TXD_W4_EIV          FIELD32(0xffffffff)
0795
0796 /*
0797  * RX descriptor format for RX Ring.
0798  */
0799
0800 /*
0801  * Word0
0802  */
0803 #define RXD_W0_UNICAST_TO_ME        FIELD32(0x00000002)
0804 #define RXD_W0_MULTICAST        FIELD32(0x00000004)
0805 #define RXD_W0_BROADCAST        FIELD32(0x00000008)
0806 #define RXD_W0_MY_BSS           FIELD32(0x00000010)
0807 #define RXD_W0_CRC_ERROR        FIELD32(0x00000020)
0808 #define RXD_W0_OFDM         FIELD32(0x00000040)
0809 #define RXD_W0_PHYSICAL_ERROR       FIELD32(0x00000080)
0810 #define RXD_W0_CIPHER           FIELD32(0x00000100)
0811 #define RXD_W0_CIPHER_ERROR     FIELD32(0x00000200)
0812 #define RXD_W0_DATABYTE_COUNT       FIELD32(0x0fff0000)
0813
0814 /*
0815  * Word1
0816  */
0817 #define RXD_W1_RSSI         FIELD32(0x000000ff)
0818 #define RXD_W1_SIGNAL           FIELD32(0x0000ff00)
0819
0820 /*
0821  * Word2
0822  */
0823 #define RXD_W2_IV           FIELD32(0xffffffff)
0824
0825 /*
0826  * Word3
0827  */
0828 #define RXD_W3_EIV          FIELD32(0xffffffff)
0829
0830 /*
0831  * Macros for converting txpower from EEPROM to mac80211 value
0832  * and from mac80211 value to register value.
0833  */
0834 #define MIN_TXPOWER 0
0835 #define MAX_TXPOWER 31
0836 #define DEFAULT_TXPOWER 24
0837
0838 #define TXPOWER_FROM_DEV(__txpower) \
0839     (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
0840
0841 #define TXPOWER_TO_DEV(__txpower) \
0842     clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
0843
0844 #endif /* RT2500USB_H */