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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003     Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
0004     <http://rt2x00.serialmonkey.com>
0005 
0006  */
0007 
0008 /*
0009     Module: rt2500pci
0010     Abstract: Data structures and registers for the rt2500pci module.
0011     Supported chipsets: RT2560.
0012  */
0013 
0014 #ifndef RT2500PCI_H
0015 #define RT2500PCI_H
0016 
0017 /*
0018  * RF chip defines.
0019  */
0020 #define RF2522              0x0000
0021 #define RF2523              0x0001
0022 #define RF2524              0x0002
0023 #define RF2525              0x0003
0024 #define RF2525E             0x0004
0025 #define RF5222              0x0010
0026 
0027 /*
0028  * RT2560 version
0029  */
0030 #define RT2560_VERSION_B        2
0031 #define RT2560_VERSION_C        3
0032 #define RT2560_VERSION_D        4
0033 
0034 /*
0035  * Signal information.
0036  * Default offset is required for RSSI <-> dBm conversion.
0037  */
0038 #define DEFAULT_RSSI_OFFSET     121
0039 
0040 /*
0041  * Register layout information.
0042  */
0043 #define CSR_REG_BASE            0x0000
0044 #define CSR_REG_SIZE            0x0174
0045 #define EEPROM_BASE         0x0000
0046 #define EEPROM_SIZE         0x0200
0047 #define BBP_BASE            0x0000
0048 #define BBP_SIZE            0x0040
0049 #define RF_BASE             0x0004
0050 #define RF_SIZE             0x0010
0051 
0052 /*
0053  * Number of TX queues.
0054  */
0055 #define NUM_TX_QUEUES           2
0056 
0057 /*
0058  * Control/Status Registers(CSR).
0059  * Some values are set in TU, whereas 1 TU == 1024 us.
0060  */
0061 
0062 /*
0063  * CSR0: ASIC revision number.
0064  */
0065 #define CSR0                0x0000
0066 #define CSR0_REVISION           FIELD32(0x0000ffff)
0067 
0068 /*
0069  * CSR1: System control register.
0070  * SOFT_RESET: Software reset, 1: reset, 0: normal.
0071  * BBP_RESET: Hardware reset, 1: reset, 0, release.
0072  * HOST_READY: Host ready after initialization.
0073  */
0074 #define CSR1                0x0004
0075 #define CSR1_SOFT_RESET         FIELD32(0x00000001)
0076 #define CSR1_BBP_RESET          FIELD32(0x00000002)
0077 #define CSR1_HOST_READY         FIELD32(0x00000004)
0078 
0079 /*
0080  * CSR2: System admin status register (invalid).
0081  */
0082 #define CSR2                0x0008
0083 
0084 /*
0085  * CSR3: STA MAC address register 0.
0086  */
0087 #define CSR3                0x000c
0088 #define CSR3_BYTE0          FIELD32(0x000000ff)
0089 #define CSR3_BYTE1          FIELD32(0x0000ff00)
0090 #define CSR3_BYTE2          FIELD32(0x00ff0000)
0091 #define CSR3_BYTE3          FIELD32(0xff000000)
0092 
0093 /*
0094  * CSR4: STA MAC address register 1.
0095  */
0096 #define CSR4                0x0010
0097 #define CSR4_BYTE4          FIELD32(0x000000ff)
0098 #define CSR4_BYTE5          FIELD32(0x0000ff00)
0099 
0100 /*
0101  * CSR5: BSSID register 0.
0102  */
0103 #define CSR5                0x0014
0104 #define CSR5_BYTE0          FIELD32(0x000000ff)
0105 #define CSR5_BYTE1          FIELD32(0x0000ff00)
0106 #define CSR5_BYTE2          FIELD32(0x00ff0000)
0107 #define CSR5_BYTE3          FIELD32(0xff000000)
0108 
0109 /*
0110  * CSR6: BSSID register 1.
0111  */
0112 #define CSR6                0x0018
0113 #define CSR6_BYTE4          FIELD32(0x000000ff)
0114 #define CSR6_BYTE5          FIELD32(0x0000ff00)
0115 
0116 /*
0117  * CSR7: Interrupt source register.
0118  * Write 1 to clear.
0119  * TBCN_EXPIRE: Beacon timer expired interrupt.
0120  * TWAKE_EXPIRE: Wakeup timer expired interrupt.
0121  * TATIMW_EXPIRE: Timer of atim window expired interrupt.
0122  * TXDONE_TXRING: Tx ring transmit done interrupt.
0123  * TXDONE_ATIMRING: Atim ring transmit done interrupt.
0124  * TXDONE_PRIORING: Priority ring transmit done interrupt.
0125  * RXDONE: Receive done interrupt.
0126  * DECRYPTION_DONE: Decryption done interrupt.
0127  * ENCRYPTION_DONE: Encryption done interrupt.
0128  * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
0129  * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
0130  * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
0131  * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
0132  * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
0133  * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
0134  * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
0135  * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
0136  * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
0137  * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
0138  * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
0139 
0140  */
0141 #define CSR7                0x001c
0142 #define CSR7_TBCN_EXPIRE        FIELD32(0x00000001)
0143 #define CSR7_TWAKE_EXPIRE       FIELD32(0x00000002)
0144 #define CSR7_TATIMW_EXPIRE      FIELD32(0x00000004)
0145 #define CSR7_TXDONE_TXRING      FIELD32(0x00000008)
0146 #define CSR7_TXDONE_ATIMRING        FIELD32(0x00000010)
0147 #define CSR7_TXDONE_PRIORING        FIELD32(0x00000020)
0148 #define CSR7_RXDONE         FIELD32(0x00000040)
0149 #define CSR7_DECRYPTION_DONE        FIELD32(0x00000080)
0150 #define CSR7_ENCRYPTION_DONE        FIELD32(0x00000100)
0151 #define CSR7_UART1_TX_TRESHOLD      FIELD32(0x00000200)
0152 #define CSR7_UART1_RX_TRESHOLD      FIELD32(0x00000400)
0153 #define CSR7_UART1_IDLE_TRESHOLD    FIELD32(0x00000800)
0154 #define CSR7_UART1_TX_BUFF_ERROR    FIELD32(0x00001000)
0155 #define CSR7_UART1_RX_BUFF_ERROR    FIELD32(0x00002000)
0156 #define CSR7_UART2_TX_TRESHOLD      FIELD32(0x00004000)
0157 #define CSR7_UART2_RX_TRESHOLD      FIELD32(0x00008000)
0158 #define CSR7_UART2_IDLE_TRESHOLD    FIELD32(0x00010000)
0159 #define CSR7_UART2_TX_BUFF_ERROR    FIELD32(0x00020000)
0160 #define CSR7_UART2_RX_BUFF_ERROR    FIELD32(0x00040000)
0161 #define CSR7_TIMER_CSR3_EXPIRE      FIELD32(0x00080000)
0162 
0163 /*
0164  * CSR8: Interrupt mask register.
0165  * Write 1 to mask interrupt.
0166  * TBCN_EXPIRE: Beacon timer expired interrupt.
0167  * TWAKE_EXPIRE: Wakeup timer expired interrupt.
0168  * TATIMW_EXPIRE: Timer of atim window expired interrupt.
0169  * TXDONE_TXRING: Tx ring transmit done interrupt.
0170  * TXDONE_ATIMRING: Atim ring transmit done interrupt.
0171  * TXDONE_PRIORING: Priority ring transmit done interrupt.
0172  * RXDONE: Receive done interrupt.
0173  * DECRYPTION_DONE: Decryption done interrupt.
0174  * ENCRYPTION_DONE: Encryption done interrupt.
0175  * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
0176  * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
0177  * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
0178  * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
0179  * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
0180  * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
0181  * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
0182  * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
0183  * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
0184  * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
0185  * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
0186  */
0187 #define CSR8                0x0020
0188 #define CSR8_TBCN_EXPIRE        FIELD32(0x00000001)
0189 #define CSR8_TWAKE_EXPIRE       FIELD32(0x00000002)
0190 #define CSR8_TATIMW_EXPIRE      FIELD32(0x00000004)
0191 #define CSR8_TXDONE_TXRING      FIELD32(0x00000008)
0192 #define CSR8_TXDONE_ATIMRING        FIELD32(0x00000010)
0193 #define CSR8_TXDONE_PRIORING        FIELD32(0x00000020)
0194 #define CSR8_RXDONE         FIELD32(0x00000040)
0195 #define CSR8_DECRYPTION_DONE        FIELD32(0x00000080)
0196 #define CSR8_ENCRYPTION_DONE        FIELD32(0x00000100)
0197 #define CSR8_UART1_TX_TRESHOLD      FIELD32(0x00000200)
0198 #define CSR8_UART1_RX_TRESHOLD      FIELD32(0x00000400)
0199 #define CSR8_UART1_IDLE_TRESHOLD    FIELD32(0x00000800)
0200 #define CSR8_UART1_TX_BUFF_ERROR    FIELD32(0x00001000)
0201 #define CSR8_UART1_RX_BUFF_ERROR    FIELD32(0x00002000)
0202 #define CSR8_UART2_TX_TRESHOLD      FIELD32(0x00004000)
0203 #define CSR8_UART2_RX_TRESHOLD      FIELD32(0x00008000)
0204 #define CSR8_UART2_IDLE_TRESHOLD    FIELD32(0x00010000)
0205 #define CSR8_UART2_TX_BUFF_ERROR    FIELD32(0x00020000)
0206 #define CSR8_UART2_RX_BUFF_ERROR    FIELD32(0x00040000)
0207 #define CSR8_TIMER_CSR3_EXPIRE      FIELD32(0x00080000)
0208 
0209 /*
0210  * CSR9: Maximum frame length register.
0211  * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
0212  */
0213 #define CSR9                0x0024
0214 #define CSR9_MAX_FRAME_UNIT     FIELD32(0x00000f80)
0215 
0216 /*
0217  * SECCSR0: WEP control register.
0218  * KICK_DECRYPT: Kick decryption engine, self-clear.
0219  * ONE_SHOT: 0: ring mode, 1: One shot only mode.
0220  * DESC_ADDRESS: Descriptor physical address of frame.
0221  */
0222 #define SECCSR0             0x0028
0223 #define SECCSR0_KICK_DECRYPT        FIELD32(0x00000001)
0224 #define SECCSR0_ONE_SHOT        FIELD32(0x00000002)
0225 #define SECCSR0_DESC_ADDRESS        FIELD32(0xfffffffc)
0226 
0227 /*
0228  * CSR11: Back-off control register.
0229  * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
0230  * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
0231  * SLOT_TIME: Slot time, default is 20us for 802.11b
0232  * CW_SELECT: CWmin/CWmax selection, 1: Register, 0: TXD.
0233  * LONG_RETRY: Long retry count.
0234  * SHORT_RETRY: Short retry count.
0235  */
0236 #define CSR11               0x002c
0237 #define CSR11_CWMIN         FIELD32(0x0000000f)
0238 #define CSR11_CWMAX         FIELD32(0x000000f0)
0239 #define CSR11_SLOT_TIME         FIELD32(0x00001f00)
0240 #define CSR11_CW_SELECT         FIELD32(0x00002000)
0241 #define CSR11_LONG_RETRY        FIELD32(0x00ff0000)
0242 #define CSR11_SHORT_RETRY       FIELD32(0xff000000)
0243 
0244 /*
0245  * CSR12: Synchronization configuration register 0.
0246  * All units in 1/16 TU.
0247  * BEACON_INTERVAL: Beacon interval, default is 100 TU.
0248  * CFP_MAX_DURATION: Cfp maximum duration, default is 100 TU.
0249  */
0250 #define CSR12               0x0030
0251 #define CSR12_BEACON_INTERVAL       FIELD32(0x0000ffff)
0252 #define CSR12_CFP_MAX_DURATION      FIELD32(0xffff0000)
0253 
0254 /*
0255  * CSR13: Synchronization configuration register 1.
0256  * All units in 1/16 TU.
0257  * ATIMW_DURATION: Atim window duration.
0258  * CFP_PERIOD: Cfp period, default is 0 TU.
0259  */
0260 #define CSR13               0x0034
0261 #define CSR13_ATIMW_DURATION        FIELD32(0x0000ffff)
0262 #define CSR13_CFP_PERIOD        FIELD32(0x00ff0000)
0263 
0264 /*
0265  * CSR14: Synchronization control register.
0266  * TSF_COUNT: Enable tsf auto counting.
0267  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
0268  * TBCN: Enable tbcn with reload value.
0269  * TCFP: Enable tcfp & cfp / cp switching.
0270  * TATIMW: Enable tatimw & atim window switching.
0271  * BEACON_GEN: Enable beacon generator.
0272  * CFP_COUNT_PRELOAD: Cfp count preload value.
0273  * TBCM_PRELOAD: Tbcn preload value in units of 64us.
0274  */
0275 #define CSR14               0x0038
0276 #define CSR14_TSF_COUNT         FIELD32(0x00000001)
0277 #define CSR14_TSF_SYNC          FIELD32(0x00000006)
0278 #define CSR14_TBCN          FIELD32(0x00000008)
0279 #define CSR14_TCFP          FIELD32(0x00000010)
0280 #define CSR14_TATIMW            FIELD32(0x00000020)
0281 #define CSR14_BEACON_GEN        FIELD32(0x00000040)
0282 #define CSR14_CFP_COUNT_PRELOAD     FIELD32(0x0000ff00)
0283 #define CSR14_TBCM_PRELOAD      FIELD32(0xffff0000)
0284 
0285 /*
0286  * CSR15: Synchronization status register.
0287  * CFP: ASIC is in contention-free period.
0288  * ATIMW: ASIC is in ATIM window.
0289  * BEACON_SENT: Beacon is send.
0290  */
0291 #define CSR15               0x003c
0292 #define CSR15_CFP           FIELD32(0x00000001)
0293 #define CSR15_ATIMW         FIELD32(0x00000002)
0294 #define CSR15_BEACON_SENT       FIELD32(0x00000004)
0295 
0296 /*
0297  * CSR16: TSF timer register 0.
0298  */
0299 #define CSR16               0x0040
0300 #define CSR16_LOW_TSFTIMER      FIELD32(0xffffffff)
0301 
0302 /*
0303  * CSR17: TSF timer register 1.
0304  */
0305 #define CSR17               0x0044
0306 #define CSR17_HIGH_TSFTIMER     FIELD32(0xffffffff)
0307 
0308 /*
0309  * CSR18: IFS timer register 0.
0310  * SIFS: Sifs, default is 10 us.
0311  * PIFS: Pifs, default is 30 us.
0312  */
0313 #define CSR18               0x0048
0314 #define CSR18_SIFS          FIELD32(0x000001ff)
0315 #define CSR18_PIFS          FIELD32(0x001f0000)
0316 
0317 /*
0318  * CSR19: IFS timer register 1.
0319  * DIFS: Difs, default is 50 us.
0320  * EIFS: Eifs, default is 364 us.
0321  */
0322 #define CSR19               0x004c
0323 #define CSR19_DIFS          FIELD32(0x0000ffff)
0324 #define CSR19_EIFS          FIELD32(0xffff0000)
0325 
0326 /*
0327  * CSR20: Wakeup timer register.
0328  * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
0329  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
0330  * AUTOWAKE: Enable auto wakeup / sleep mechanism.
0331  */
0332 #define CSR20               0x0050
0333 #define CSR20_DELAY_AFTER_TBCN      FIELD32(0x0000ffff)
0334 #define CSR20_TBCN_BEFORE_WAKEUP    FIELD32(0x00ff0000)
0335 #define CSR20_AUTOWAKE          FIELD32(0x01000000)
0336 
0337 /*
0338  * CSR21: EEPROM control register.
0339  * RELOAD: Write 1 to reload eeprom content.
0340  * TYPE_93C46: 1: 93c46, 0:93c66.
0341  */
0342 #define CSR21               0x0054
0343 #define CSR21_RELOAD            FIELD32(0x00000001)
0344 #define CSR21_EEPROM_DATA_CLOCK     FIELD32(0x00000002)
0345 #define CSR21_EEPROM_CHIP_SELECT    FIELD32(0x00000004)
0346 #define CSR21_EEPROM_DATA_IN        FIELD32(0x00000008)
0347 #define CSR21_EEPROM_DATA_OUT       FIELD32(0x00000010)
0348 #define CSR21_TYPE_93C46        FIELD32(0x00000020)
0349 
0350 /*
0351  * CSR22: CFP control register.
0352  * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
0353  * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
0354  */
0355 #define CSR22               0x0058
0356 #define CSR22_CFP_DURATION_REMAIN   FIELD32(0x0000ffff)
0357 #define CSR22_RELOAD_CFP_DURATION   FIELD32(0x00010000)
0358 
0359 /*
0360  * Transmit related CSRs.
0361  * Some values are set in TU, whereas 1 TU == 1024 us.
0362  */
0363 
0364 /*
0365  * TXCSR0: TX Control Register.
0366  * KICK_TX: Kick tx ring.
0367  * KICK_ATIM: Kick atim ring.
0368  * KICK_PRIO: Kick priority ring.
0369  * ABORT: Abort all transmit related ring operation.
0370  */
0371 #define TXCSR0              0x0060
0372 #define TXCSR0_KICK_TX          FIELD32(0x00000001)
0373 #define TXCSR0_KICK_ATIM        FIELD32(0x00000002)
0374 #define TXCSR0_KICK_PRIO        FIELD32(0x00000004)
0375 #define TXCSR0_ABORT            FIELD32(0x00000008)
0376 
0377 /*
0378  * TXCSR1: TX Configuration Register.
0379  * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
0380  * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
0381  * TSF_OFFSET: Insert tsf offset.
0382  * AUTORESPONDER: Enable auto responder which include ack & cts.
0383  */
0384 #define TXCSR1              0x0064
0385 #define TXCSR1_ACK_TIMEOUT      FIELD32(0x000001ff)
0386 #define TXCSR1_ACK_CONSUME_TIME     FIELD32(0x0003fe00)
0387 #define TXCSR1_TSF_OFFSET       FIELD32(0x00fc0000)
0388 #define TXCSR1_AUTORESPONDER        FIELD32(0x01000000)
0389 
0390 /*
0391  * TXCSR2: Tx descriptor configuration register.
0392  * TXD_SIZE: Tx descriptor size, default is 48.
0393  * NUM_TXD: Number of tx entries in ring.
0394  * NUM_ATIM: Number of atim entries in ring.
0395  * NUM_PRIO: Number of priority entries in ring.
0396  */
0397 #define TXCSR2              0x0068
0398 #define TXCSR2_TXD_SIZE         FIELD32(0x000000ff)
0399 #define TXCSR2_NUM_TXD          FIELD32(0x0000ff00)
0400 #define TXCSR2_NUM_ATIM         FIELD32(0x00ff0000)
0401 #define TXCSR2_NUM_PRIO         FIELD32(0xff000000)
0402 
0403 /*
0404  * TXCSR3: TX Ring Base address register.
0405  */
0406 #define TXCSR3              0x006c
0407 #define TXCSR3_TX_RING_REGISTER     FIELD32(0xffffffff)
0408 
0409 /*
0410  * TXCSR4: TX Atim Ring Base address register.
0411  */
0412 #define TXCSR4              0x0070
0413 #define TXCSR4_ATIM_RING_REGISTER   FIELD32(0xffffffff)
0414 
0415 /*
0416  * TXCSR5: TX Prio Ring Base address register.
0417  */
0418 #define TXCSR5              0x0074
0419 #define TXCSR5_PRIO_RING_REGISTER   FIELD32(0xffffffff)
0420 
0421 /*
0422  * TXCSR6: Beacon Base address register.
0423  */
0424 #define TXCSR6              0x0078
0425 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
0426 
0427 /*
0428  * TXCSR7: Auto responder control register.
0429  * AR_POWERMANAGEMENT: Auto responder power management bit.
0430  */
0431 #define TXCSR7              0x007c
0432 #define TXCSR7_AR_POWERMANAGEMENT   FIELD32(0x00000001)
0433 
0434 /*
0435  * TXCSR8: CCK Tx BBP register.
0436  */
0437 #define TXCSR8              0x0098
0438 #define TXCSR8_BBP_ID0          FIELD32(0x0000007f)
0439 #define TXCSR8_BBP_ID0_VALID        FIELD32(0x00000080)
0440 #define TXCSR8_BBP_ID1          FIELD32(0x00007f00)
0441 #define TXCSR8_BBP_ID1_VALID        FIELD32(0x00008000)
0442 #define TXCSR8_BBP_ID2          FIELD32(0x007f0000)
0443 #define TXCSR8_BBP_ID2_VALID        FIELD32(0x00800000)
0444 #define TXCSR8_BBP_ID3          FIELD32(0x7f000000)
0445 #define TXCSR8_BBP_ID3_VALID        FIELD32(0x80000000)
0446 
0447 /*
0448  * TXCSR9: OFDM TX BBP registers
0449  * OFDM_SIGNAL: BBP rate field address for OFDM.
0450  * OFDM_SERVICE: BBP service field address for OFDM.
0451  * OFDM_LENGTH_LOW: BBP length low byte address for OFDM.
0452  * OFDM_LENGTH_HIGH: BBP length high byte address for OFDM.
0453  */
0454 #define TXCSR9              0x0094
0455 #define TXCSR9_OFDM_RATE        FIELD32(0x000000ff)
0456 #define TXCSR9_OFDM_SERVICE     FIELD32(0x0000ff00)
0457 #define TXCSR9_OFDM_LENGTH_LOW      FIELD32(0x00ff0000)
0458 #define TXCSR9_OFDM_LENGTH_HIGH     FIELD32(0xff000000)
0459 
0460 /*
0461  * Receive related CSRs.
0462  * Some values are set in TU, whereas 1 TU == 1024 us.
0463  */
0464 
0465 /*
0466  * RXCSR0: RX Control Register.
0467  * DISABLE_RX: Disable rx engine.
0468  * DROP_CRC: Drop crc error.
0469  * DROP_PHYSICAL: Drop physical error.
0470  * DROP_CONTROL: Drop control frame.
0471  * DROP_NOT_TO_ME: Drop not to me unicast frame.
0472  * DROP_TODS: Drop frame tods bit is true.
0473  * DROP_VERSION_ERROR: Drop version error frame.
0474  * PASS_CRC: Pass all packets with crc attached.
0475  * PASS_CRC: Pass all packets with crc attached.
0476  * PASS_PLCP: Pass all packets with 4 bytes PLCP attached.
0477  * DROP_MCAST: Drop multicast frames.
0478  * DROP_BCAST: Drop broadcast frames.
0479  * ENABLE_QOS: Accept QOS data frame and parse QOS field.
0480  */
0481 #define RXCSR0              0x0080
0482 #define RXCSR0_DISABLE_RX       FIELD32(0x00000001)
0483 #define RXCSR0_DROP_CRC         FIELD32(0x00000002)
0484 #define RXCSR0_DROP_PHYSICAL        FIELD32(0x00000004)
0485 #define RXCSR0_DROP_CONTROL     FIELD32(0x00000008)
0486 #define RXCSR0_DROP_NOT_TO_ME       FIELD32(0x00000010)
0487 #define RXCSR0_DROP_TODS        FIELD32(0x00000020)
0488 #define RXCSR0_DROP_VERSION_ERROR   FIELD32(0x00000040)
0489 #define RXCSR0_PASS_CRC         FIELD32(0x00000080)
0490 #define RXCSR0_PASS_PLCP        FIELD32(0x00000100)
0491 #define RXCSR0_DROP_MCAST       FIELD32(0x00000200)
0492 #define RXCSR0_DROP_BCAST       FIELD32(0x00000400)
0493 #define RXCSR0_ENABLE_QOS       FIELD32(0x00000800)
0494 
0495 /*
0496  * RXCSR1: RX descriptor configuration register.
0497  * RXD_SIZE: Rx descriptor size, default is 32b.
0498  * NUM_RXD: Number of rx entries in ring.
0499  */
0500 #define RXCSR1              0x0084
0501 #define RXCSR1_RXD_SIZE         FIELD32(0x000000ff)
0502 #define RXCSR1_NUM_RXD          FIELD32(0x0000ff00)
0503 
0504 /*
0505  * RXCSR2: RX Ring base address register.
0506  */
0507 #define RXCSR2              0x0088
0508 #define RXCSR2_RX_RING_REGISTER     FIELD32(0xffffffff)
0509 
0510 /*
0511  * RXCSR3: BBP ID register for Rx operation.
0512  * BBP_ID#: BBP register # id.
0513  * BBP_ID#_VALID: BBP register # id is valid or not.
0514  */
0515 #define RXCSR3              0x0090
0516 #define RXCSR3_BBP_ID0          FIELD32(0x0000007f)
0517 #define RXCSR3_BBP_ID0_VALID        FIELD32(0x00000080)
0518 #define RXCSR3_BBP_ID1          FIELD32(0x00007f00)
0519 #define RXCSR3_BBP_ID1_VALID        FIELD32(0x00008000)
0520 #define RXCSR3_BBP_ID2          FIELD32(0x007f0000)
0521 #define RXCSR3_BBP_ID2_VALID        FIELD32(0x00800000)
0522 #define RXCSR3_BBP_ID3          FIELD32(0x7f000000)
0523 #define RXCSR3_BBP_ID3_VALID        FIELD32(0x80000000)
0524 
0525 /*
0526  * ARCSR1: Auto Responder PLCP config register 1.
0527  * AR_BBP_DATA#: Auto responder BBP register # data.
0528  * AR_BBP_ID#: Auto responder BBP register # Id.
0529  */
0530 #define ARCSR1              0x009c
0531 #define ARCSR1_AR_BBP_DATA2     FIELD32(0x000000ff)
0532 #define ARCSR1_AR_BBP_ID2       FIELD32(0x0000ff00)
0533 #define ARCSR1_AR_BBP_DATA3     FIELD32(0x00ff0000)
0534 #define ARCSR1_AR_BBP_ID3       FIELD32(0xff000000)
0535 
0536 /*
0537  * Miscellaneous Registers.
0538  * Some values are set in TU, whereas 1 TU == 1024 us.
0539 
0540  */
0541 
0542 /*
0543  * PCICSR: PCI control register.
0544  * BIG_ENDIAN: 1: big endian, 0: little endian.
0545  * RX_TRESHOLD: Rx threshold in dw to start pci access
0546  * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
0547  * TX_TRESHOLD: Tx threshold in dw to start pci access
0548  * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
0549  * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
0550  * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
0551  * READ_MULTIPLE: Enable memory read multiple.
0552  * WRITE_INVALID: Enable memory write & invalid.
0553  */
0554 #define PCICSR              0x008c
0555 #define PCICSR_BIG_ENDIAN       FIELD32(0x00000001)
0556 #define PCICSR_RX_TRESHOLD      FIELD32(0x00000006)
0557 #define PCICSR_TX_TRESHOLD      FIELD32(0x00000018)
0558 #define PCICSR_BURST_LENTH      FIELD32(0x00000060)
0559 #define PCICSR_ENABLE_CLK       FIELD32(0x00000080)
0560 #define PCICSR_READ_MULTIPLE        FIELD32(0x00000100)
0561 #define PCICSR_WRITE_INVALID        FIELD32(0x00000200)
0562 
0563 /*
0564  * CNT0: FCS error count.
0565  * FCS_ERROR: FCS error count, cleared when read.
0566  */
0567 #define CNT0                0x00a0
0568 #define CNT0_FCS_ERROR          FIELD32(0x0000ffff)
0569 
0570 /*
0571  * Statistic Register.
0572  * CNT1: PLCP error count.
0573  * CNT2: Long error count.
0574  */
0575 #define TIMECSR2            0x00a8
0576 #define CNT1                0x00ac
0577 #define CNT2                0x00b0
0578 #define TIMECSR3            0x00b4
0579 
0580 /*
0581  * CNT3: CCA false alarm count.
0582  */
0583 #define CNT3                0x00b8
0584 #define CNT3_FALSE_CCA          FIELD32(0x0000ffff)
0585 
0586 /*
0587  * Statistic Register.
0588  * CNT4: Rx FIFO overflow count.
0589  * CNT5: Tx FIFO underrun count.
0590  */
0591 #define CNT4                0x00bc
0592 #define CNT5                0x00c0
0593 
0594 /*
0595  * Baseband Control Register.
0596  */
0597 
0598 /*
0599  * PWRCSR0: Power mode configuration register.
0600  */
0601 #define PWRCSR0             0x00c4
0602 
0603 /*
0604  * Power state transition time registers.
0605  */
0606 #define PSCSR0              0x00c8
0607 #define PSCSR1              0x00cc
0608 #define PSCSR2              0x00d0
0609 #define PSCSR3              0x00d4
0610 
0611 /*
0612  * PWRCSR1: Manual power control / status register.
0613  * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
0614  * SET_STATE: Set state. Write 1 to trigger, self cleared.
0615  * BBP_DESIRE_STATE: BBP desired state.
0616  * RF_DESIRE_STATE: RF desired state.
0617  * BBP_CURR_STATE: BBP current state.
0618  * RF_CURR_STATE: RF current state.
0619  * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
0620  */
0621 #define PWRCSR1             0x00d8
0622 #define PWRCSR1_SET_STATE       FIELD32(0x00000001)
0623 #define PWRCSR1_BBP_DESIRE_STATE    FIELD32(0x00000006)
0624 #define PWRCSR1_RF_DESIRE_STATE     FIELD32(0x00000018)
0625 #define PWRCSR1_BBP_CURR_STATE      FIELD32(0x00000060)
0626 #define PWRCSR1_RF_CURR_STATE       FIELD32(0x00000180)
0627 #define PWRCSR1_PUT_TO_SLEEP        FIELD32(0x00000200)
0628 
0629 /*
0630  * TIMECSR: Timer control register.
0631  * US_COUNT: 1 us timer count in units of clock cycles.
0632  * US_64_COUNT: 64 us timer count in units of 1 us timer.
0633  * BEACON_EXPECT: Beacon expect window.
0634  */
0635 #define TIMECSR             0x00dc
0636 #define TIMECSR_US_COUNT        FIELD32(0x000000ff)
0637 #define TIMECSR_US_64_COUNT     FIELD32(0x0000ff00)
0638 #define TIMECSR_BEACON_EXPECT       FIELD32(0x00070000)
0639 
0640 /*
0641  * MACCSR0: MAC configuration register 0.
0642  */
0643 #define MACCSR0             0x00e0
0644 
0645 /*
0646  * MACCSR1: MAC configuration register 1.
0647  * KICK_RX: Kick one-shot rx in one-shot rx mode.
0648  * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
0649  * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
0650  * AUTO_TXBBP: Auto tx logic access bbp control register.
0651  * AUTO_RXBBP: Auto rx logic access bbp control register.
0652  * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
0653  * INTERSIL_IF: Intersil if calibration pin.
0654  */
0655 #define MACCSR1             0x00e4
0656 #define MACCSR1_KICK_RX         FIELD32(0x00000001)
0657 #define MACCSR1_ONESHOT_RXMODE      FIELD32(0x00000002)
0658 #define MACCSR1_BBPRX_RESET_MODE    FIELD32(0x00000004)
0659 #define MACCSR1_AUTO_TXBBP      FIELD32(0x00000008)
0660 #define MACCSR1_AUTO_RXBBP      FIELD32(0x00000010)
0661 #define MACCSR1_LOOPBACK        FIELD32(0x00000060)
0662 #define MACCSR1_INTERSIL_IF     FIELD32(0x00000080)
0663 
0664 /*
0665  * RALINKCSR: Ralink Rx auto-reset BBCR.
0666  * AR_BBP_DATA#: Auto reset BBP register # data.
0667  * AR_BBP_ID#: Auto reset BBP register # id.
0668  */
0669 #define RALINKCSR           0x00e8
0670 #define RALINKCSR_AR_BBP_DATA0      FIELD32(0x000000ff)
0671 #define RALINKCSR_AR_BBP_ID0        FIELD32(0x00007f00)
0672 #define RALINKCSR_AR_BBP_VALID0     FIELD32(0x00008000)
0673 #define RALINKCSR_AR_BBP_DATA1      FIELD32(0x00ff0000)
0674 #define RALINKCSR_AR_BBP_ID1        FIELD32(0x7f000000)
0675 #define RALINKCSR_AR_BBP_VALID1     FIELD32(0x80000000)
0676 
0677 /*
0678  * BCNCSR: Beacon interval control register.
0679  * CHANGE: Write one to change beacon interval.
0680  * DELTATIME: The delta time value.
0681  * NUM_BEACON: Number of beacon according to mode.
0682  * MODE: Please refer to asic specs.
0683  * PLUS: Plus or minus delta time value.
0684  */
0685 #define BCNCSR              0x00ec
0686 #define BCNCSR_CHANGE           FIELD32(0x00000001)
0687 #define BCNCSR_DELTATIME        FIELD32(0x0000001e)
0688 #define BCNCSR_NUM_BEACON       FIELD32(0x00001fe0)
0689 #define BCNCSR_MODE         FIELD32(0x00006000)
0690 #define BCNCSR_PLUS         FIELD32(0x00008000)
0691 
0692 /*
0693  * BBP / RF / IF Control Register.
0694  */
0695 
0696 /*
0697  * BBPCSR: BBP serial control register.
0698  * VALUE: Register value to program into BBP.
0699  * REGNUM: Selected BBP register.
0700  * BUSY: 1: asic is busy execute BBP programming.
0701  * WRITE_CONTROL: 1: write BBP, 0: read BBP.
0702  */
0703 #define BBPCSR              0x00f0
0704 #define BBPCSR_VALUE            FIELD32(0x000000ff)
0705 #define BBPCSR_REGNUM           FIELD32(0x00007f00)
0706 #define BBPCSR_BUSY         FIELD32(0x00008000)
0707 #define BBPCSR_WRITE_CONTROL        FIELD32(0x00010000)
0708 
0709 /*
0710  * RFCSR: RF serial control register.
0711  * VALUE: Register value + id to program into rf/if.
0712  * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
0713  * IF_SELECT: Chip to program: 0: rf, 1: if.
0714  * PLL_LD: Rf pll_ld status.
0715  * BUSY: 1: asic is busy execute rf programming.
0716  */
0717 #define RFCSR               0x00f4
0718 #define RFCSR_VALUE         FIELD32(0x00ffffff)
0719 #define RFCSR_NUMBER_OF_BITS        FIELD32(0x1f000000)
0720 #define RFCSR_IF_SELECT         FIELD32(0x20000000)
0721 #define RFCSR_PLL_LD            FIELD32(0x40000000)
0722 #define RFCSR_BUSY          FIELD32(0x80000000)
0723 
0724 /*
0725  * LEDCSR: LED control register.
0726  * ON_PERIOD: On period, default 70ms.
0727  * OFF_PERIOD: Off period, default 30ms.
0728  * LINK: 0: linkoff, 1: linkup.
0729  * ACTIVITY: 0: idle, 1: active.
0730  * LINK_POLARITY: 0: active low, 1: active high.
0731  * ACTIVITY_POLARITY: 0: active low, 1: active high.
0732  * LED_DEFAULT: LED state for "enable" 0: ON, 1: OFF.
0733  */
0734 #define LEDCSR              0x00f8
0735 #define LEDCSR_ON_PERIOD        FIELD32(0x000000ff)
0736 #define LEDCSR_OFF_PERIOD       FIELD32(0x0000ff00)
0737 #define LEDCSR_LINK         FIELD32(0x00010000)
0738 #define LEDCSR_ACTIVITY         FIELD32(0x00020000)
0739 #define LEDCSR_LINK_POLARITY        FIELD32(0x00040000)
0740 #define LEDCSR_ACTIVITY_POLARITY    FIELD32(0x00080000)
0741 #define LEDCSR_LED_DEFAULT      FIELD32(0x00100000)
0742 
0743 /*
0744  * SECCSR3: AES control register.
0745  */
0746 #define SECCSR3             0x00fc
0747 
0748 /*
0749  * ASIC pointer information.
0750  * RXPTR: Current RX ring address.
0751  * TXPTR: Current Tx ring address.
0752  * PRIPTR: Current Priority ring address.
0753  * ATIMPTR: Current ATIM ring address.
0754  */
0755 #define RXPTR               0x0100
0756 #define TXPTR               0x0104
0757 #define PRIPTR              0x0108
0758 #define ATIMPTR             0x010c
0759 
0760 /*
0761  * TXACKCSR0: TX ACK timeout.
0762  */
0763 #define TXACKCSR0           0x0110
0764 
0765 /*
0766  * ACK timeout count registers.
0767  * ACKCNT0: TX ACK timeout count.
0768  * ACKCNT1: RX ACK timeout count.
0769  */
0770 #define ACKCNT0             0x0114
0771 #define ACKCNT1             0x0118
0772 
0773 /*
0774  * GPIO and others.
0775  */
0776 
0777 /*
0778  * GPIOCSR: GPIO control register.
0779  *  GPIOCSR_VALx: GPIO value
0780  *  GPIOCSR_DIRx: GPIO direction: 0 = output; 1 = input
0781  */
0782 #define GPIOCSR             0x0120
0783 #define GPIOCSR_VAL0            FIELD32(0x00000001)
0784 #define GPIOCSR_VAL1            FIELD32(0x00000002)
0785 #define GPIOCSR_VAL2            FIELD32(0x00000004)
0786 #define GPIOCSR_VAL3            FIELD32(0x00000008)
0787 #define GPIOCSR_VAL4            FIELD32(0x00000010)
0788 #define GPIOCSR_VAL5            FIELD32(0x00000020)
0789 #define GPIOCSR_VAL6            FIELD32(0x00000040)
0790 #define GPIOCSR_VAL7            FIELD32(0x00000080)
0791 #define GPIOCSR_DIR0            FIELD32(0x00000100)
0792 #define GPIOCSR_DIR1            FIELD32(0x00000200)
0793 #define GPIOCSR_DIR2            FIELD32(0x00000400)
0794 #define GPIOCSR_DIR3            FIELD32(0x00000800)
0795 #define GPIOCSR_DIR4            FIELD32(0x00001000)
0796 #define GPIOCSR_DIR5            FIELD32(0x00002000)
0797 #define GPIOCSR_DIR6            FIELD32(0x00004000)
0798 #define GPIOCSR_DIR7            FIELD32(0x00008000)
0799 
0800 /*
0801  * FIFO pointer registers.
0802  * FIFOCSR0: TX FIFO pointer.
0803  * FIFOCSR1: RX FIFO pointer.
0804  */
0805 #define FIFOCSR0            0x0128
0806 #define FIFOCSR1            0x012c
0807 
0808 /*
0809  * BCNCSR1: Tx BEACON offset time control register.
0810  * PRELOAD: Beacon timer offset in units of usec.
0811  * BEACON_CWMIN: 2^CwMin.
0812  */
0813 #define BCNCSR1             0x0130
0814 #define BCNCSR1_PRELOAD         FIELD32(0x0000ffff)
0815 #define BCNCSR1_BEACON_CWMIN        FIELD32(0x000f0000)
0816 
0817 /*
0818  * MACCSR2: TX_PE to RX_PE turn-around time control register
0819  * DELAY: RX_PE low width, in units of pci clock cycle.
0820  */
0821 #define MACCSR2             0x0134
0822 #define MACCSR2_DELAY           FIELD32(0x000000ff)
0823 
0824 /*
0825  * TESTCSR: TEST mode selection register.
0826  */
0827 #define TESTCSR             0x0138
0828 
0829 /*
0830  * ARCSR2: 1 Mbps ACK/CTS PLCP.
0831  */
0832 #define ARCSR2              0x013c
0833 #define ARCSR2_SIGNAL           FIELD32(0x000000ff)
0834 #define ARCSR2_SERVICE          FIELD32(0x0000ff00)
0835 #define ARCSR2_LENGTH           FIELD32(0xffff0000)
0836 
0837 /*
0838  * ARCSR3: 2 Mbps ACK/CTS PLCP.
0839  */
0840 #define ARCSR3              0x0140
0841 #define ARCSR3_SIGNAL           FIELD32(0x000000ff)
0842 #define ARCSR3_SERVICE          FIELD32(0x0000ff00)
0843 #define ARCSR3_LENGTH           FIELD32(0xffff0000)
0844 
0845 /*
0846  * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
0847  */
0848 #define ARCSR4              0x0144
0849 #define ARCSR4_SIGNAL           FIELD32(0x000000ff)
0850 #define ARCSR4_SERVICE          FIELD32(0x0000ff00)
0851 #define ARCSR4_LENGTH           FIELD32(0xffff0000)
0852 
0853 /*
0854  * ARCSR5: 11 Mbps ACK/CTS PLCP.
0855  */
0856 #define ARCSR5              0x0148
0857 #define ARCSR5_SIGNAL           FIELD32(0x000000ff)
0858 #define ARCSR5_SERVICE          FIELD32(0x0000ff00)
0859 #define ARCSR5_LENGTH           FIELD32(0xffff0000)
0860 
0861 /*
0862  * ARTCSR0: CCK ACK/CTS payload consumed time for 1/2/5.5/11 mbps.
0863  */
0864 #define ARTCSR0             0x014c
0865 #define ARTCSR0_ACK_CTS_11MBS       FIELD32(0x000000ff)
0866 #define ARTCSR0_ACK_CTS_5_5MBS      FIELD32(0x0000ff00)
0867 #define ARTCSR0_ACK_CTS_2MBS        FIELD32(0x00ff0000)
0868 #define ARTCSR0_ACK_CTS_1MBS        FIELD32(0xff000000)
0869 
0870 
0871 /*
0872  * ARTCSR1: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
0873  */
0874 #define ARTCSR1             0x0150
0875 #define ARTCSR1_ACK_CTS_6MBS        FIELD32(0x000000ff)
0876 #define ARTCSR1_ACK_CTS_9MBS        FIELD32(0x0000ff00)
0877 #define ARTCSR1_ACK_CTS_12MBS       FIELD32(0x00ff0000)
0878 #define ARTCSR1_ACK_CTS_18MBS       FIELD32(0xff000000)
0879 
0880 /*
0881  * ARTCSR2: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
0882  */
0883 #define ARTCSR2             0x0154
0884 #define ARTCSR2_ACK_CTS_24MBS       FIELD32(0x000000ff)
0885 #define ARTCSR2_ACK_CTS_36MBS       FIELD32(0x0000ff00)
0886 #define ARTCSR2_ACK_CTS_48MBS       FIELD32(0x00ff0000)
0887 #define ARTCSR2_ACK_CTS_54MBS       FIELD32(0xff000000)
0888 
0889 /*
0890  * SECCSR1: WEP control register.
0891  * KICK_ENCRYPT: Kick encryption engine, self-clear.
0892  * ONE_SHOT: 0: ring mode, 1: One shot only mode.
0893  * DESC_ADDRESS: Descriptor physical address of frame.
0894  */
0895 #define SECCSR1             0x0158
0896 #define SECCSR1_KICK_ENCRYPT        FIELD32(0x00000001)
0897 #define SECCSR1_ONE_SHOT        FIELD32(0x00000002)
0898 #define SECCSR1_DESC_ADDRESS        FIELD32(0xfffffffc)
0899 
0900 /*
0901  * BBPCSR1: BBP TX configuration.
0902  */
0903 #define BBPCSR1             0x015c
0904 #define BBPCSR1_CCK         FIELD32(0x00000003)
0905 #define BBPCSR1_CCK_FLIP        FIELD32(0x00000004)
0906 #define BBPCSR1_OFDM            FIELD32(0x00030000)
0907 #define BBPCSR1_OFDM_FLIP       FIELD32(0x00040000)
0908 
0909 /*
0910  * Dual band configuration registers.
0911  * DBANDCSR0: Dual band configuration register 0.
0912  * DBANDCSR1: Dual band configuration register 1.
0913  */
0914 #define DBANDCSR0           0x0160
0915 #define DBANDCSR1           0x0164
0916 
0917 /*
0918  * BBPPCSR: BBP Pin control register.
0919  */
0920 #define BBPPCSR             0x0168
0921 
0922 /*
0923  * MAC special debug mode selection registers.
0924  * DBGSEL0: MAC special debug mode selection register 0.
0925  * DBGSEL1: MAC special debug mode selection register 1.
0926  */
0927 #define DBGSEL0             0x016c
0928 #define DBGSEL1             0x0170
0929 
0930 /*
0931  * BISTCSR: BBP BIST register.
0932  */
0933 #define BISTCSR             0x0174
0934 
0935 /*
0936  * Multicast filter registers.
0937  * MCAST0: Multicast filter register 0.
0938  * MCAST1: Multicast filter register 1.
0939  */
0940 #define MCAST0              0x0178
0941 #define MCAST1              0x017c
0942 
0943 /*
0944  * UART registers.
0945  * UARTCSR0: UART1 TX register.
0946  * UARTCSR1: UART1 RX register.
0947  * UARTCSR3: UART1 frame control register.
0948  * UARTCSR4: UART1 buffer control register.
0949  * UART2CSR0: UART2 TX register.
0950  * UART2CSR1: UART2 RX register.
0951  * UART2CSR3: UART2 frame control register.
0952  * UART2CSR4: UART2 buffer control register.
0953  */
0954 #define UARTCSR0            0x0180
0955 #define UARTCSR1            0x0184
0956 #define UARTCSR3            0x0188
0957 #define UARTCSR4            0x018c
0958 #define UART2CSR0           0x0190
0959 #define UART2CSR1           0x0194
0960 #define UART2CSR3           0x0198
0961 #define UART2CSR4           0x019c
0962 
0963 /*
0964  * BBP registers.
0965  * The wordsize of the BBP is 8 bits.
0966  */
0967 
0968 /*
0969  * R2: TX antenna control
0970  */
0971 #define BBP_R2_TX_ANTENNA       FIELD8(0x03)
0972 #define BBP_R2_TX_IQ_FLIP       FIELD8(0x04)
0973 
0974 /*
0975  * R14: RX antenna control
0976  */
0977 #define BBP_R14_RX_ANTENNA      FIELD8(0x03)
0978 #define BBP_R14_RX_IQ_FLIP      FIELD8(0x04)
0979 
0980 /*
0981  * BBP_R70
0982  */
0983 #define BBP_R70_JAPAN_FILTER        FIELD8(0x08)
0984 
0985 /*
0986  * RF registers
0987  */
0988 
0989 /*
0990  * RF 1
0991  */
0992 #define RF1_TUNER           FIELD32(0x00020000)
0993 
0994 /*
0995  * RF 3
0996  */
0997 #define RF3_TUNER           FIELD32(0x00000100)
0998 #define RF3_TXPOWER         FIELD32(0x00003e00)
0999 
1000 /*
1001  * EEPROM content.
1002  * The wordsize of the EEPROM is 16 bits.
1003  */
1004 
1005 /*
1006  * HW MAC address.
1007  */
1008 #define EEPROM_MAC_ADDR_0       0x0002
1009 #define EEPROM_MAC_ADDR_BYTE0       FIELD16(0x00ff)
1010 #define EEPROM_MAC_ADDR_BYTE1       FIELD16(0xff00)
1011 #define EEPROM_MAC_ADDR1        0x0003
1012 #define EEPROM_MAC_ADDR_BYTE2       FIELD16(0x00ff)
1013 #define EEPROM_MAC_ADDR_BYTE3       FIELD16(0xff00)
1014 #define EEPROM_MAC_ADDR_2       0x0004
1015 #define EEPROM_MAC_ADDR_BYTE4       FIELD16(0x00ff)
1016 #define EEPROM_MAC_ADDR_BYTE5       FIELD16(0xff00)
1017 
1018 /*
1019  * EEPROM antenna.
1020  * ANTENNA_NUM: Number of antenna's.
1021  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1022  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1023  * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
1024  * DYN_TXAGC: Dynamic TX AGC control.
1025  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1026  * RF_TYPE: Rf_type of this adapter.
1027  */
1028 #define EEPROM_ANTENNA          0x10
1029 #define EEPROM_ANTENNA_NUM      FIELD16(0x0003)
1030 #define EEPROM_ANTENNA_TX_DEFAULT   FIELD16(0x000c)
1031 #define EEPROM_ANTENNA_RX_DEFAULT   FIELD16(0x0030)
1032 #define EEPROM_ANTENNA_LED_MODE     FIELD16(0x01c0)
1033 #define EEPROM_ANTENNA_DYN_TXAGC    FIELD16(0x0200)
1034 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
1035 #define EEPROM_ANTENNA_RF_TYPE      FIELD16(0xf800)
1036 
1037 /*
1038  * EEPROM NIC config.
1039  * CARDBUS_ACCEL: 0: enable, 1: disable.
1040  * DYN_BBP_TUNE: 0: enable, 1: disable.
1041  * CCK_TX_POWER: CCK TX power compensation.
1042  */
1043 #define EEPROM_NIC          0x11
1044 #define EEPROM_NIC_CARDBUS_ACCEL    FIELD16(0x0001)
1045 #define EEPROM_NIC_DYN_BBP_TUNE     FIELD16(0x0002)
1046 #define EEPROM_NIC_CCK_TX_POWER     FIELD16(0x000c)
1047 
1048 /*
1049  * EEPROM geography.
1050  * GEO: Default geography setting for device.
1051  */
1052 #define EEPROM_GEOGRAPHY        0x12
1053 #define EEPROM_GEOGRAPHY_GEO        FIELD16(0x0f00)
1054 
1055 /*
1056  * EEPROM BBP.
1057  */
1058 #define EEPROM_BBP_START        0x13
1059 #define EEPROM_BBP_SIZE         16
1060 #define EEPROM_BBP_VALUE        FIELD16(0x00ff)
1061 #define EEPROM_BBP_REG_ID       FIELD16(0xff00)
1062 
1063 /*
1064  * EEPROM TXPOWER
1065  */
1066 #define EEPROM_TXPOWER_START        0x23
1067 #define EEPROM_TXPOWER_SIZE     7
1068 #define EEPROM_TXPOWER_1        FIELD16(0x00ff)
1069 #define EEPROM_TXPOWER_2        FIELD16(0xff00)
1070 
1071 /*
1072  * RSSI <-> dBm offset calibration
1073  */
1074 #define EEPROM_CALIBRATE_OFFSET     0x3e
1075 #define EEPROM_CALIBRATE_OFFSET_RSSI    FIELD16(0x00ff)
1076 
1077 /*
1078  * DMA descriptor defines.
1079  */
1080 #define TXD_DESC_SIZE           (11 * sizeof(__le32))
1081 #define RXD_DESC_SIZE           (11 * sizeof(__le32))
1082 
1083 /*
1084  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
1085  */
1086 
1087 /*
1088  * Word0
1089  */
1090 #define TXD_W0_OWNER_NIC        FIELD32(0x00000001)
1091 #define TXD_W0_VALID            FIELD32(0x00000002)
1092 #define TXD_W0_RESULT           FIELD32(0x0000001c)
1093 #define TXD_W0_RETRY_COUNT      FIELD32(0x000000e0)
1094 #define TXD_W0_MORE_FRAG        FIELD32(0x00000100)
1095 #define TXD_W0_ACK          FIELD32(0x00000200)
1096 #define TXD_W0_TIMESTAMP        FIELD32(0x00000400)
1097 #define TXD_W0_OFDM         FIELD32(0x00000800)
1098 #define TXD_W0_CIPHER_OWNER     FIELD32(0x00001000)
1099 #define TXD_W0_IFS          FIELD32(0x00006000)
1100 #define TXD_W0_RETRY_MODE       FIELD32(0x00008000)
1101 #define TXD_W0_DATABYTE_COUNT       FIELD32(0x0fff0000)
1102 #define TXD_W0_CIPHER_ALG       FIELD32(0xe0000000)
1103 
1104 /*
1105  * Word1
1106  */
1107 #define TXD_W1_BUFFER_ADDRESS       FIELD32(0xffffffff)
1108 
1109 /*
1110  * Word2
1111  */
1112 #define TXD_W2_IV_OFFSET        FIELD32(0x0000003f)
1113 #define TXD_W2_AIFS         FIELD32(0x000000c0)
1114 #define TXD_W2_CWMIN            FIELD32(0x00000f00)
1115 #define TXD_W2_CWMAX            FIELD32(0x0000f000)
1116 
1117 /*
1118  * Word3: PLCP information
1119  */
1120 #define TXD_W3_PLCP_SIGNAL      FIELD32(0x000000ff)
1121 #define TXD_W3_PLCP_SERVICE     FIELD32(0x0000ff00)
1122 #define TXD_W3_PLCP_LENGTH_LOW      FIELD32(0x00ff0000)
1123 #define TXD_W3_PLCP_LENGTH_HIGH     FIELD32(0xff000000)
1124 
1125 /*
1126  * Word4
1127  */
1128 #define TXD_W4_IV           FIELD32(0xffffffff)
1129 
1130 /*
1131  * Word5
1132  */
1133 #define TXD_W5_EIV          FIELD32(0xffffffff)
1134 
1135 /*
1136  * Word6-9: Key
1137  */
1138 #define TXD_W6_KEY          FIELD32(0xffffffff)
1139 #define TXD_W7_KEY          FIELD32(0xffffffff)
1140 #define TXD_W8_KEY          FIELD32(0xffffffff)
1141 #define TXD_W9_KEY          FIELD32(0xffffffff)
1142 
1143 /*
1144  * Word10
1145  */
1146 #define TXD_W10_RTS         FIELD32(0x00000001)
1147 #define TXD_W10_TX_RATE         FIELD32(0x000000fe)
1148 
1149 /*
1150  * RX descriptor format for RX Ring.
1151  */
1152 
1153 /*
1154  * Word0
1155  */
1156 #define RXD_W0_OWNER_NIC        FIELD32(0x00000001)
1157 #define RXD_W0_UNICAST_TO_ME        FIELD32(0x00000002)
1158 #define RXD_W0_MULTICAST        FIELD32(0x00000004)
1159 #define RXD_W0_BROADCAST        FIELD32(0x00000008)
1160 #define RXD_W0_MY_BSS           FIELD32(0x00000010)
1161 #define RXD_W0_CRC_ERROR        FIELD32(0x00000020)
1162 #define RXD_W0_OFDM         FIELD32(0x00000040)
1163 #define RXD_W0_PHYSICAL_ERROR       FIELD32(0x00000080)
1164 #define RXD_W0_CIPHER_OWNER     FIELD32(0x00000100)
1165 #define RXD_W0_ICV_ERROR        FIELD32(0x00000200)
1166 #define RXD_W0_IV_OFFSET        FIELD32(0x0000fc00)
1167 #define RXD_W0_DATABYTE_COUNT       FIELD32(0x0fff0000)
1168 #define RXD_W0_CIPHER_ALG       FIELD32(0xe0000000)
1169 
1170 /*
1171  * Word1
1172  */
1173 #define RXD_W1_BUFFER_ADDRESS       FIELD32(0xffffffff)
1174 
1175 /*
1176  * Word2
1177  */
1178 #define RXD_W2_SIGNAL           FIELD32(0x000000ff)
1179 #define RXD_W2_RSSI         FIELD32(0x0000ff00)
1180 #define RXD_W2_TA           FIELD32(0xffff0000)
1181 
1182 /*
1183  * Word3
1184  */
1185 #define RXD_W3_TA           FIELD32(0xffffffff)
1186 
1187 /*
1188  * Word4
1189  */
1190 #define RXD_W4_IV           FIELD32(0xffffffff)
1191 
1192 /*
1193  * Word5
1194  */
1195 #define RXD_W5_EIV          FIELD32(0xffffffff)
1196 
1197 /*
1198  * Word6-9: Key
1199  */
1200 #define RXD_W6_KEY          FIELD32(0xffffffff)
1201 #define RXD_W7_KEY          FIELD32(0xffffffff)
1202 #define RXD_W8_KEY          FIELD32(0xffffffff)
1203 #define RXD_W9_KEY          FIELD32(0xffffffff)
1204 
1205 /*
1206  * Word10
1207  */
1208 #define RXD_W10_DROP            FIELD32(0x00000001)
1209 
1210 /*
1211  * Macros for converting txpower from EEPROM to mac80211 value
1212  * and from mac80211 value to register value.
1213  */
1214 #define MIN_TXPOWER 0
1215 #define MAX_TXPOWER 31
1216 #define DEFAULT_TXPOWER 24
1217 
1218 #define TXPOWER_FROM_DEV(__txpower) \
1219     (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1220 
1221 #define TXPOWER_TO_DEV(__txpower) \
1222     clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1223 
1224 #endif /* RT2500PCI_H */
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