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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
0004     <http://rt2x00.serialmonkey.com>
0005 
0006  */
0007 
0008 /*
0009     Module: rt2500pci
0010     Abstract: rt2500pci device specific routines.
0011     Supported chipsets: RT2560.
0012  */
0013 
0014 #include <linux/delay.h>
0015 #include <linux/etherdevice.h>
0016 #include <linux/kernel.h>
0017 #include <linux/module.h>
0018 #include <linux/pci.h>
0019 #include <linux/eeprom_93cx6.h>
0020 #include <linux/slab.h>
0021 
0022 #include "rt2x00.h"
0023 #include "rt2x00mmio.h"
0024 #include "rt2x00pci.h"
0025 #include "rt2500pci.h"
0026 
0027 /*
0028  * Register access.
0029  * All access to the CSR registers will go through the methods
0030  * rt2x00mmio_register_read and rt2x00mmio_register_write.
0031  * BBP and RF register require indirect register access,
0032  * and use the CSR registers BBPCSR and RFCSR to achieve this.
0033  * These indirect registers work with busy bits,
0034  * and we will try maximal REGISTER_BUSY_COUNT times to access
0035  * the register while taking a REGISTER_BUSY_DELAY us delay
0036  * between each attampt. When the busy bit is still set at that time,
0037  * the access attempt is considered to have failed,
0038  * and we will print an error.
0039  */
0040 #define WAIT_FOR_BBP(__dev, __reg) \
0041     rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
0042 #define WAIT_FOR_RF(__dev, __reg) \
0043     rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
0044 
0045 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
0046                 const unsigned int word, const u8 value)
0047 {
0048     u32 reg;
0049 
0050     mutex_lock(&rt2x00dev->csr_mutex);
0051 
0052     /*
0053      * Wait until the BBP becomes available, afterwards we
0054      * can safely write the new data into the register.
0055      */
0056     if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
0057         reg = 0;
0058         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
0059         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
0060         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
0061         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
0062 
0063         rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
0064     }
0065 
0066     mutex_unlock(&rt2x00dev->csr_mutex);
0067 }
0068 
0069 static u8 rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
0070                  const unsigned int word)
0071 {
0072     u32 reg;
0073     u8 value;
0074 
0075     mutex_lock(&rt2x00dev->csr_mutex);
0076 
0077     /*
0078      * Wait until the BBP becomes available, afterwards we
0079      * can safely write the read request into the register.
0080      * After the data has been written, we wait until hardware
0081      * returns the correct value, if at any time the register
0082      * doesn't become available in time, reg will be 0xffffffff
0083      * which means we return 0xff to the caller.
0084      */
0085     if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
0086         reg = 0;
0087         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
0088         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
0089         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
0090 
0091         rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
0092 
0093         WAIT_FOR_BBP(rt2x00dev, &reg);
0094     }
0095 
0096     value = rt2x00_get_field32(reg, BBPCSR_VALUE);
0097 
0098     mutex_unlock(&rt2x00dev->csr_mutex);
0099 
0100     return value;
0101 }
0102 
0103 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
0104                    const unsigned int word, const u32 value)
0105 {
0106     u32 reg;
0107 
0108     mutex_lock(&rt2x00dev->csr_mutex);
0109 
0110     /*
0111      * Wait until the RF becomes available, afterwards we
0112      * can safely write the new data into the register.
0113      */
0114     if (WAIT_FOR_RF(rt2x00dev, &reg)) {
0115         reg = 0;
0116         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
0117         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
0118         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
0119         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
0120 
0121         rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
0122         rt2x00_rf_write(rt2x00dev, word, value);
0123     }
0124 
0125     mutex_unlock(&rt2x00dev->csr_mutex);
0126 }
0127 
0128 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
0129 {
0130     struct rt2x00_dev *rt2x00dev = eeprom->data;
0131     u32 reg;
0132 
0133     reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
0134 
0135     eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
0136     eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
0137     eeprom->reg_data_clock =
0138         !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
0139     eeprom->reg_chip_select =
0140         !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
0141 }
0142 
0143 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
0144 {
0145     struct rt2x00_dev *rt2x00dev = eeprom->data;
0146     u32 reg = 0;
0147 
0148     rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
0149     rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
0150     rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
0151                !!eeprom->reg_data_clock);
0152     rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
0153                !!eeprom->reg_chip_select);
0154 
0155     rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
0156 }
0157 
0158 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
0159 static const struct rt2x00debug rt2500pci_rt2x00debug = {
0160     .owner  = THIS_MODULE,
0161     .csr    = {
0162         .read       = rt2x00mmio_register_read,
0163         .write      = rt2x00mmio_register_write,
0164         .flags      = RT2X00DEBUGFS_OFFSET,
0165         .word_base  = CSR_REG_BASE,
0166         .word_size  = sizeof(u32),
0167         .word_count = CSR_REG_SIZE / sizeof(u32),
0168     },
0169     .eeprom = {
0170         .read       = rt2x00_eeprom_read,
0171         .write      = rt2x00_eeprom_write,
0172         .word_base  = EEPROM_BASE,
0173         .word_size  = sizeof(u16),
0174         .word_count = EEPROM_SIZE / sizeof(u16),
0175     },
0176     .bbp    = {
0177         .read       = rt2500pci_bbp_read,
0178         .write      = rt2500pci_bbp_write,
0179         .word_base  = BBP_BASE,
0180         .word_size  = sizeof(u8),
0181         .word_count = BBP_SIZE / sizeof(u8),
0182     },
0183     .rf = {
0184         .read       = rt2x00_rf_read,
0185         .write      = rt2500pci_rf_write,
0186         .word_base  = RF_BASE,
0187         .word_size  = sizeof(u32),
0188         .word_count = RF_SIZE / sizeof(u32),
0189     },
0190 };
0191 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
0192 
0193 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
0194 {
0195     u32 reg;
0196 
0197     reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
0198     return rt2x00_get_field32(reg, GPIOCSR_VAL0);
0199 }
0200 
0201 #ifdef CONFIG_RT2X00_LIB_LEDS
0202 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
0203                      enum led_brightness brightness)
0204 {
0205     struct rt2x00_led *led =
0206         container_of(led_cdev, struct rt2x00_led, led_dev);
0207     unsigned int enabled = brightness != LED_OFF;
0208     u32 reg;
0209 
0210     reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
0211 
0212     if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
0213         rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
0214     else if (led->type == LED_TYPE_ACTIVITY)
0215         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
0216 
0217     rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
0218 }
0219 
0220 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
0221                    unsigned long *delay_on,
0222                    unsigned long *delay_off)
0223 {
0224     struct rt2x00_led *led =
0225         container_of(led_cdev, struct rt2x00_led, led_dev);
0226     u32 reg;
0227 
0228     reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
0229     rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
0230     rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
0231     rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
0232 
0233     return 0;
0234 }
0235 
0236 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
0237                    struct rt2x00_led *led,
0238                    enum led_type type)
0239 {
0240     led->rt2x00dev = rt2x00dev;
0241     led->type = type;
0242     led->led_dev.brightness_set = rt2500pci_brightness_set;
0243     led->led_dev.blink_set = rt2500pci_blink_set;
0244     led->flags = LED_INITIALIZED;
0245 }
0246 #endif /* CONFIG_RT2X00_LIB_LEDS */
0247 
0248 /*
0249  * Configuration handlers.
0250  */
0251 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
0252                     const unsigned int filter_flags)
0253 {
0254     u32 reg;
0255 
0256     /*
0257      * Start configuration steps.
0258      * Note that the version error will always be dropped
0259      * and broadcast frames will always be accepted since
0260      * there is no filter for it at this time.
0261      */
0262     reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
0263     rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
0264                !(filter_flags & FIF_FCSFAIL));
0265     rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
0266                !(filter_flags & FIF_PLCPFAIL));
0267     rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
0268                !(filter_flags & FIF_CONTROL));
0269     rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
0270                !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
0271     rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
0272                !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) &&
0273                !rt2x00dev->intf_ap_count);
0274     rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
0275     rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
0276                !(filter_flags & FIF_ALLMULTI));
0277     rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
0278     rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
0279 }
0280 
0281 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
0282                   struct rt2x00_intf *intf,
0283                   struct rt2x00intf_conf *conf,
0284                   const unsigned int flags)
0285 {
0286     struct data_queue *queue = rt2x00dev->bcn;
0287     unsigned int bcn_preload;
0288     u32 reg;
0289 
0290     if (flags & CONFIG_UPDATE_TYPE) {
0291         /*
0292          * Enable beacon config
0293          */
0294         bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
0295         reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1);
0296         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
0297         rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
0298         rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
0299 
0300         /*
0301          * Enable synchronisation.
0302          */
0303         reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
0304         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
0305         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
0306     }
0307 
0308     if (flags & CONFIG_UPDATE_MAC)
0309         rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
0310                           conf->mac, sizeof(conf->mac));
0311 
0312     if (flags & CONFIG_UPDATE_BSSID)
0313         rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
0314                           conf->bssid, sizeof(conf->bssid));
0315 }
0316 
0317 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
0318                  struct rt2x00lib_erp *erp,
0319                  u32 changed)
0320 {
0321     int preamble_mask;
0322     u32 reg;
0323 
0324     /*
0325      * When short preamble is enabled, we should set bit 0x08
0326      */
0327     if (changed & BSS_CHANGED_ERP_PREAMBLE) {
0328         preamble_mask = erp->short_preamble << 3;
0329 
0330         reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1);
0331         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
0332         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
0333         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
0334         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
0335         rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
0336 
0337         reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2);
0338         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
0339         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
0340         rt2x00_set_field32(&reg, ARCSR2_LENGTH,
0341                    GET_DURATION(ACK_SIZE, 10));
0342         rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
0343 
0344         reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3);
0345         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
0346         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
0347         rt2x00_set_field32(&reg, ARCSR2_LENGTH,
0348                    GET_DURATION(ACK_SIZE, 20));
0349         rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
0350 
0351         reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4);
0352         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
0353         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
0354         rt2x00_set_field32(&reg, ARCSR2_LENGTH,
0355                    GET_DURATION(ACK_SIZE, 55));
0356         rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
0357 
0358         reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5);
0359         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
0360         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
0361         rt2x00_set_field32(&reg, ARCSR2_LENGTH,
0362                    GET_DURATION(ACK_SIZE, 110));
0363         rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
0364     }
0365 
0366     if (changed & BSS_CHANGED_BASIC_RATES)
0367         rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
0368 
0369     if (changed & BSS_CHANGED_ERP_SLOT) {
0370         reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
0371         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
0372         rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
0373 
0374         reg = rt2x00mmio_register_read(rt2x00dev, CSR18);
0375         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
0376         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
0377         rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
0378 
0379         reg = rt2x00mmio_register_read(rt2x00dev, CSR19);
0380         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
0381         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
0382         rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
0383     }
0384 
0385     if (changed & BSS_CHANGED_BEACON_INT) {
0386         reg = rt2x00mmio_register_read(rt2x00dev, CSR12);
0387         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
0388                    erp->beacon_int * 16);
0389         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
0390                    erp->beacon_int * 16);
0391         rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
0392     }
0393 
0394 }
0395 
0396 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
0397                  struct antenna_setup *ant)
0398 {
0399     u32 reg;
0400     u8 r14;
0401     u8 r2;
0402 
0403     /*
0404      * We should never come here because rt2x00lib is supposed
0405      * to catch this and send us the correct antenna explicitely.
0406      */
0407     BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
0408            ant->tx == ANTENNA_SW_DIVERSITY);
0409 
0410     reg = rt2x00mmio_register_read(rt2x00dev, BBPCSR1);
0411     r14 = rt2500pci_bbp_read(rt2x00dev, 14);
0412     r2 = rt2500pci_bbp_read(rt2x00dev, 2);
0413 
0414     /*
0415      * Configure the TX antenna.
0416      */
0417     switch (ant->tx) {
0418     case ANTENNA_A:
0419         rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
0420         rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
0421         rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
0422         break;
0423     case ANTENNA_B:
0424     default:
0425         rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
0426         rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
0427         rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
0428         break;
0429     }
0430 
0431     /*
0432      * Configure the RX antenna.
0433      */
0434     switch (ant->rx) {
0435     case ANTENNA_A:
0436         rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
0437         break;
0438     case ANTENNA_B:
0439     default:
0440         rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
0441         break;
0442     }
0443 
0444     /*
0445      * RT2525E and RT5222 need to flip TX I/Q
0446      */
0447     if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
0448         rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
0449         rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
0450         rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
0451 
0452         /*
0453          * RT2525E does not need RX I/Q Flip.
0454          */
0455         if (rt2x00_rf(rt2x00dev, RF2525E))
0456             rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
0457     } else {
0458         rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
0459         rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
0460     }
0461 
0462     rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg);
0463     rt2500pci_bbp_write(rt2x00dev, 14, r14);
0464     rt2500pci_bbp_write(rt2x00dev, 2, r2);
0465 }
0466 
0467 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
0468                      struct rf_channel *rf, const int txpower)
0469 {
0470     u8 r70;
0471 
0472     /*
0473      * Set TXpower.
0474      */
0475     rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
0476 
0477     /*
0478      * Switch on tuning bits.
0479      * For RT2523 devices we do not need to update the R1 register.
0480      */
0481     if (!rt2x00_rf(rt2x00dev, RF2523))
0482         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
0483     rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
0484 
0485     /*
0486      * For RT2525 we should first set the channel to half band higher.
0487      */
0488     if (rt2x00_rf(rt2x00dev, RF2525)) {
0489         static const u32 vals[] = {
0490             0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
0491             0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
0492             0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
0493             0x00080d2e, 0x00080d3a
0494         };
0495 
0496         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
0497         rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
0498         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
0499         if (rf->rf4)
0500             rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
0501     }
0502 
0503     rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
0504     rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
0505     rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
0506     if (rf->rf4)
0507         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
0508 
0509     /*
0510      * Channel 14 requires the Japan filter bit to be set.
0511      */
0512     r70 = 0x46;
0513     rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
0514     rt2500pci_bbp_write(rt2x00dev, 70, r70);
0515 
0516     msleep(1);
0517 
0518     /*
0519      * Switch off tuning bits.
0520      * For RT2523 devices we do not need to update the R1 register.
0521      */
0522     if (!rt2x00_rf(rt2x00dev, RF2523)) {
0523         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
0524         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
0525     }
0526 
0527     rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
0528     rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
0529 
0530     /*
0531      * Clear false CRC during channel switch.
0532      */
0533     rf->rf1 = rt2x00mmio_register_read(rt2x00dev, CNT0);
0534 }
0535 
0536 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
0537                      const int txpower)
0538 {
0539     u32 rf3;
0540 
0541     rf3 = rt2x00_rf_read(rt2x00dev, 3);
0542     rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
0543     rt2500pci_rf_write(rt2x00dev, 3, rf3);
0544 }
0545 
0546 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
0547                      struct rt2x00lib_conf *libconf)
0548 {
0549     u32 reg;
0550 
0551     reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
0552     rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
0553                libconf->conf->long_frame_max_tx_count);
0554     rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
0555                libconf->conf->short_frame_max_tx_count);
0556     rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
0557 }
0558 
0559 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
0560                 struct rt2x00lib_conf *libconf)
0561 {
0562     enum dev_state state =
0563         (libconf->conf->flags & IEEE80211_CONF_PS) ?
0564         STATE_SLEEP : STATE_AWAKE;
0565     u32 reg;
0566 
0567     if (state == STATE_SLEEP) {
0568         reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
0569         rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
0570                    (rt2x00dev->beacon_int - 20) * 16);
0571         rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
0572                    libconf->conf->listen_interval - 1);
0573 
0574         /* We must first disable autowake before it can be enabled */
0575         rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
0576         rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
0577 
0578         rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
0579         rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
0580     } else {
0581         reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
0582         rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
0583         rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
0584     }
0585 
0586     rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
0587 }
0588 
0589 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
0590                  struct rt2x00lib_conf *libconf,
0591                  const unsigned int flags)
0592 {
0593     if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
0594         rt2500pci_config_channel(rt2x00dev, &libconf->rf,
0595                      libconf->conf->power_level);
0596     if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
0597         !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
0598         rt2500pci_config_txpower(rt2x00dev,
0599                      libconf->conf->power_level);
0600     if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
0601         rt2500pci_config_retry_limit(rt2x00dev, libconf);
0602     if (flags & IEEE80211_CONF_CHANGE_PS)
0603         rt2500pci_config_ps(rt2x00dev, libconf);
0604 }
0605 
0606 /*
0607  * Link tuning
0608  */
0609 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
0610                  struct link_qual *qual)
0611 {
0612     u32 reg;
0613 
0614     /*
0615      * Update FCS error count from register.
0616      */
0617     reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
0618     qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
0619 
0620     /*
0621      * Update False CCA count from register.
0622      */
0623     reg = rt2x00mmio_register_read(rt2x00dev, CNT3);
0624     qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
0625 }
0626 
0627 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
0628                      struct link_qual *qual, u8 vgc_level)
0629 {
0630     if (qual->vgc_level_reg != vgc_level) {
0631         rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
0632         qual->vgc_level = vgc_level;
0633         qual->vgc_level_reg = vgc_level;
0634     }
0635 }
0636 
0637 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
0638                   struct link_qual *qual)
0639 {
0640     rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
0641 }
0642 
0643 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
0644                  struct link_qual *qual, const u32 count)
0645 {
0646     /*
0647      * To prevent collisions with MAC ASIC on chipsets
0648      * up to version C the link tuning should halt after 20
0649      * seconds while being associated.
0650      */
0651     if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
0652         rt2x00dev->intf_associated && count > 20)
0653         return;
0654 
0655     /*
0656      * Chipset versions C and lower should directly continue
0657      * to the dynamic CCA tuning. Chipset version D and higher
0658      * should go straight to dynamic CCA tuning when they
0659      * are not associated.
0660      */
0661     if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
0662         !rt2x00dev->intf_associated)
0663         goto dynamic_cca_tune;
0664 
0665     /*
0666      * A too low RSSI will cause too much false CCA which will
0667      * then corrupt the R17 tuning. To remidy this the tuning should
0668      * be stopped (While making sure the R17 value will not exceed limits)
0669      */
0670     if (qual->rssi < -80 && count > 20) {
0671         if (qual->vgc_level_reg >= 0x41)
0672             rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
0673         return;
0674     }
0675 
0676     /*
0677      * Special big-R17 for short distance
0678      */
0679     if (qual->rssi >= -58) {
0680         rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
0681         return;
0682     }
0683 
0684     /*
0685      * Special mid-R17 for middle distance
0686      */
0687     if (qual->rssi >= -74) {
0688         rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
0689         return;
0690     }
0691 
0692     /*
0693      * Leave short or middle distance condition, restore r17
0694      * to the dynamic tuning range.
0695      */
0696     if (qual->vgc_level_reg >= 0x41) {
0697         rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
0698         return;
0699     }
0700 
0701 dynamic_cca_tune:
0702 
0703     /*
0704      * R17 is inside the dynamic tuning range,
0705      * start tuning the link based on the false cca counter.
0706      */
0707     if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40)
0708         rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
0709     else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32)
0710         rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
0711 }
0712 
0713 /*
0714  * Queue handlers.
0715  */
0716 static void rt2500pci_start_queue(struct data_queue *queue)
0717 {
0718     struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
0719     u32 reg;
0720 
0721     switch (queue->qid) {
0722     case QID_RX:
0723         reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
0724         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
0725         rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
0726         break;
0727     case QID_BEACON:
0728         reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
0729         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
0730         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
0731         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
0732         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
0733         break;
0734     default:
0735         break;
0736     }
0737 }
0738 
0739 static void rt2500pci_kick_queue(struct data_queue *queue)
0740 {
0741     struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
0742     u32 reg;
0743 
0744     switch (queue->qid) {
0745     case QID_AC_VO:
0746         reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
0747         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
0748         rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
0749         break;
0750     case QID_AC_VI:
0751         reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
0752         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
0753         rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
0754         break;
0755     case QID_ATIM:
0756         reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
0757         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
0758         rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
0759         break;
0760     default:
0761         break;
0762     }
0763 }
0764 
0765 static void rt2500pci_stop_queue(struct data_queue *queue)
0766 {
0767     struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
0768     u32 reg;
0769 
0770     switch (queue->qid) {
0771     case QID_AC_VO:
0772     case QID_AC_VI:
0773     case QID_ATIM:
0774         reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
0775         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
0776         rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
0777         break;
0778     case QID_RX:
0779         reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
0780         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
0781         rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
0782         break;
0783     case QID_BEACON:
0784         reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
0785         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
0786         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
0787         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
0788         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
0789 
0790         /*
0791          * Wait for possibly running tbtt tasklets.
0792          */
0793         tasklet_kill(&rt2x00dev->tbtt_tasklet);
0794         break;
0795     default:
0796         break;
0797     }
0798 }
0799 
0800 /*
0801  * Initialization functions.
0802  */
0803 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
0804 {
0805     struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
0806     u32 word;
0807 
0808     if (entry->queue->qid == QID_RX) {
0809         word = rt2x00_desc_read(entry_priv->desc, 0);
0810 
0811         return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
0812     } else {
0813         word = rt2x00_desc_read(entry_priv->desc, 0);
0814 
0815         return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
0816                 rt2x00_get_field32(word, TXD_W0_VALID));
0817     }
0818 }
0819 
0820 static void rt2500pci_clear_entry(struct queue_entry *entry)
0821 {
0822     struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
0823     struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
0824     u32 word;
0825 
0826     if (entry->queue->qid == QID_RX) {
0827         word = rt2x00_desc_read(entry_priv->desc, 1);
0828         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
0829         rt2x00_desc_write(entry_priv->desc, 1, word);
0830 
0831         word = rt2x00_desc_read(entry_priv->desc, 0);
0832         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
0833         rt2x00_desc_write(entry_priv->desc, 0, word);
0834     } else {
0835         word = rt2x00_desc_read(entry_priv->desc, 0);
0836         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
0837         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
0838         rt2x00_desc_write(entry_priv->desc, 0, word);
0839     }
0840 }
0841 
0842 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
0843 {
0844     struct queue_entry_priv_mmio *entry_priv;
0845     u32 reg;
0846 
0847     /*
0848      * Initialize registers.
0849      */
0850     reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2);
0851     rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
0852     rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
0853     rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
0854     rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
0855     rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
0856 
0857     entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
0858     reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3);
0859     rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
0860                entry_priv->desc_dma);
0861     rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
0862 
0863     entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
0864     reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5);
0865     rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
0866                entry_priv->desc_dma);
0867     rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
0868 
0869     entry_priv = rt2x00dev->atim->entries[0].priv_data;
0870     reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4);
0871     rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
0872                entry_priv->desc_dma);
0873     rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
0874 
0875     entry_priv = rt2x00dev->bcn->entries[0].priv_data;
0876     reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6);
0877     rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
0878                entry_priv->desc_dma);
0879     rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
0880 
0881     reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1);
0882     rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
0883     rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
0884     rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
0885 
0886     entry_priv = rt2x00dev->rx->entries[0].priv_data;
0887     reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2);
0888     rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
0889                entry_priv->desc_dma);
0890     rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
0891 
0892     return 0;
0893 }
0894 
0895 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
0896 {
0897     u32 reg;
0898 
0899     rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
0900     rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
0901     rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00020002);
0902     rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
0903 
0904     reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR);
0905     rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
0906     rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
0907     rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
0908     rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
0909 
0910     reg = rt2x00mmio_register_read(rt2x00dev, CSR9);
0911     rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
0912                rt2x00dev->rx->data_size / 128);
0913     rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
0914 
0915     /*
0916      * Always use CWmin and CWmax set in descriptor.
0917      */
0918     reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
0919     rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
0920     rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
0921 
0922     reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
0923     rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
0924     rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
0925     rt2x00_set_field32(&reg, CSR14_TBCN, 0);
0926     rt2x00_set_field32(&reg, CSR14_TCFP, 0);
0927     rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
0928     rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
0929     rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
0930     rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
0931     rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
0932 
0933     rt2x00mmio_register_write(rt2x00dev, CNT3, 0);
0934 
0935     reg = rt2x00mmio_register_read(rt2x00dev, TXCSR8);
0936     rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
0937     rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
0938     rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
0939     rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
0940     rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
0941     rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
0942     rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
0943     rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
0944     rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg);
0945 
0946     reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR0);
0947     rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
0948     rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
0949     rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
0950     rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
0951     rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg);
0952 
0953     reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR1);
0954     rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
0955     rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
0956     rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
0957     rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
0958     rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg);
0959 
0960     reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR2);
0961     rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
0962     rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
0963     rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
0964     rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
0965     rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg);
0966 
0967     reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3);
0968     rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
0969     rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
0970     rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
0971     rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
0972     rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
0973     rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
0974     rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
0975     rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
0976     rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
0977 
0978     reg = rt2x00mmio_register_read(rt2x00dev, PCICSR);
0979     rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
0980     rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
0981     rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
0982     rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
0983     rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
0984     rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
0985     rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
0986     rt2x00mmio_register_write(rt2x00dev, PCICSR, reg);
0987 
0988     rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
0989 
0990     rt2x00mmio_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
0991     rt2x00mmio_register_write(rt2x00dev, TESTCSR, 0x000000f0);
0992 
0993     if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
0994         return -EBUSY;
0995 
0996     rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00213223);
0997     rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
0998 
0999     reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2);
1000     rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
1001     rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
1002 
1003     reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR);
1004     rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
1005     rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
1006     rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
1007     rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
1008     rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
1009     rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
1010     rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
1011 
1012     rt2x00mmio_register_write(rt2x00dev, BBPCSR1, 0x82188200);
1013 
1014     rt2x00mmio_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
1015 
1016     reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
1017     rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
1018     rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
1019     rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
1020     rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
1021 
1022     reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
1023     rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
1024     rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
1025     rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
1026 
1027     /*
1028      * We must clear the FCS and FIFO error count.
1029      * These registers are cleared on read,
1030      * so we may pass a useless variable to store the value.
1031      */
1032     reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
1033     reg = rt2x00mmio_register_read(rt2x00dev, CNT4);
1034 
1035     return 0;
1036 }
1037 
1038 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1039 {
1040     unsigned int i;
1041     u8 value;
1042 
1043     for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1044         value = rt2500pci_bbp_read(rt2x00dev, 0);
1045         if ((value != 0xff) && (value != 0x00))
1046             return 0;
1047         udelay(REGISTER_BUSY_DELAY);
1048     }
1049 
1050     rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
1051     return -EACCES;
1052 }
1053 
1054 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1055 {
1056     unsigned int i;
1057     u16 eeprom;
1058     u8 reg_id;
1059     u8 value;
1060 
1061     if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
1062         return -EACCES;
1063 
1064     rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1065     rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1066     rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1067     rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1068     rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1069     rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1070     rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1071     rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1072     rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1073     rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1074     rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1075     rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1076     rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1077     rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1078     rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1079     rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1080     rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1081     rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1082     rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1083     rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1084     rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1085     rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1086     rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1087     rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1088     rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1089     rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1090     rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1091     rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1092     rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1093     rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1094 
1095     for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1096         eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i);
1097 
1098         if (eeprom != 0xffff && eeprom != 0x0000) {
1099             reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1100             value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1101             rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1102         }
1103     }
1104 
1105     return 0;
1106 }
1107 
1108 /*
1109  * Device state switch handlers.
1110  */
1111 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1112                  enum dev_state state)
1113 {
1114     int mask = (state == STATE_RADIO_IRQ_OFF);
1115     u32 reg;
1116     unsigned long flags;
1117 
1118     /*
1119      * When interrupts are being enabled, the interrupt registers
1120      * should clear the register to assure a clean state.
1121      */
1122     if (state == STATE_RADIO_IRQ_ON) {
1123         reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
1124         rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1125     }
1126 
1127     /*
1128      * Only toggle the interrupts bits we are going to use.
1129      * Non-checked interrupt bits are disabled by default.
1130      */
1131     spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1132 
1133     reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1134     rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1135     rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1136     rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1137     rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1138     rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1139     rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1140 
1141     spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1142 
1143     if (state == STATE_RADIO_IRQ_OFF) {
1144         /*
1145          * Ensure that all tasklets are finished.
1146          */
1147         tasklet_kill(&rt2x00dev->txstatus_tasklet);
1148         tasklet_kill(&rt2x00dev->rxdone_tasklet);
1149         tasklet_kill(&rt2x00dev->tbtt_tasklet);
1150     }
1151 }
1152 
1153 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1154 {
1155     /*
1156      * Initialize all registers.
1157      */
1158     if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1159              rt2500pci_init_registers(rt2x00dev) ||
1160              rt2500pci_init_bbp(rt2x00dev)))
1161         return -EIO;
1162 
1163     return 0;
1164 }
1165 
1166 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1167 {
1168     /*
1169      * Disable power
1170      */
1171     rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
1172 }
1173 
1174 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1175                    enum dev_state state)
1176 {
1177     u32 reg, reg2;
1178     unsigned int i;
1179     char put_to_sleep;
1180     char bbp_state;
1181     char rf_state;
1182 
1183     put_to_sleep = (state != STATE_AWAKE);
1184 
1185     reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1186     rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1187     rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1188     rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1189     rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1190     rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1191 
1192     /*
1193      * Device is not guaranteed to be in the requested state yet.
1194      * We must wait until the register indicates that the
1195      * device has entered the correct state.
1196      */
1197     for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1198         reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1199         bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1200         rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1201         if (bbp_state == state && rf_state == state)
1202             return 0;
1203         rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1204         msleep(10);
1205     }
1206 
1207     return -EBUSY;
1208 }
1209 
1210 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1211                       enum dev_state state)
1212 {
1213     int retval = 0;
1214 
1215     switch (state) {
1216     case STATE_RADIO_ON:
1217         retval = rt2500pci_enable_radio(rt2x00dev);
1218         break;
1219     case STATE_RADIO_OFF:
1220         rt2500pci_disable_radio(rt2x00dev);
1221         break;
1222     case STATE_RADIO_IRQ_ON:
1223     case STATE_RADIO_IRQ_OFF:
1224         rt2500pci_toggle_irq(rt2x00dev, state);
1225         break;
1226     case STATE_DEEP_SLEEP:
1227     case STATE_SLEEP:
1228     case STATE_STANDBY:
1229     case STATE_AWAKE:
1230         retval = rt2500pci_set_state(rt2x00dev, state);
1231         break;
1232     default:
1233         retval = -ENOTSUPP;
1234         break;
1235     }
1236 
1237     if (unlikely(retval))
1238         rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1239                state, retval);
1240 
1241     return retval;
1242 }
1243 
1244 /*
1245  * TX descriptor initialization
1246  */
1247 static void rt2500pci_write_tx_desc(struct queue_entry *entry,
1248                     struct txentry_desc *txdesc)
1249 {
1250     struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1251     struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1252     __le32 *txd = entry_priv->desc;
1253     u32 word;
1254 
1255     /*
1256      * Start writing the descriptor words.
1257      */
1258     word = rt2x00_desc_read(txd, 1);
1259     rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1260     rt2x00_desc_write(txd, 1, word);
1261 
1262     word = rt2x00_desc_read(txd, 2);
1263     rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1264     rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);
1265     rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);
1266     rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);
1267     rt2x00_desc_write(txd, 2, word);
1268 
1269     word = rt2x00_desc_read(txd, 3);
1270     rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1271     rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1272     rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW,
1273                txdesc->u.plcp.length_low);
1274     rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH,
1275                txdesc->u.plcp.length_high);
1276     rt2x00_desc_write(txd, 3, word);
1277 
1278     word = rt2x00_desc_read(txd, 10);
1279     rt2x00_set_field32(&word, TXD_W10_RTS,
1280                test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1281     rt2x00_desc_write(txd, 10, word);
1282 
1283     /*
1284      * Writing TXD word 0 must the last to prevent a race condition with
1285      * the device, whereby the device may take hold of the TXD before we
1286      * finished updating it.
1287      */
1288     word = rt2x00_desc_read(txd, 0);
1289     rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1290     rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1291     rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1292                test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1293     rt2x00_set_field32(&word, TXD_W0_ACK,
1294                test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1295     rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1296                test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1297     rt2x00_set_field32(&word, TXD_W0_OFDM,
1298                (txdesc->rate_mode == RATE_MODE_OFDM));
1299     rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1300     rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1301     rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1302                test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1303     rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1304     rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1305     rt2x00_desc_write(txd, 0, word);
1306 
1307     /*
1308      * Register descriptor details in skb frame descriptor.
1309      */
1310     skbdesc->desc = txd;
1311     skbdesc->desc_len = TXD_DESC_SIZE;
1312 }
1313 
1314 /*
1315  * TX data initialization
1316  */
1317 static void rt2500pci_write_beacon(struct queue_entry *entry,
1318                    struct txentry_desc *txdesc)
1319 {
1320     struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1321     u32 reg;
1322 
1323     /*
1324      * Disable beaconing while we are reloading the beacon data,
1325      * otherwise we might be sending out invalid data.
1326      */
1327     reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
1328     rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1329     rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1330 
1331     if (rt2x00queue_map_txskb(entry)) {
1332         rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
1333         goto out;
1334     }
1335 
1336     /*
1337      * Write the TX descriptor for the beacon.
1338      */
1339     rt2500pci_write_tx_desc(entry, txdesc);
1340 
1341     /*
1342      * Dump beacon to userspace through debugfs.
1343      */
1344     rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1345 out:
1346     /*
1347      * Enable beaconing again.
1348      */
1349     rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1350     rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1351 }
1352 
1353 /*
1354  * RX control handlers
1355  */
1356 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1357                   struct rxdone_entry_desc *rxdesc)
1358 {
1359     struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1360     u32 word0;
1361     u32 word2;
1362 
1363     word0 = rt2x00_desc_read(entry_priv->desc, 0);
1364     word2 = rt2x00_desc_read(entry_priv->desc, 2);
1365 
1366     if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1367         rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1368     if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1369         rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1370 
1371     /*
1372      * Obtain the status about this packet.
1373      * When frame was received with an OFDM bitrate,
1374      * the signal is the PLCP value. If it was received with
1375      * a CCK bitrate the signal is the rate in 100kbit/s.
1376      */
1377     rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1378     rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1379         entry->queue->rt2x00dev->rssi_offset;
1380     rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1381 
1382     if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1383         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1384     else
1385         rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1386     if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1387         rxdesc->dev_flags |= RXDONE_MY_BSS;
1388 }
1389 
1390 /*
1391  * Interrupt functions.
1392  */
1393 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1394                  const enum data_queue_qid queue_idx)
1395 {
1396     struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1397     struct queue_entry_priv_mmio *entry_priv;
1398     struct queue_entry *entry;
1399     struct txdone_entry_desc txdesc;
1400     u32 word;
1401 
1402     while (!rt2x00queue_empty(queue)) {
1403         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1404         entry_priv = entry->priv_data;
1405         word = rt2x00_desc_read(entry_priv->desc, 0);
1406 
1407         if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1408             !rt2x00_get_field32(word, TXD_W0_VALID))
1409             break;
1410 
1411         /*
1412          * Obtain the status about this packet.
1413          */
1414         txdesc.flags = 0;
1415         switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1416         case 0: /* Success */
1417         case 1: /* Success with retry */
1418             __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1419             break;
1420         case 2: /* Failure, excessive retries */
1421             __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1422             fallthrough;    /* this is a failed frame! */
1423         default: /* Failure */
1424             __set_bit(TXDONE_FAILURE, &txdesc.flags);
1425         }
1426         txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1427 
1428         rt2x00lib_txdone(entry, &txdesc);
1429     }
1430 }
1431 
1432 static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1433                           struct rt2x00_field32 irq_field)
1434 {
1435     u32 reg;
1436 
1437     /*
1438      * Enable a single interrupt. The interrupt mask register
1439      * access needs locking.
1440      */
1441     spin_lock_irq(&rt2x00dev->irqmask_lock);
1442 
1443     reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1444     rt2x00_set_field32(&reg, irq_field, 0);
1445     rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1446 
1447     spin_unlock_irq(&rt2x00dev->irqmask_lock);
1448 }
1449 
1450 static void rt2500pci_txstatus_tasklet(struct tasklet_struct *t)
1451 {
1452     struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1453                             txstatus_tasklet);
1454     u32 reg;
1455 
1456     /*
1457      * Handle all tx queues.
1458      */
1459     rt2500pci_txdone(rt2x00dev, QID_ATIM);
1460     rt2500pci_txdone(rt2x00dev, QID_AC_VO);
1461     rt2500pci_txdone(rt2x00dev, QID_AC_VI);
1462 
1463     /*
1464      * Enable all TXDONE interrupts again.
1465      */
1466     if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1467         spin_lock_irq(&rt2x00dev->irqmask_lock);
1468 
1469         reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1470         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1471         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1472         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1473         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1474 
1475         spin_unlock_irq(&rt2x00dev->irqmask_lock);
1476     }
1477 }
1478 
1479 static void rt2500pci_tbtt_tasklet(struct tasklet_struct *t)
1480 {
1481     struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet);
1482     rt2x00lib_beacondone(rt2x00dev);
1483     if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1484         rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1485 }
1486 
1487 static void rt2500pci_rxdone_tasklet(struct tasklet_struct *t)
1488 {
1489     struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1490                             rxdone_tasklet);
1491     if (rt2x00mmio_rxdone(rt2x00dev))
1492         tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1493     else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1494         rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1495 }
1496 
1497 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1498 {
1499     struct rt2x00_dev *rt2x00dev = dev_instance;
1500     u32 reg, mask;
1501 
1502     /*
1503      * Get the interrupt sources & saved to local variable.
1504      * Write register value back to clear pending interrupts.
1505      */
1506     reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
1507     rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1508 
1509     if (!reg)
1510         return IRQ_NONE;
1511 
1512     if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1513         return IRQ_HANDLED;
1514 
1515     mask = reg;
1516 
1517     /*
1518      * Schedule tasklets for interrupt handling.
1519      */
1520     if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1521         tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1522 
1523     if (rt2x00_get_field32(reg, CSR7_RXDONE))
1524         tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1525 
1526     if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1527         rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1528         rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1529         tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1530         /*
1531          * Mask out all txdone interrupts.
1532          */
1533         rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1534         rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1535         rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1536     }
1537 
1538     /*
1539      * Disable all interrupts for which a tasklet was scheduled right now,
1540      * the tasklet will reenable the appropriate interrupts.
1541      */
1542     spin_lock(&rt2x00dev->irqmask_lock);
1543 
1544     reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1545     reg |= mask;
1546     rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1547 
1548     spin_unlock(&rt2x00dev->irqmask_lock);
1549 
1550     return IRQ_HANDLED;
1551 }
1552 
1553 /*
1554  * Device probe functions.
1555  */
1556 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1557 {
1558     struct eeprom_93cx6 eeprom;
1559     u32 reg;
1560     u16 word;
1561     u8 *mac;
1562 
1563     reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
1564 
1565     eeprom.data = rt2x00dev;
1566     eeprom.register_read = rt2500pci_eepromregister_read;
1567     eeprom.register_write = rt2500pci_eepromregister_write;
1568     eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1569         PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1570     eeprom.reg_data_in = 0;
1571     eeprom.reg_data_out = 0;
1572     eeprom.reg_data_clock = 0;
1573     eeprom.reg_chip_select = 0;
1574 
1575     eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1576                    EEPROM_SIZE / sizeof(u16));
1577 
1578     /*
1579      * Start validation of the data that has been read.
1580      */
1581     mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1582     rt2x00lib_set_mac_address(rt2x00dev, mac);
1583 
1584     word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1585     if (word == 0xffff) {
1586         rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1587         rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1588                    ANTENNA_SW_DIVERSITY);
1589         rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1590                    ANTENNA_SW_DIVERSITY);
1591         rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1592                    LED_MODE_DEFAULT);
1593         rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1594         rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1595         rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1596         rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1597         rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
1598     }
1599 
1600     word = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC);
1601     if (word == 0xffff) {
1602         rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1603         rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1604         rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1605         rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1606         rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
1607     }
1608 
1609     word = rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET);
1610     if (word == 0xffff) {
1611         rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1612                    DEFAULT_RSSI_OFFSET);
1613         rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1614         rt2x00_eeprom_dbg(rt2x00dev, "Calibrate offset: 0x%04x\n",
1615                   word);
1616     }
1617 
1618     return 0;
1619 }
1620 
1621 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1622 {
1623     u32 reg;
1624     u16 value;
1625     u16 eeprom;
1626 
1627     /*
1628      * Read EEPROM word for configuration.
1629      */
1630     eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1631 
1632     /*
1633      * Identify RF chipset.
1634      */
1635     value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1636     reg = rt2x00mmio_register_read(rt2x00dev, CSR0);
1637     rt2x00_set_chip(rt2x00dev, RT2560, value,
1638             rt2x00_get_field32(reg, CSR0_REVISION));
1639 
1640     if (!rt2x00_rf(rt2x00dev, RF2522) &&
1641         !rt2x00_rf(rt2x00dev, RF2523) &&
1642         !rt2x00_rf(rt2x00dev, RF2524) &&
1643         !rt2x00_rf(rt2x00dev, RF2525) &&
1644         !rt2x00_rf(rt2x00dev, RF2525E) &&
1645         !rt2x00_rf(rt2x00dev, RF5222)) {
1646         rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1647         return -ENODEV;
1648     }
1649 
1650     /*
1651      * Identify default antenna configuration.
1652      */
1653     rt2x00dev->default_ant.tx =
1654         rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1655     rt2x00dev->default_ant.rx =
1656         rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1657 
1658     /*
1659      * Store led mode, for correct led behaviour.
1660      */
1661 #ifdef CONFIG_RT2X00_LIB_LEDS
1662     value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1663 
1664     rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1665     if (value == LED_MODE_TXRX_ACTIVITY ||
1666         value == LED_MODE_DEFAULT ||
1667         value == LED_MODE_ASUS)
1668         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1669                    LED_TYPE_ACTIVITY);
1670 #endif /* CONFIG_RT2X00_LIB_LEDS */
1671 
1672     /*
1673      * Detect if this device has an hardware controlled radio.
1674      */
1675     if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) {
1676         __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1677         /*
1678          * On this device RFKILL initialized during probe does not work.
1679          */
1680         __set_bit(REQUIRE_DELAYED_RFKILL, &rt2x00dev->cap_flags);
1681     }
1682 
1683     /*
1684      * Check if the BBP tuning should be enabled.
1685      */
1686     eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC);
1687     if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1688         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1689 
1690     /*
1691      * Read the RSSI <-> dBm offset information.
1692      */
1693     eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET);
1694     rt2x00dev->rssi_offset =
1695         rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1696 
1697     return 0;
1698 }
1699 
1700 /*
1701  * RF value list for RF2522
1702  * Supports: 2.4 GHz
1703  */
1704 static const struct rf_channel rf_vals_bg_2522[] = {
1705     { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1706     { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1707     { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1708     { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1709     { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1710     { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1711     { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1712     { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1713     { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1714     { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1715     { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1716     { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1717     { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1718     { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1719 };
1720 
1721 /*
1722  * RF value list for RF2523
1723  * Supports: 2.4 GHz
1724  */
1725 static const struct rf_channel rf_vals_bg_2523[] = {
1726     { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1727     { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1728     { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1729     { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1730     { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1731     { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1732     { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1733     { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1734     { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1735     { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1736     { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1737     { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1738     { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1739     { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1740 };
1741 
1742 /*
1743  * RF value list for RF2524
1744  * Supports: 2.4 GHz
1745  */
1746 static const struct rf_channel rf_vals_bg_2524[] = {
1747     { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1748     { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1749     { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1750     { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1751     { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1752     { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1753     { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1754     { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1755     { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1756     { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1757     { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1758     { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1759     { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1760     { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1761 };
1762 
1763 /*
1764  * RF value list for RF2525
1765  * Supports: 2.4 GHz
1766  */
1767 static const struct rf_channel rf_vals_bg_2525[] = {
1768     { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1769     { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1770     { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1771     { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1772     { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1773     { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1774     { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1775     { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1776     { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1777     { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1778     { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1779     { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1780     { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1781     { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1782 };
1783 
1784 /*
1785  * RF value list for RF2525e
1786  * Supports: 2.4 GHz
1787  */
1788 static const struct rf_channel rf_vals_bg_2525e[] = {
1789     { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1790     { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1791     { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1792     { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1793     { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1794     { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1795     { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1796     { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1797     { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1798     { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1799     { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1800     { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1801     { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1802     { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1803 };
1804 
1805 /*
1806  * RF value list for RF5222
1807  * Supports: 2.4 GHz & 5.2 GHz
1808  */
1809 static const struct rf_channel rf_vals_5222[] = {
1810     { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1811     { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1812     { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1813     { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1814     { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1815     { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1816     { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1817     { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1818     { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1819     { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1820     { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1821     { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1822     { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1823     { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1824 
1825     /* 802.11 UNI / HyperLan 2 */
1826     { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1827     { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1828     { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1829     { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1830     { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1831     { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1832     { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1833     { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1834 
1835     /* 802.11 HyperLan 2 */
1836     { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1837     { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1838     { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1839     { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1840     { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1841     { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1842     { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1843     { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1844     { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1845     { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1846 
1847     /* 802.11 UNII */
1848     { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1849     { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1850     { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1851     { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1852     { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1853 };
1854 
1855 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1856 {
1857     struct hw_mode_spec *spec = &rt2x00dev->spec;
1858     struct channel_info *info;
1859     char *tx_power;
1860     unsigned int i;
1861 
1862     /*
1863      * Initialize all hw fields.
1864      */
1865     ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
1866     ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
1867     ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
1868     ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
1869 
1870     SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1871     SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1872                 rt2x00_eeprom_addr(rt2x00dev,
1873                            EEPROM_MAC_ADDR_0));
1874 
1875     /*
1876      * Disable powersaving as default.
1877      */
1878     rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
1879 
1880     /*
1881      * Initialize hw_mode information.
1882      */
1883     spec->supported_bands = SUPPORT_BAND_2GHZ;
1884     spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1885 
1886     if (rt2x00_rf(rt2x00dev, RF2522)) {
1887         spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1888         spec->channels = rf_vals_bg_2522;
1889     } else if (rt2x00_rf(rt2x00dev, RF2523)) {
1890         spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1891         spec->channels = rf_vals_bg_2523;
1892     } else if (rt2x00_rf(rt2x00dev, RF2524)) {
1893         spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1894         spec->channels = rf_vals_bg_2524;
1895     } else if (rt2x00_rf(rt2x00dev, RF2525)) {
1896         spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1897         spec->channels = rf_vals_bg_2525;
1898     } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
1899         spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1900         spec->channels = rf_vals_bg_2525e;
1901     } else if (rt2x00_rf(rt2x00dev, RF5222)) {
1902         spec->supported_bands |= SUPPORT_BAND_5GHZ;
1903         spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1904         spec->channels = rf_vals_5222;
1905     }
1906 
1907     /*
1908      * Create channel information array
1909      */
1910     info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1911     if (!info)
1912         return -ENOMEM;
1913 
1914     spec->channels_info = info;
1915 
1916     tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1917     for (i = 0; i < 14; i++) {
1918         info[i].max_power = MAX_TXPOWER;
1919         info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1920     }
1921 
1922     if (spec->num_channels > 14) {
1923         for (i = 14; i < spec->num_channels; i++) {
1924             info[i].max_power = MAX_TXPOWER;
1925             info[i].default_power1 = DEFAULT_TXPOWER;
1926         }
1927     }
1928 
1929     return 0;
1930 }
1931 
1932 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1933 {
1934     int retval;
1935     u32 reg;
1936 
1937     /*
1938      * Allocate eeprom data.
1939      */
1940     retval = rt2500pci_validate_eeprom(rt2x00dev);
1941     if (retval)
1942         return retval;
1943 
1944     retval = rt2500pci_init_eeprom(rt2x00dev);
1945     if (retval)
1946         return retval;
1947 
1948     /*
1949      * Enable rfkill polling by setting GPIO direction of the
1950      * rfkill switch GPIO pin correctly.
1951      */
1952     reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
1953     rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
1954     rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1955 
1956     /*
1957      * Initialize hw specifications.
1958      */
1959     retval = rt2500pci_probe_hw_mode(rt2x00dev);
1960     if (retval)
1961         return retval;
1962 
1963     /*
1964      * This device requires the atim queue and DMA-mapped skbs.
1965      */
1966     __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1967     __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1968     __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1969 
1970     /*
1971      * Set the rssi offset.
1972      */
1973     rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1974 
1975     return 0;
1976 }
1977 
1978 /*
1979  * IEEE80211 stack callback functions.
1980  */
1981 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw,
1982                  struct ieee80211_vif *vif)
1983 {
1984     struct rt2x00_dev *rt2x00dev = hw->priv;
1985     u64 tsf;
1986     u32 reg;
1987 
1988     reg = rt2x00mmio_register_read(rt2x00dev, CSR17);
1989     tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1990     reg = rt2x00mmio_register_read(rt2x00dev, CSR16);
1991     tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1992 
1993     return tsf;
1994 }
1995 
1996 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1997 {
1998     struct rt2x00_dev *rt2x00dev = hw->priv;
1999     u32 reg;
2000 
2001     reg = rt2x00mmio_register_read(rt2x00dev, CSR15);
2002     return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
2003 }
2004 
2005 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
2006     .tx         = rt2x00mac_tx,
2007     .start          = rt2x00mac_start,
2008     .stop           = rt2x00mac_stop,
2009     .add_interface      = rt2x00mac_add_interface,
2010     .remove_interface   = rt2x00mac_remove_interface,
2011     .config         = rt2x00mac_config,
2012     .configure_filter   = rt2x00mac_configure_filter,
2013     .sw_scan_start      = rt2x00mac_sw_scan_start,
2014     .sw_scan_complete   = rt2x00mac_sw_scan_complete,
2015     .get_stats      = rt2x00mac_get_stats,
2016     .bss_info_changed   = rt2x00mac_bss_info_changed,
2017     .conf_tx        = rt2x00mac_conf_tx,
2018     .get_tsf        = rt2500pci_get_tsf,
2019     .tx_last_beacon     = rt2500pci_tx_last_beacon,
2020     .rfkill_poll        = rt2x00mac_rfkill_poll,
2021     .flush          = rt2x00mac_flush,
2022     .set_antenna        = rt2x00mac_set_antenna,
2023     .get_antenna        = rt2x00mac_get_antenna,
2024     .get_ringparam      = rt2x00mac_get_ringparam,
2025     .tx_frames_pending  = rt2x00mac_tx_frames_pending,
2026 };
2027 
2028 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
2029     .irq_handler        = rt2500pci_interrupt,
2030     .txstatus_tasklet   = rt2500pci_txstatus_tasklet,
2031     .tbtt_tasklet       = rt2500pci_tbtt_tasklet,
2032     .rxdone_tasklet     = rt2500pci_rxdone_tasklet,
2033     .probe_hw       = rt2500pci_probe_hw,
2034     .initialize     = rt2x00mmio_initialize,
2035     .uninitialize       = rt2x00mmio_uninitialize,
2036     .get_entry_state    = rt2500pci_get_entry_state,
2037     .clear_entry        = rt2500pci_clear_entry,
2038     .set_device_state   = rt2500pci_set_device_state,
2039     .rfkill_poll        = rt2500pci_rfkill_poll,
2040     .link_stats     = rt2500pci_link_stats,
2041     .reset_tuner        = rt2500pci_reset_tuner,
2042     .link_tuner     = rt2500pci_link_tuner,
2043     .start_queue        = rt2500pci_start_queue,
2044     .kick_queue     = rt2500pci_kick_queue,
2045     .stop_queue     = rt2500pci_stop_queue,
2046     .flush_queue        = rt2x00mmio_flush_queue,
2047     .write_tx_desc      = rt2500pci_write_tx_desc,
2048     .write_beacon       = rt2500pci_write_beacon,
2049     .fill_rxdone        = rt2500pci_fill_rxdone,
2050     .config_filter      = rt2500pci_config_filter,
2051     .config_intf        = rt2500pci_config_intf,
2052     .config_erp     = rt2500pci_config_erp,
2053     .config_ant     = rt2500pci_config_ant,
2054     .config         = rt2500pci_config,
2055 };
2056 
2057 static void rt2500pci_queue_init(struct data_queue *queue)
2058 {
2059     switch (queue->qid) {
2060     case QID_RX:
2061         queue->limit = 32;
2062         queue->data_size = DATA_FRAME_SIZE;
2063         queue->desc_size = RXD_DESC_SIZE;
2064         queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2065         break;
2066 
2067     case QID_AC_VO:
2068     case QID_AC_VI:
2069     case QID_AC_BE:
2070     case QID_AC_BK:
2071         queue->limit = 32;
2072         queue->data_size = DATA_FRAME_SIZE;
2073         queue->desc_size = TXD_DESC_SIZE;
2074         queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2075         break;
2076 
2077     case QID_BEACON:
2078         queue->limit = 1;
2079         queue->data_size = MGMT_FRAME_SIZE;
2080         queue->desc_size = TXD_DESC_SIZE;
2081         queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2082         break;
2083 
2084     case QID_ATIM:
2085         queue->limit = 8;
2086         queue->data_size = DATA_FRAME_SIZE;
2087         queue->desc_size = TXD_DESC_SIZE;
2088         queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2089         break;
2090 
2091     default:
2092         BUG();
2093         break;
2094     }
2095 }
2096 
2097 static const struct rt2x00_ops rt2500pci_ops = {
2098     .name           = KBUILD_MODNAME,
2099     .max_ap_intf        = 1,
2100     .eeprom_size        = EEPROM_SIZE,
2101     .rf_size        = RF_SIZE,
2102     .tx_queues      = NUM_TX_QUEUES,
2103     .queue_init     = rt2500pci_queue_init,
2104     .lib            = &rt2500pci_rt2x00_ops,
2105     .hw         = &rt2500pci_mac80211_ops,
2106 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2107     .debugfs        = &rt2500pci_rt2x00debug,
2108 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2109 };
2110 
2111 /*
2112  * RT2500pci module information.
2113  */
2114 static const struct pci_device_id rt2500pci_device_table[] = {
2115     { PCI_DEVICE(0x1814, 0x0201) },
2116     { 0, }
2117 };
2118 
2119 MODULE_AUTHOR(DRV_PROJECT);
2120 MODULE_VERSION(DRV_VERSION);
2121 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
2122 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
2123 MODULE_LICENSE("GPL");
2124 
2125 static int rt2500pci_probe(struct pci_dev *pci_dev,
2126                const struct pci_device_id *id)
2127 {
2128     return rt2x00pci_probe(pci_dev, &rt2500pci_ops);
2129 }
2130 
2131 static struct pci_driver rt2500pci_driver = {
2132     .name       = KBUILD_MODNAME,
2133     .id_table   = rt2500pci_device_table,
2134     .probe      = rt2500pci_probe,
2135     .remove     = rt2x00pci_remove,
2136     .driver.pm  = &rt2x00pci_pm_ops,
2137 };
2138 
2139 module_pci_driver(rt2500pci_driver);
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