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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003     Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
0004     <http://rt2x00.serialmonkey.com>
0005 
0006  */
0007 
0008 /*
0009     Module: rt2400pci
0010     Abstract: Data structures and registers for the rt2400pci module.
0011     Supported chipsets: RT2460.
0012  */
0013 
0014 #ifndef RT2400PCI_H
0015 #define RT2400PCI_H
0016 
0017 /*
0018  * RF chip defines.
0019  */
0020 #define RF2420              0x0000
0021 #define RF2421              0x0001
0022 
0023 /*
0024  * Signal information.
0025  * Default offset is required for RSSI <-> dBm conversion.
0026  */
0027 #define DEFAULT_RSSI_OFFSET     100
0028 
0029 /*
0030  * Register layout information.
0031  */
0032 #define CSR_REG_BASE            0x0000
0033 #define CSR_REG_SIZE            0x014c
0034 #define EEPROM_BASE         0x0000
0035 #define EEPROM_SIZE         0x0100
0036 #define BBP_BASE            0x0000
0037 #define BBP_SIZE            0x0020
0038 #define RF_BASE             0x0004
0039 #define RF_SIZE             0x000c
0040 
0041 /*
0042  * Number of TX queues.
0043  */
0044 #define NUM_TX_QUEUES           2
0045 
0046 /*
0047  * Control/Status Registers(CSR).
0048  * Some values are set in TU, whereas 1 TU == 1024 us.
0049  */
0050 
0051 /*
0052  * CSR0: ASIC revision number.
0053  */
0054 #define CSR0                0x0000
0055 #define CSR0_REVISION           FIELD32(0x0000ffff)
0056 
0057 /*
0058  * CSR1: System control register.
0059  * SOFT_RESET: Software reset, 1: reset, 0: normal.
0060  * BBP_RESET: Hardware reset, 1: reset, 0, release.
0061  * HOST_READY: Host ready after initialization.
0062  */
0063 #define CSR1                0x0004
0064 #define CSR1_SOFT_RESET         FIELD32(0x00000001)
0065 #define CSR1_BBP_RESET          FIELD32(0x00000002)
0066 #define CSR1_HOST_READY         FIELD32(0x00000004)
0067 
0068 /*
0069  * CSR2: System admin status register (invalid).
0070  */
0071 #define CSR2                0x0008
0072 
0073 /*
0074  * CSR3: STA MAC address register 0.
0075  */
0076 #define CSR3                0x000c
0077 #define CSR3_BYTE0          FIELD32(0x000000ff)
0078 #define CSR3_BYTE1          FIELD32(0x0000ff00)
0079 #define CSR3_BYTE2          FIELD32(0x00ff0000)
0080 #define CSR3_BYTE3          FIELD32(0xff000000)
0081 
0082 /*
0083  * CSR4: STA MAC address register 1.
0084  */
0085 #define CSR4                0x0010
0086 #define CSR4_BYTE4          FIELD32(0x000000ff)
0087 #define CSR4_BYTE5          FIELD32(0x0000ff00)
0088 
0089 /*
0090  * CSR5: BSSID register 0.
0091  */
0092 #define CSR5                0x0014
0093 #define CSR5_BYTE0          FIELD32(0x000000ff)
0094 #define CSR5_BYTE1          FIELD32(0x0000ff00)
0095 #define CSR5_BYTE2          FIELD32(0x00ff0000)
0096 #define CSR5_BYTE3          FIELD32(0xff000000)
0097 
0098 /*
0099  * CSR6: BSSID register 1.
0100  */
0101 #define CSR6                0x0018
0102 #define CSR6_BYTE4          FIELD32(0x000000ff)
0103 #define CSR6_BYTE5          FIELD32(0x0000ff00)
0104 
0105 /*
0106  * CSR7: Interrupt source register.
0107  * Write 1 to clear interrupt.
0108  * TBCN_EXPIRE: Beacon timer expired interrupt.
0109  * TWAKE_EXPIRE: Wakeup timer expired interrupt.
0110  * TATIMW_EXPIRE: Timer of atim window expired interrupt.
0111  * TXDONE_TXRING: Tx ring transmit done interrupt.
0112  * TXDONE_ATIMRING: Atim ring transmit done interrupt.
0113  * TXDONE_PRIORING: Priority ring transmit done interrupt.
0114  * RXDONE: Receive done interrupt.
0115  */
0116 #define CSR7                0x001c
0117 #define CSR7_TBCN_EXPIRE        FIELD32(0x00000001)
0118 #define CSR7_TWAKE_EXPIRE       FIELD32(0x00000002)
0119 #define CSR7_TATIMW_EXPIRE      FIELD32(0x00000004)
0120 #define CSR7_TXDONE_TXRING      FIELD32(0x00000008)
0121 #define CSR7_TXDONE_ATIMRING        FIELD32(0x00000010)
0122 #define CSR7_TXDONE_PRIORING        FIELD32(0x00000020)
0123 #define CSR7_RXDONE         FIELD32(0x00000040)
0124 
0125 /*
0126  * CSR8: Interrupt mask register.
0127  * Write 1 to mask interrupt.
0128  * TBCN_EXPIRE: Beacon timer expired interrupt.
0129  * TWAKE_EXPIRE: Wakeup timer expired interrupt.
0130  * TATIMW_EXPIRE: Timer of atim window expired interrupt.
0131  * TXDONE_TXRING: Tx ring transmit done interrupt.
0132  * TXDONE_ATIMRING: Atim ring transmit done interrupt.
0133  * TXDONE_PRIORING: Priority ring transmit done interrupt.
0134  * RXDONE: Receive done interrupt.
0135  */
0136 #define CSR8                0x0020
0137 #define CSR8_TBCN_EXPIRE        FIELD32(0x00000001)
0138 #define CSR8_TWAKE_EXPIRE       FIELD32(0x00000002)
0139 #define CSR8_TATIMW_EXPIRE      FIELD32(0x00000004)
0140 #define CSR8_TXDONE_TXRING      FIELD32(0x00000008)
0141 #define CSR8_TXDONE_ATIMRING        FIELD32(0x00000010)
0142 #define CSR8_TXDONE_PRIORING        FIELD32(0x00000020)
0143 #define CSR8_RXDONE         FIELD32(0x00000040)
0144 
0145 /*
0146  * CSR9: Maximum frame length register.
0147  * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
0148  */
0149 #define CSR9                0x0024
0150 #define CSR9_MAX_FRAME_UNIT     FIELD32(0x00000f80)
0151 
0152 /*
0153  * CSR11: Back-off control register.
0154  * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
0155  * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
0156  * SLOT_TIME: Slot time, default is 20us for 802.11b.
0157  * LONG_RETRY: Long retry count.
0158  * SHORT_RETRY: Short retry count.
0159  */
0160 #define CSR11               0x002c
0161 #define CSR11_CWMIN         FIELD32(0x0000000f)
0162 #define CSR11_CWMAX         FIELD32(0x000000f0)
0163 #define CSR11_SLOT_TIME         FIELD32(0x00001f00)
0164 #define CSR11_LONG_RETRY        FIELD32(0x00ff0000)
0165 #define CSR11_SHORT_RETRY       FIELD32(0xff000000)
0166 
0167 /*
0168  * CSR12: Synchronization configuration register 0.
0169  * All units in 1/16 TU.
0170  * BEACON_INTERVAL: Beacon interval, default is 100 TU.
0171  * CFPMAX_DURATION: Cfp maximum duration, default is 100 TU.
0172  */
0173 #define CSR12               0x0030
0174 #define CSR12_BEACON_INTERVAL       FIELD32(0x0000ffff)
0175 #define CSR12_CFP_MAX_DURATION      FIELD32(0xffff0000)
0176 
0177 /*
0178  * CSR13: Synchronization configuration register 1.
0179  * All units in 1/16 TU.
0180  * ATIMW_DURATION: Atim window duration.
0181  * CFP_PERIOD: Cfp period, default is 0 TU.
0182  */
0183 #define CSR13               0x0034
0184 #define CSR13_ATIMW_DURATION        FIELD32(0x0000ffff)
0185 #define CSR13_CFP_PERIOD        FIELD32(0x00ff0000)
0186 
0187 /*
0188  * CSR14: Synchronization control register.
0189  * TSF_COUNT: Enable tsf auto counting.
0190  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
0191  * TBCN: Enable tbcn with reload value.
0192  * TCFP: Enable tcfp & cfp / cp switching.
0193  * TATIMW: Enable tatimw & atim window switching.
0194  * BEACON_GEN: Enable beacon generator.
0195  * CFP_COUNT_PRELOAD: Cfp count preload value.
0196  * TBCM_PRELOAD: Tbcn preload value in units of 64us.
0197  */
0198 #define CSR14               0x0038
0199 #define CSR14_TSF_COUNT         FIELD32(0x00000001)
0200 #define CSR14_TSF_SYNC          FIELD32(0x00000006)
0201 #define CSR14_TBCN          FIELD32(0x00000008)
0202 #define CSR14_TCFP          FIELD32(0x00000010)
0203 #define CSR14_TATIMW            FIELD32(0x00000020)
0204 #define CSR14_BEACON_GEN        FIELD32(0x00000040)
0205 #define CSR14_CFP_COUNT_PRELOAD     FIELD32(0x0000ff00)
0206 #define CSR14_TBCM_PRELOAD      FIELD32(0xffff0000)
0207 
0208 /*
0209  * CSR15: Synchronization status register.
0210  * CFP: ASIC is in contention-free period.
0211  * ATIMW: ASIC is in ATIM window.
0212  * BEACON_SENT: Beacon is send.
0213  */
0214 #define CSR15               0x003c
0215 #define CSR15_CFP           FIELD32(0x00000001)
0216 #define CSR15_ATIMW         FIELD32(0x00000002)
0217 #define CSR15_BEACON_SENT       FIELD32(0x00000004)
0218 
0219 /*
0220  * CSR16: TSF timer register 0.
0221  */
0222 #define CSR16               0x0040
0223 #define CSR16_LOW_TSFTIMER      FIELD32(0xffffffff)
0224 
0225 /*
0226  * CSR17: TSF timer register 1.
0227  */
0228 #define CSR17               0x0044
0229 #define CSR17_HIGH_TSFTIMER     FIELD32(0xffffffff)
0230 
0231 /*
0232  * CSR18: IFS timer register 0.
0233  * SIFS: Sifs, default is 10 us.
0234  * PIFS: Pifs, default is 30 us.
0235  */
0236 #define CSR18               0x0048
0237 #define CSR18_SIFS          FIELD32(0x0000ffff)
0238 #define CSR18_PIFS          FIELD32(0xffff0000)
0239 
0240 /*
0241  * CSR19: IFS timer register 1.
0242  * DIFS: Difs, default is 50 us.
0243  * EIFS: Eifs, default is 364 us.
0244  */
0245 #define CSR19               0x004c
0246 #define CSR19_DIFS          FIELD32(0x0000ffff)
0247 #define CSR19_EIFS          FIELD32(0xffff0000)
0248 
0249 /*
0250  * CSR20: Wakeup timer register.
0251  * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
0252  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
0253  * AUTOWAKE: Enable auto wakeup / sleep mechanism.
0254  */
0255 #define CSR20               0x0050
0256 #define CSR20_DELAY_AFTER_TBCN      FIELD32(0x0000ffff)
0257 #define CSR20_TBCN_BEFORE_WAKEUP    FIELD32(0x00ff0000)
0258 #define CSR20_AUTOWAKE          FIELD32(0x01000000)
0259 
0260 /*
0261  * CSR21: EEPROM control register.
0262  * RELOAD: Write 1 to reload eeprom content.
0263  * TYPE_93C46: 1: 93c46, 0:93c66.
0264  */
0265 #define CSR21               0x0054
0266 #define CSR21_RELOAD            FIELD32(0x00000001)
0267 #define CSR21_EEPROM_DATA_CLOCK     FIELD32(0x00000002)
0268 #define CSR21_EEPROM_CHIP_SELECT    FIELD32(0x00000004)
0269 #define CSR21_EEPROM_DATA_IN        FIELD32(0x00000008)
0270 #define CSR21_EEPROM_DATA_OUT       FIELD32(0x00000010)
0271 #define CSR21_TYPE_93C46        FIELD32(0x00000020)
0272 
0273 /*
0274  * CSR22: CFP control register.
0275  * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
0276  * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
0277  */
0278 #define CSR22               0x0058
0279 #define CSR22_CFP_DURATION_REMAIN   FIELD32(0x0000ffff)
0280 #define CSR22_RELOAD_CFP_DURATION   FIELD32(0x00010000)
0281 
0282 /*
0283  * Transmit related CSRs.
0284  * Some values are set in TU, whereas 1 TU == 1024 us.
0285  */
0286 
0287 /*
0288  * TXCSR0: TX Control Register.
0289  * KICK_TX: Kick tx ring.
0290  * KICK_ATIM: Kick atim ring.
0291  * KICK_PRIO: Kick priority ring.
0292  * ABORT: Abort all transmit related ring operation.
0293  */
0294 #define TXCSR0              0x0060
0295 #define TXCSR0_KICK_TX          FIELD32(0x00000001)
0296 #define TXCSR0_KICK_ATIM        FIELD32(0x00000002)
0297 #define TXCSR0_KICK_PRIO        FIELD32(0x00000004)
0298 #define TXCSR0_ABORT            FIELD32(0x00000008)
0299 
0300 /*
0301  * TXCSR1: TX Configuration Register.
0302  * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
0303  * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
0304  * TSF_OFFSET: Insert tsf offset.
0305  * AUTORESPONDER: Enable auto responder which include ack & cts.
0306  */
0307 #define TXCSR1              0x0064
0308 #define TXCSR1_ACK_TIMEOUT      FIELD32(0x000001ff)
0309 #define TXCSR1_ACK_CONSUME_TIME     FIELD32(0x0003fe00)
0310 #define TXCSR1_TSF_OFFSET       FIELD32(0x00fc0000)
0311 #define TXCSR1_AUTORESPONDER        FIELD32(0x01000000)
0312 
0313 /*
0314  * TXCSR2: Tx descriptor configuration register.
0315  * TXD_SIZE: Tx descriptor size, default is 48.
0316  * NUM_TXD: Number of tx entries in ring.
0317  * NUM_ATIM: Number of atim entries in ring.
0318  * NUM_PRIO: Number of priority entries in ring.
0319  */
0320 #define TXCSR2              0x0068
0321 #define TXCSR2_TXD_SIZE         FIELD32(0x000000ff)
0322 #define TXCSR2_NUM_TXD          FIELD32(0x0000ff00)
0323 #define TXCSR2_NUM_ATIM         FIELD32(0x00ff0000)
0324 #define TXCSR2_NUM_PRIO         FIELD32(0xff000000)
0325 
0326 /*
0327  * TXCSR3: TX Ring Base address register.
0328  */
0329 #define TXCSR3              0x006c
0330 #define TXCSR3_TX_RING_REGISTER     FIELD32(0xffffffff)
0331 
0332 /*
0333  * TXCSR4: TX Atim Ring Base address register.
0334  */
0335 #define TXCSR4              0x0070
0336 #define TXCSR4_ATIM_RING_REGISTER   FIELD32(0xffffffff)
0337 
0338 /*
0339  * TXCSR5: TX Prio Ring Base address register.
0340  */
0341 #define TXCSR5              0x0074
0342 #define TXCSR5_PRIO_RING_REGISTER   FIELD32(0xffffffff)
0343 
0344 /*
0345  * TXCSR6: Beacon Base address register.
0346  */
0347 #define TXCSR6              0x0078
0348 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
0349 
0350 /*
0351  * TXCSR7: Auto responder control register.
0352  * AR_POWERMANAGEMENT: Auto responder power management bit.
0353  */
0354 #define TXCSR7              0x007c
0355 #define TXCSR7_AR_POWERMANAGEMENT   FIELD32(0x00000001)
0356 
0357 /*
0358  * Receive related CSRs.
0359  * Some values are set in TU, whereas 1 TU == 1024 us.
0360  */
0361 
0362 /*
0363  * RXCSR0: RX Control Register.
0364  * DISABLE_RX: Disable rx engine.
0365  * DROP_CRC: Drop crc error.
0366  * DROP_PHYSICAL: Drop physical error.
0367  * DROP_CONTROL: Drop control frame.
0368  * DROP_NOT_TO_ME: Drop not to me unicast frame.
0369  * DROP_TODS: Drop frame tods bit is true.
0370  * DROP_VERSION_ERROR: Drop version error frame.
0371  * PASS_CRC: Pass all packets with crc attached.
0372  */
0373 #define RXCSR0              0x0080
0374 #define RXCSR0_DISABLE_RX       FIELD32(0x00000001)
0375 #define RXCSR0_DROP_CRC         FIELD32(0x00000002)
0376 #define RXCSR0_DROP_PHYSICAL        FIELD32(0x00000004)
0377 #define RXCSR0_DROP_CONTROL     FIELD32(0x00000008)
0378 #define RXCSR0_DROP_NOT_TO_ME       FIELD32(0x00000010)
0379 #define RXCSR0_DROP_TODS        FIELD32(0x00000020)
0380 #define RXCSR0_DROP_VERSION_ERROR   FIELD32(0x00000040)
0381 #define RXCSR0_PASS_CRC         FIELD32(0x00000080)
0382 
0383 /*
0384  * RXCSR1: RX descriptor configuration register.
0385  * RXD_SIZE: Rx descriptor size, default is 32b.
0386  * NUM_RXD: Number of rx entries in ring.
0387  */
0388 #define RXCSR1              0x0084
0389 #define RXCSR1_RXD_SIZE         FIELD32(0x000000ff)
0390 #define RXCSR1_NUM_RXD          FIELD32(0x0000ff00)
0391 
0392 /*
0393  * RXCSR2: RX Ring base address register.
0394  */
0395 #define RXCSR2              0x0088
0396 #define RXCSR2_RX_RING_REGISTER     FIELD32(0xffffffff)
0397 
0398 /*
0399  * RXCSR3: BBP ID register for Rx operation.
0400  * BBP_ID#: BBP register # id.
0401  * BBP_ID#_VALID: BBP register # id is valid or not.
0402  */
0403 #define RXCSR3              0x0090
0404 #define RXCSR3_BBP_ID0          FIELD32(0x0000007f)
0405 #define RXCSR3_BBP_ID0_VALID        FIELD32(0x00000080)
0406 #define RXCSR3_BBP_ID1          FIELD32(0x00007f00)
0407 #define RXCSR3_BBP_ID1_VALID        FIELD32(0x00008000)
0408 #define RXCSR3_BBP_ID2          FIELD32(0x007f0000)
0409 #define RXCSR3_BBP_ID2_VALID        FIELD32(0x00800000)
0410 #define RXCSR3_BBP_ID3          FIELD32(0x7f000000)
0411 #define RXCSR3_BBP_ID3_VALID        FIELD32(0x80000000)
0412 
0413 /*
0414  * RXCSR4: BBP ID register for Rx operation.
0415  * BBP_ID#: BBP register # id.
0416  * BBP_ID#_VALID: BBP register # id is valid or not.
0417  */
0418 #define RXCSR4              0x0094
0419 #define RXCSR4_BBP_ID4          FIELD32(0x0000007f)
0420 #define RXCSR4_BBP_ID4_VALID        FIELD32(0x00000080)
0421 #define RXCSR4_BBP_ID5          FIELD32(0x00007f00)
0422 #define RXCSR4_BBP_ID5_VALID        FIELD32(0x00008000)
0423 
0424 /*
0425  * ARCSR0: Auto Responder PLCP config register 0.
0426  * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
0427  * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
0428  */
0429 #define ARCSR0              0x0098
0430 #define ARCSR0_AR_BBP_DATA0     FIELD32(0x000000ff)
0431 #define ARCSR0_AR_BBP_ID0       FIELD32(0x0000ff00)
0432 #define ARCSR0_AR_BBP_DATA1     FIELD32(0x00ff0000)
0433 #define ARCSR0_AR_BBP_ID1       FIELD32(0xff000000)
0434 
0435 /*
0436  * ARCSR1: Auto Responder PLCP config register 1.
0437  * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
0438  * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
0439  */
0440 #define ARCSR1              0x009c
0441 #define ARCSR1_AR_BBP_DATA2     FIELD32(0x000000ff)
0442 #define ARCSR1_AR_BBP_ID2       FIELD32(0x0000ff00)
0443 #define ARCSR1_AR_BBP_DATA3     FIELD32(0x00ff0000)
0444 #define ARCSR1_AR_BBP_ID3       FIELD32(0xff000000)
0445 
0446 /*
0447  * Miscellaneous Registers.
0448  * Some values are set in TU, whereas 1 TU == 1024 us.
0449  */
0450 
0451 /*
0452  * PCICSR: PCI control register.
0453  * BIG_ENDIAN: 1: big endian, 0: little endian.
0454  * RX_TRESHOLD: Rx threshold in dw to start pci access
0455  * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
0456  * TX_TRESHOLD: Tx threshold in dw to start pci access
0457  * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
0458  * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
0459  * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
0460  */
0461 #define PCICSR              0x008c
0462 #define PCICSR_BIG_ENDIAN       FIELD32(0x00000001)
0463 #define PCICSR_RX_TRESHOLD      FIELD32(0x00000006)
0464 #define PCICSR_TX_TRESHOLD      FIELD32(0x00000018)
0465 #define PCICSR_BURST_LENTH      FIELD32(0x00000060)
0466 #define PCICSR_ENABLE_CLK       FIELD32(0x00000080)
0467 
0468 /*
0469  * CNT0: FCS error count.
0470  * FCS_ERROR: FCS error count, cleared when read.
0471  */
0472 #define CNT0                0x00a0
0473 #define CNT0_FCS_ERROR          FIELD32(0x0000ffff)
0474 
0475 /*
0476  * Statistic Register.
0477  * CNT1: PLCP error count.
0478  * CNT2: Long error count.
0479  * CNT3: CCA false alarm count.
0480  * CNT4: Rx FIFO overflow count.
0481  * CNT5: Tx FIFO underrun count.
0482  */
0483 #define TIMECSR2            0x00a8
0484 #define CNT1                0x00ac
0485 #define CNT2                0x00b0
0486 #define TIMECSR3            0x00b4
0487 #define CNT3                0x00b8
0488 #define CNT4                0x00bc
0489 #define CNT5                0x00c0
0490 
0491 /*
0492  * Baseband Control Register.
0493  */
0494 
0495 /*
0496  * PWRCSR0: Power mode configuration register.
0497  */
0498 #define PWRCSR0             0x00c4
0499 
0500 /*
0501  * Power state transition time registers.
0502  */
0503 #define PSCSR0              0x00c8
0504 #define PSCSR1              0x00cc
0505 #define PSCSR2              0x00d0
0506 #define PSCSR3              0x00d4
0507 
0508 /*
0509  * PWRCSR1: Manual power control / status register.
0510  * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
0511  * SET_STATE: Set state. Write 1 to trigger, self cleared.
0512  * BBP_DESIRE_STATE: BBP desired state.
0513  * RF_DESIRE_STATE: RF desired state.
0514  * BBP_CURR_STATE: BBP current state.
0515  * RF_CURR_STATE: RF current state.
0516  * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
0517  */
0518 #define PWRCSR1             0x00d8
0519 #define PWRCSR1_SET_STATE       FIELD32(0x00000001)
0520 #define PWRCSR1_BBP_DESIRE_STATE    FIELD32(0x00000006)
0521 #define PWRCSR1_RF_DESIRE_STATE     FIELD32(0x00000018)
0522 #define PWRCSR1_BBP_CURR_STATE      FIELD32(0x00000060)
0523 #define PWRCSR1_RF_CURR_STATE       FIELD32(0x00000180)
0524 #define PWRCSR1_PUT_TO_SLEEP        FIELD32(0x00000200)
0525 
0526 /*
0527  * TIMECSR: Timer control register.
0528  * US_COUNT: 1 us timer count in units of clock cycles.
0529  * US_64_COUNT: 64 us timer count in units of 1 us timer.
0530  * BEACON_EXPECT: Beacon expect window.
0531  */
0532 #define TIMECSR             0x00dc
0533 #define TIMECSR_US_COUNT        FIELD32(0x000000ff)
0534 #define TIMECSR_US_64_COUNT     FIELD32(0x0000ff00)
0535 #define TIMECSR_BEACON_EXPECT       FIELD32(0x00070000)
0536 
0537 /*
0538  * MACCSR0: MAC configuration register 0.
0539  */
0540 #define MACCSR0             0x00e0
0541 
0542 /*
0543  * MACCSR1: MAC configuration register 1.
0544  * KICK_RX: Kick one-shot rx in one-shot rx mode.
0545  * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
0546  * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
0547  * AUTO_TXBBP: Auto tx logic access bbp control register.
0548  * AUTO_RXBBP: Auto rx logic access bbp control register.
0549  * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
0550  * INTERSIL_IF: Intersil if calibration pin.
0551  */
0552 #define MACCSR1             0x00e4
0553 #define MACCSR1_KICK_RX         FIELD32(0x00000001)
0554 #define MACCSR1_ONESHOT_RXMODE      FIELD32(0x00000002)
0555 #define MACCSR1_BBPRX_RESET_MODE    FIELD32(0x00000004)
0556 #define MACCSR1_AUTO_TXBBP      FIELD32(0x00000008)
0557 #define MACCSR1_AUTO_RXBBP      FIELD32(0x00000010)
0558 #define MACCSR1_LOOPBACK        FIELD32(0x00000060)
0559 #define MACCSR1_INTERSIL_IF     FIELD32(0x00000080)
0560 
0561 /*
0562  * RALINKCSR: Ralink Rx auto-reset BBCR.
0563  * AR_BBP_DATA#: Auto reset BBP register # data.
0564  * AR_BBP_ID#: Auto reset BBP register # id.
0565  */
0566 #define RALINKCSR           0x00e8
0567 #define RALINKCSR_AR_BBP_DATA0      FIELD32(0x000000ff)
0568 #define RALINKCSR_AR_BBP_ID0        FIELD32(0x0000ff00)
0569 #define RALINKCSR_AR_BBP_DATA1      FIELD32(0x00ff0000)
0570 #define RALINKCSR_AR_BBP_ID1        FIELD32(0xff000000)
0571 
0572 /*
0573  * BCNCSR: Beacon interval control register.
0574  * CHANGE: Write one to change beacon interval.
0575  * DELTATIME: The delta time value.
0576  * NUM_BEACON: Number of beacon according to mode.
0577  * MODE: Please refer to asic specs.
0578  * PLUS: Plus or minus delta time value.
0579  */
0580 #define BCNCSR              0x00ec
0581 #define BCNCSR_CHANGE           FIELD32(0x00000001)
0582 #define BCNCSR_DELTATIME        FIELD32(0x0000001e)
0583 #define BCNCSR_NUM_BEACON       FIELD32(0x00001fe0)
0584 #define BCNCSR_MODE         FIELD32(0x00006000)
0585 #define BCNCSR_PLUS         FIELD32(0x00008000)
0586 
0587 /*
0588  * BBP / RF / IF Control Register.
0589  */
0590 
0591 /*
0592  * BBPCSR: BBP serial control register.
0593  * VALUE: Register value to program into BBP.
0594  * REGNUM: Selected BBP register.
0595  * BUSY: 1: asic is busy execute BBP programming.
0596  * WRITE_CONTROL: 1: write BBP, 0: read BBP.
0597  */
0598 #define BBPCSR              0x00f0
0599 #define BBPCSR_VALUE            FIELD32(0x000000ff)
0600 #define BBPCSR_REGNUM           FIELD32(0x00007f00)
0601 #define BBPCSR_BUSY         FIELD32(0x00008000)
0602 #define BBPCSR_WRITE_CONTROL        FIELD32(0x00010000)
0603 
0604 /*
0605  * RFCSR: RF serial control register.
0606  * VALUE: Register value + id to program into rf/if.
0607  * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
0608  * IF_SELECT: Chip to program: 0: rf, 1: if.
0609  * PLL_LD: Rf pll_ld status.
0610  * BUSY: 1: asic is busy execute rf programming.
0611  */
0612 #define RFCSR               0x00f4
0613 #define RFCSR_VALUE         FIELD32(0x00ffffff)
0614 #define RFCSR_NUMBER_OF_BITS        FIELD32(0x1f000000)
0615 #define RFCSR_IF_SELECT         FIELD32(0x20000000)
0616 #define RFCSR_PLL_LD            FIELD32(0x40000000)
0617 #define RFCSR_BUSY          FIELD32(0x80000000)
0618 
0619 /*
0620  * LEDCSR: LED control register.
0621  * ON_PERIOD: On period, default 70ms.
0622  * OFF_PERIOD: Off period, default 30ms.
0623  * LINK: 0: linkoff, 1: linkup.
0624  * ACTIVITY: 0: idle, 1: active.
0625  */
0626 #define LEDCSR              0x00f8
0627 #define LEDCSR_ON_PERIOD        FIELD32(0x000000ff)
0628 #define LEDCSR_OFF_PERIOD       FIELD32(0x0000ff00)
0629 #define LEDCSR_LINK         FIELD32(0x00010000)
0630 #define LEDCSR_ACTIVITY         FIELD32(0x00020000)
0631 
0632 /*
0633  * ASIC pointer information.
0634  * RXPTR: Current RX ring address.
0635  * TXPTR: Current Tx ring address.
0636  * PRIPTR: Current Priority ring address.
0637  * ATIMPTR: Current ATIM ring address.
0638  */
0639 #define RXPTR               0x0100
0640 #define TXPTR               0x0104
0641 #define PRIPTR              0x0108
0642 #define ATIMPTR             0x010c
0643 
0644 /*
0645  * GPIO and others.
0646  */
0647 
0648 /*
0649  * GPIOCSR: GPIO control register.
0650  *  GPIOCSR_VALx: Actual GPIO pin x value
0651  *  GPIOCSR_DIRx: GPIO direction: 0 = output; 1 = input
0652  */
0653 #define GPIOCSR             0x0120
0654 #define GPIOCSR_VAL0            FIELD32(0x00000001)
0655 #define GPIOCSR_VAL1            FIELD32(0x00000002)
0656 #define GPIOCSR_VAL2            FIELD32(0x00000004)
0657 #define GPIOCSR_VAL3            FIELD32(0x00000008)
0658 #define GPIOCSR_VAL4            FIELD32(0x00000010)
0659 #define GPIOCSR_VAL5            FIELD32(0x00000020)
0660 #define GPIOCSR_VAL6            FIELD32(0x00000040)
0661 #define GPIOCSR_VAL7            FIELD32(0x00000080)
0662 #define GPIOCSR_DIR0            FIELD32(0x00000100)
0663 #define GPIOCSR_DIR1            FIELD32(0x00000200)
0664 #define GPIOCSR_DIR2            FIELD32(0x00000400)
0665 #define GPIOCSR_DIR3            FIELD32(0x00000800)
0666 #define GPIOCSR_DIR4            FIELD32(0x00001000)
0667 #define GPIOCSR_DIR5            FIELD32(0x00002000)
0668 #define GPIOCSR_DIR6            FIELD32(0x00004000)
0669 #define GPIOCSR_DIR7            FIELD32(0x00008000)
0670 
0671 /*
0672  * BBPPCSR: BBP Pin control register.
0673  */
0674 #define BBPPCSR             0x0124
0675 
0676 /*
0677  * BCNCSR1: Tx BEACON offset time control register.
0678  * PRELOAD: Beacon timer offset in units of usec.
0679  */
0680 #define BCNCSR1             0x0130
0681 #define BCNCSR1_PRELOAD         FIELD32(0x0000ffff)
0682 
0683 /*
0684  * MACCSR2: TX_PE to RX_PE turn-around time control register
0685  * DELAY: RX_PE low width, in units of pci clock cycle.
0686  */
0687 #define MACCSR2             0x0134
0688 #define MACCSR2_DELAY           FIELD32(0x000000ff)
0689 
0690 /*
0691  * ARCSR2: 1 Mbps ACK/CTS PLCP.
0692  */
0693 #define ARCSR2              0x013c
0694 #define ARCSR2_SIGNAL           FIELD32(0x000000ff)
0695 #define ARCSR2_SERVICE          FIELD32(0x0000ff00)
0696 #define ARCSR2_LENGTH_LOW       FIELD32(0x00ff0000)
0697 #define ARCSR2_LENGTH           FIELD32(0xffff0000)
0698 
0699 /*
0700  * ARCSR3: 2 Mbps ACK/CTS PLCP.
0701  */
0702 #define ARCSR3              0x0140
0703 #define ARCSR3_SIGNAL           FIELD32(0x000000ff)
0704 #define ARCSR3_SERVICE          FIELD32(0x0000ff00)
0705 #define ARCSR3_LENGTH           FIELD32(0xffff0000)
0706 
0707 /*
0708  * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
0709  */
0710 #define ARCSR4              0x0144
0711 #define ARCSR4_SIGNAL           FIELD32(0x000000ff)
0712 #define ARCSR4_SERVICE          FIELD32(0x0000ff00)
0713 #define ARCSR4_LENGTH           FIELD32(0xffff0000)
0714 
0715 /*
0716  * ARCSR5: 11 Mbps ACK/CTS PLCP.
0717  */
0718 #define ARCSR5              0x0148
0719 #define ARCSR5_SIGNAL           FIELD32(0x000000ff)
0720 #define ARCSR5_SERVICE          FIELD32(0x0000ff00)
0721 #define ARCSR5_LENGTH           FIELD32(0xffff0000)
0722 
0723 /*
0724  * BBP registers.
0725  * The wordsize of the BBP is 8 bits.
0726  */
0727 
0728 /*
0729  * R1: TX antenna control
0730  */
0731 #define BBP_R1_TX_ANTENNA       FIELD8(0x03)
0732 
0733 /*
0734  * R4: RX antenna control
0735  */
0736 #define BBP_R4_RX_ANTENNA       FIELD8(0x06)
0737 
0738 /*
0739  * RF registers
0740  */
0741 
0742 /*
0743  * RF 1
0744  */
0745 #define RF1_TUNER           FIELD32(0x00020000)
0746 
0747 /*
0748  * RF 3
0749  */
0750 #define RF3_TUNER           FIELD32(0x00000100)
0751 #define RF3_TXPOWER         FIELD32(0x00003e00)
0752 
0753 /*
0754  * EEPROM content.
0755  * The wordsize of the EEPROM is 16 bits.
0756  */
0757 
0758 /*
0759  * HW MAC address.
0760  */
0761 #define EEPROM_MAC_ADDR_0       0x0002
0762 #define EEPROM_MAC_ADDR_BYTE0       FIELD16(0x00ff)
0763 #define EEPROM_MAC_ADDR_BYTE1       FIELD16(0xff00)
0764 #define EEPROM_MAC_ADDR1        0x0003
0765 #define EEPROM_MAC_ADDR_BYTE2       FIELD16(0x00ff)
0766 #define EEPROM_MAC_ADDR_BYTE3       FIELD16(0xff00)
0767 #define EEPROM_MAC_ADDR_2       0x0004
0768 #define EEPROM_MAC_ADDR_BYTE4       FIELD16(0x00ff)
0769 #define EEPROM_MAC_ADDR_BYTE5       FIELD16(0xff00)
0770 
0771 /*
0772  * EEPROM antenna.
0773  * ANTENNA_NUM: Number of antenna's.
0774  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
0775  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
0776  * RF_TYPE: Rf_type of this adapter.
0777  * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
0778  * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning.
0779  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
0780  */
0781 #define EEPROM_ANTENNA          0x0b
0782 #define EEPROM_ANTENNA_NUM      FIELD16(0x0003)
0783 #define EEPROM_ANTENNA_TX_DEFAULT   FIELD16(0x000c)
0784 #define EEPROM_ANTENNA_RX_DEFAULT   FIELD16(0x0030)
0785 #define EEPROM_ANTENNA_RF_TYPE      FIELD16(0x0040)
0786 #define EEPROM_ANTENNA_LED_MODE     FIELD16(0x0180)
0787 #define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200)
0788 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
0789 
0790 /*
0791  * EEPROM BBP.
0792  */
0793 #define EEPROM_BBP_START        0x0c
0794 #define EEPROM_BBP_SIZE         7
0795 #define EEPROM_BBP_VALUE        FIELD16(0x00ff)
0796 #define EEPROM_BBP_REG_ID       FIELD16(0xff00)
0797 
0798 /*
0799  * EEPROM TXPOWER
0800  */
0801 #define EEPROM_TXPOWER_START        0x13
0802 #define EEPROM_TXPOWER_SIZE     7
0803 #define EEPROM_TXPOWER_1        FIELD16(0x00ff)
0804 #define EEPROM_TXPOWER_2        FIELD16(0xff00)
0805 
0806 /*
0807  * DMA descriptor defines.
0808  */
0809 #define TXD_DESC_SIZE           (8 * sizeof(__le32))
0810 #define RXD_DESC_SIZE           (8 * sizeof(__le32))
0811 
0812 /*
0813  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
0814  */
0815 
0816 /*
0817  * Word0
0818  */
0819 #define TXD_W0_OWNER_NIC        FIELD32(0x00000001)
0820 #define TXD_W0_VALID            FIELD32(0x00000002)
0821 #define TXD_W0_RESULT           FIELD32(0x0000001c)
0822 #define TXD_W0_RETRY_COUNT      FIELD32(0x000000e0)
0823 #define TXD_W0_MORE_FRAG        FIELD32(0x00000100)
0824 #define TXD_W0_ACK          FIELD32(0x00000200)
0825 #define TXD_W0_TIMESTAMP        FIELD32(0x00000400)
0826 #define TXD_W0_RTS          FIELD32(0x00000800)
0827 #define TXD_W0_IFS          FIELD32(0x00006000)
0828 #define TXD_W0_RETRY_MODE       FIELD32(0x00008000)
0829 #define TXD_W0_AGC          FIELD32(0x00ff0000)
0830 #define TXD_W0_R2           FIELD32(0xff000000)
0831 
0832 /*
0833  * Word1
0834  */
0835 #define TXD_W1_BUFFER_ADDRESS       FIELD32(0xffffffff)
0836 
0837 /*
0838  * Word2
0839  */
0840 #define TXD_W2_BUFFER_LENGTH        FIELD32(0x0000ffff)
0841 #define TXD_W2_DATABYTE_COUNT       FIELD32(0xffff0000)
0842 
0843 /*
0844  * Word3 & 4: PLCP information
0845  * The PLCP values should be treated as if they were BBP values.
0846  */
0847 #define TXD_W3_PLCP_SIGNAL      FIELD32(0x000000ff)
0848 #define TXD_W3_PLCP_SIGNAL_REGNUM   FIELD32(0x00007f00)
0849 #define TXD_W3_PLCP_SIGNAL_BUSY     FIELD32(0x00008000)
0850 #define TXD_W3_PLCP_SERVICE     FIELD32(0x00ff0000)
0851 #define TXD_W3_PLCP_SERVICE_REGNUM  FIELD32(0x7f000000)
0852 #define TXD_W3_PLCP_SERVICE_BUSY    FIELD32(0x80000000)
0853 
0854 #define TXD_W4_PLCP_LENGTH_LOW      FIELD32(0x000000ff)
0855 #define TXD_W3_PLCP_LENGTH_LOW_REGNUM   FIELD32(0x00007f00)
0856 #define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000)
0857 #define TXD_W4_PLCP_LENGTH_HIGH     FIELD32(0x00ff0000)
0858 #define TXD_W3_PLCP_LENGTH_HIGH_REGNUM  FIELD32(0x7f000000)
0859 #define TXD_W3_PLCP_LENGTH_HIGH_BUSY    FIELD32(0x80000000)
0860 
0861 /*
0862  * Word5
0863  */
0864 #define TXD_W5_BBCR4            FIELD32(0x0000ffff)
0865 #define TXD_W5_AGC_REG          FIELD32(0x007f0000)
0866 #define TXD_W5_AGC_REG_VALID        FIELD32(0x00800000)
0867 #define TXD_W5_XXX_REG          FIELD32(0x7f000000)
0868 #define TXD_W5_XXX_REG_VALID        FIELD32(0x80000000)
0869 
0870 /*
0871  * Word6
0872  */
0873 #define TXD_W6_SK_BUFF          FIELD32(0xffffffff)
0874 
0875 /*
0876  * Word7
0877  */
0878 #define TXD_W7_RESERVED         FIELD32(0xffffffff)
0879 
0880 /*
0881  * RX descriptor format for RX Ring.
0882  */
0883 
0884 /*
0885  * Word0
0886  */
0887 #define RXD_W0_OWNER_NIC        FIELD32(0x00000001)
0888 #define RXD_W0_UNICAST_TO_ME        FIELD32(0x00000002)
0889 #define RXD_W0_MULTICAST        FIELD32(0x00000004)
0890 #define RXD_W0_BROADCAST        FIELD32(0x00000008)
0891 #define RXD_W0_MY_BSS           FIELD32(0x00000010)
0892 #define RXD_W0_CRC_ERROR        FIELD32(0x00000020)
0893 #define RXD_W0_PHYSICAL_ERROR       FIELD32(0x00000080)
0894 #define RXD_W0_DATABYTE_COUNT       FIELD32(0xffff0000)
0895 
0896 /*
0897  * Word1
0898  */
0899 #define RXD_W1_BUFFER_ADDRESS       FIELD32(0xffffffff)
0900 
0901 /*
0902  * Word2
0903  */
0904 #define RXD_W2_BUFFER_LENGTH        FIELD32(0x0000ffff)
0905 #define RXD_W2_BBR0         FIELD32(0x00ff0000)
0906 #define RXD_W2_SIGNAL           FIELD32(0xff000000)
0907 
0908 /*
0909  * Word3
0910  */
0911 #define RXD_W3_RSSI         FIELD32(0x000000ff)
0912 #define RXD_W3_BBR3         FIELD32(0x0000ff00)
0913 #define RXD_W3_BBR4         FIELD32(0x00ff0000)
0914 #define RXD_W3_BBR5         FIELD32(0xff000000)
0915 
0916 /*
0917  * Word4
0918  */
0919 #define RXD_W4_RX_END_TIME      FIELD32(0xffffffff)
0920 
0921 /*
0922  * Word5 & 6 & 7: Reserved
0923  */
0924 #define RXD_W5_RESERVED         FIELD32(0xffffffff)
0925 #define RXD_W6_RESERVED         FIELD32(0xffffffff)
0926 #define RXD_W7_RESERVED         FIELD32(0xffffffff)
0927 
0928 /*
0929  * Macros for converting txpower from EEPROM to mac80211 value
0930  * and from mac80211 value to register value.
0931  * NOTE: Logics in rt2400pci for txpower are reversed
0932  * compared to the other rt2x00 drivers. A higher txpower
0933  * value means that the txpower must be lowered. This is
0934  * important when converting the value coming from the
0935  * mac80211 stack to the rt2400 acceptable value.
0936  */
0937 #define MIN_TXPOWER 31
0938 #define MAX_TXPOWER 62
0939 #define DEFAULT_TXPOWER 39
0940 
0941 #define __CLAMP_TX(__txpower) \
0942     clamp_t(char, (__txpower), MIN_TXPOWER, MAX_TXPOWER)
0943 
0944 #define TXPOWER_FROM_DEV(__txpower) \
0945     ((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER)
0946 
0947 #define TXPOWER_TO_DEV(__txpower) \
0948     (MAX_TXPOWER - (__CLAMP_TX(__txpower) - MIN_TXPOWER))
0949 
0950 #endif /* RT2400PCI_H */
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