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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
0004     <http://rt2x00.serialmonkey.com>
0005 
0006  */
0007 
0008 /*
0009     Module: rt2400pci
0010     Abstract: rt2400pci device specific routines.
0011     Supported chipsets: RT2460.
0012  */
0013 
0014 #include <linux/delay.h>
0015 #include <linux/etherdevice.h>
0016 #include <linux/kernel.h>
0017 #include <linux/module.h>
0018 #include <linux/pci.h>
0019 #include <linux/eeprom_93cx6.h>
0020 #include <linux/slab.h>
0021 
0022 #include "rt2x00.h"
0023 #include "rt2x00mmio.h"
0024 #include "rt2x00pci.h"
0025 #include "rt2400pci.h"
0026 
0027 /*
0028  * Register access.
0029  * All access to the CSR registers will go through the methods
0030  * rt2x00mmio_register_read and rt2x00mmio_register_write.
0031  * BBP and RF register require indirect register access,
0032  * and use the CSR registers BBPCSR and RFCSR to achieve this.
0033  * These indirect registers work with busy bits,
0034  * and we will try maximal REGISTER_BUSY_COUNT times to access
0035  * the register while taking a REGISTER_BUSY_DELAY us delay
0036  * between each attempt. When the busy bit is still set at that time,
0037  * the access attempt is considered to have failed,
0038  * and we will print an error.
0039  */
0040 #define WAIT_FOR_BBP(__dev, __reg) \
0041     rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
0042 #define WAIT_FOR_RF(__dev, __reg) \
0043     rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
0044 
0045 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
0046                 const unsigned int word, const u8 value)
0047 {
0048     u32 reg;
0049 
0050     mutex_lock(&rt2x00dev->csr_mutex);
0051 
0052     /*
0053      * Wait until the BBP becomes available, afterwards we
0054      * can safely write the new data into the register.
0055      */
0056     if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
0057         reg = 0;
0058         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
0059         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
0060         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
0061         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
0062 
0063         rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
0064     }
0065 
0066     mutex_unlock(&rt2x00dev->csr_mutex);
0067 }
0068 
0069 static u8 rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
0070                  const unsigned int word)
0071 {
0072     u32 reg;
0073     u8 value;
0074 
0075     mutex_lock(&rt2x00dev->csr_mutex);
0076 
0077     /*
0078      * Wait until the BBP becomes available, afterwards we
0079      * can safely write the read request into the register.
0080      * After the data has been written, we wait until hardware
0081      * returns the correct value, if at any time the register
0082      * doesn't become available in time, reg will be 0xffffffff
0083      * which means we return 0xff to the caller.
0084      */
0085     if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
0086         reg = 0;
0087         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
0088         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
0089         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
0090 
0091         rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
0092 
0093         WAIT_FOR_BBP(rt2x00dev, &reg);
0094     }
0095 
0096     value = rt2x00_get_field32(reg, BBPCSR_VALUE);
0097 
0098     mutex_unlock(&rt2x00dev->csr_mutex);
0099 
0100     return value;
0101 }
0102 
0103 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
0104                    const unsigned int word, const u32 value)
0105 {
0106     u32 reg;
0107 
0108     mutex_lock(&rt2x00dev->csr_mutex);
0109 
0110     /*
0111      * Wait until the RF becomes available, afterwards we
0112      * can safely write the new data into the register.
0113      */
0114     if (WAIT_FOR_RF(rt2x00dev, &reg)) {
0115         reg = 0;
0116         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
0117         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
0118         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
0119         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
0120 
0121         rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
0122         rt2x00_rf_write(rt2x00dev, word, value);
0123     }
0124 
0125     mutex_unlock(&rt2x00dev->csr_mutex);
0126 }
0127 
0128 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
0129 {
0130     struct rt2x00_dev *rt2x00dev = eeprom->data;
0131     u32 reg;
0132 
0133     reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
0134 
0135     eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
0136     eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
0137     eeprom->reg_data_clock =
0138         !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
0139     eeprom->reg_chip_select =
0140         !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
0141 }
0142 
0143 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
0144 {
0145     struct rt2x00_dev *rt2x00dev = eeprom->data;
0146     u32 reg = 0;
0147 
0148     rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
0149     rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
0150     rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
0151                !!eeprom->reg_data_clock);
0152     rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
0153                !!eeprom->reg_chip_select);
0154 
0155     rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
0156 }
0157 
0158 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
0159 static const struct rt2x00debug rt2400pci_rt2x00debug = {
0160     .owner  = THIS_MODULE,
0161     .csr    = {
0162         .read       = rt2x00mmio_register_read,
0163         .write      = rt2x00mmio_register_write,
0164         .flags      = RT2X00DEBUGFS_OFFSET,
0165         .word_base  = CSR_REG_BASE,
0166         .word_size  = sizeof(u32),
0167         .word_count = CSR_REG_SIZE / sizeof(u32),
0168     },
0169     .eeprom = {
0170         .read       = rt2x00_eeprom_read,
0171         .write      = rt2x00_eeprom_write,
0172         .word_base  = EEPROM_BASE,
0173         .word_size  = sizeof(u16),
0174         .word_count = EEPROM_SIZE / sizeof(u16),
0175     },
0176     .bbp    = {
0177         .read       = rt2400pci_bbp_read,
0178         .write      = rt2400pci_bbp_write,
0179         .word_base  = BBP_BASE,
0180         .word_size  = sizeof(u8),
0181         .word_count = BBP_SIZE / sizeof(u8),
0182     },
0183     .rf = {
0184         .read       = rt2x00_rf_read,
0185         .write      = rt2400pci_rf_write,
0186         .word_base  = RF_BASE,
0187         .word_size  = sizeof(u32),
0188         .word_count = RF_SIZE / sizeof(u32),
0189     },
0190 };
0191 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
0192 
0193 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
0194 {
0195     u32 reg;
0196 
0197     reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
0198     return rt2x00_get_field32(reg, GPIOCSR_VAL0);
0199 }
0200 
0201 #ifdef CONFIG_RT2X00_LIB_LEDS
0202 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
0203                      enum led_brightness brightness)
0204 {
0205     struct rt2x00_led *led =
0206         container_of(led_cdev, struct rt2x00_led, led_dev);
0207     unsigned int enabled = brightness != LED_OFF;
0208     u32 reg;
0209 
0210     reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
0211 
0212     if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
0213         rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
0214     else if (led->type == LED_TYPE_ACTIVITY)
0215         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
0216 
0217     rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
0218 }
0219 
0220 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
0221                    unsigned long *delay_on,
0222                    unsigned long *delay_off)
0223 {
0224     struct rt2x00_led *led =
0225         container_of(led_cdev, struct rt2x00_led, led_dev);
0226     u32 reg;
0227 
0228     reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
0229     rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
0230     rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
0231     rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
0232 
0233     return 0;
0234 }
0235 
0236 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
0237                    struct rt2x00_led *led,
0238                    enum led_type type)
0239 {
0240     led->rt2x00dev = rt2x00dev;
0241     led->type = type;
0242     led->led_dev.brightness_set = rt2400pci_brightness_set;
0243     led->led_dev.blink_set = rt2400pci_blink_set;
0244     led->flags = LED_INITIALIZED;
0245 }
0246 #endif /* CONFIG_RT2X00_LIB_LEDS */
0247 
0248 /*
0249  * Configuration handlers.
0250  */
0251 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
0252                     const unsigned int filter_flags)
0253 {
0254     u32 reg;
0255 
0256     /*
0257      * Start configuration steps.
0258      * Note that the version error will always be dropped
0259      * since there is no filter for it at this time.
0260      */
0261     reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
0262     rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
0263                !(filter_flags & FIF_FCSFAIL));
0264     rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
0265                !(filter_flags & FIF_PLCPFAIL));
0266     rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
0267                !(filter_flags & FIF_CONTROL));
0268     rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
0269                !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
0270     rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
0271                !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) &&
0272                !rt2x00dev->intf_ap_count);
0273     rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
0274     rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
0275 }
0276 
0277 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
0278                   struct rt2x00_intf *intf,
0279                   struct rt2x00intf_conf *conf,
0280                   const unsigned int flags)
0281 {
0282     unsigned int bcn_preload;
0283     u32 reg;
0284 
0285     if (flags & CONFIG_UPDATE_TYPE) {
0286         /*
0287          * Enable beacon config
0288          */
0289         bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
0290         reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1);
0291         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
0292         rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
0293 
0294         /*
0295          * Enable synchronisation.
0296          */
0297         reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
0298         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
0299         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
0300     }
0301 
0302     if (flags & CONFIG_UPDATE_MAC)
0303         rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
0304                            conf->mac, sizeof(conf->mac));
0305 
0306     if (flags & CONFIG_UPDATE_BSSID)
0307         rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
0308                            conf->bssid,
0309                            sizeof(conf->bssid));
0310 }
0311 
0312 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
0313                  struct rt2x00lib_erp *erp,
0314                  u32 changed)
0315 {
0316     int preamble_mask;
0317     u32 reg;
0318 
0319     /*
0320      * When short preamble is enabled, we should set bit 0x08
0321      */
0322     if (changed & BSS_CHANGED_ERP_PREAMBLE) {
0323         preamble_mask = erp->short_preamble << 3;
0324 
0325         reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1);
0326         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
0327         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
0328         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
0329         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
0330         rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
0331 
0332         reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2);
0333         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
0334         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
0335         rt2x00_set_field32(&reg, ARCSR2_LENGTH,
0336                    GET_DURATION(ACK_SIZE, 10));
0337         rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
0338 
0339         reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3);
0340         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
0341         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
0342         rt2x00_set_field32(&reg, ARCSR2_LENGTH,
0343                    GET_DURATION(ACK_SIZE, 20));
0344         rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
0345 
0346         reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4);
0347         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
0348         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
0349         rt2x00_set_field32(&reg, ARCSR2_LENGTH,
0350                    GET_DURATION(ACK_SIZE, 55));
0351         rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
0352 
0353         reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5);
0354         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
0355         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
0356         rt2x00_set_field32(&reg, ARCSR2_LENGTH,
0357                    GET_DURATION(ACK_SIZE, 110));
0358         rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
0359     }
0360 
0361     if (changed & BSS_CHANGED_BASIC_RATES)
0362         rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
0363 
0364     if (changed & BSS_CHANGED_ERP_SLOT) {
0365         reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
0366         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
0367         rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
0368 
0369         reg = rt2x00mmio_register_read(rt2x00dev, CSR18);
0370         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
0371         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
0372         rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
0373 
0374         reg = rt2x00mmio_register_read(rt2x00dev, CSR19);
0375         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
0376         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
0377         rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
0378     }
0379 
0380     if (changed & BSS_CHANGED_BEACON_INT) {
0381         reg = rt2x00mmio_register_read(rt2x00dev, CSR12);
0382         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
0383                    erp->beacon_int * 16);
0384         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
0385                    erp->beacon_int * 16);
0386         rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
0387     }
0388 }
0389 
0390 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
0391                  struct antenna_setup *ant)
0392 {
0393     u8 r1;
0394     u8 r4;
0395 
0396     /*
0397      * We should never come here because rt2x00lib is supposed
0398      * to catch this and send us the correct antenna explicitely.
0399      */
0400     BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
0401            ant->tx == ANTENNA_SW_DIVERSITY);
0402 
0403     r4 = rt2400pci_bbp_read(rt2x00dev, 4);
0404     r1 = rt2400pci_bbp_read(rt2x00dev, 1);
0405 
0406     /*
0407      * Configure the TX antenna.
0408      */
0409     switch (ant->tx) {
0410     case ANTENNA_HW_DIVERSITY:
0411         rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
0412         break;
0413     case ANTENNA_A:
0414         rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
0415         break;
0416     case ANTENNA_B:
0417     default:
0418         rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
0419         break;
0420     }
0421 
0422     /*
0423      * Configure the RX antenna.
0424      */
0425     switch (ant->rx) {
0426     case ANTENNA_HW_DIVERSITY:
0427         rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
0428         break;
0429     case ANTENNA_A:
0430         rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
0431         break;
0432     case ANTENNA_B:
0433     default:
0434         rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
0435         break;
0436     }
0437 
0438     rt2400pci_bbp_write(rt2x00dev, 4, r4);
0439     rt2400pci_bbp_write(rt2x00dev, 1, r1);
0440 }
0441 
0442 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
0443                      struct rf_channel *rf)
0444 {
0445     /*
0446      * Switch on tuning bits.
0447      */
0448     rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
0449     rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
0450 
0451     rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
0452     rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
0453     rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
0454 
0455     /*
0456      * RF2420 chipset don't need any additional actions.
0457      */
0458     if (rt2x00_rf(rt2x00dev, RF2420))
0459         return;
0460 
0461     /*
0462      * For the RT2421 chipsets we need to write an invalid
0463      * reference clock rate to activate auto_tune.
0464      * After that we set the value back to the correct channel.
0465      */
0466     rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
0467     rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
0468     rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
0469 
0470     msleep(1);
0471 
0472     rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
0473     rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
0474     rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
0475 
0476     msleep(1);
0477 
0478     /*
0479      * Switch off tuning bits.
0480      */
0481     rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
0482     rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
0483 
0484     rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
0485     rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
0486 
0487     /*
0488      * Clear false CRC during channel switch.
0489      */
0490     rf->rf1 = rt2x00mmio_register_read(rt2x00dev, CNT0);
0491 }
0492 
0493 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
0494 {
0495     rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
0496 }
0497 
0498 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
0499                      struct rt2x00lib_conf *libconf)
0500 {
0501     u32 reg;
0502 
0503     reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
0504     rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
0505                libconf->conf->long_frame_max_tx_count);
0506     rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
0507                libconf->conf->short_frame_max_tx_count);
0508     rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
0509 }
0510 
0511 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
0512                 struct rt2x00lib_conf *libconf)
0513 {
0514     enum dev_state state =
0515         (libconf->conf->flags & IEEE80211_CONF_PS) ?
0516         STATE_SLEEP : STATE_AWAKE;
0517     u32 reg;
0518 
0519     if (state == STATE_SLEEP) {
0520         reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
0521         rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
0522                    (rt2x00dev->beacon_int - 20) * 16);
0523         rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
0524                    libconf->conf->listen_interval - 1);
0525 
0526         /* We must first disable autowake before it can be enabled */
0527         rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
0528         rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
0529 
0530         rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
0531         rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
0532     } else {
0533         reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
0534         rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
0535         rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
0536     }
0537 
0538     rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
0539 }
0540 
0541 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
0542                  struct rt2x00lib_conf *libconf,
0543                  const unsigned int flags)
0544 {
0545     if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
0546         rt2400pci_config_channel(rt2x00dev, &libconf->rf);
0547     if (flags & IEEE80211_CONF_CHANGE_POWER)
0548         rt2400pci_config_txpower(rt2x00dev,
0549                      libconf->conf->power_level);
0550     if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
0551         rt2400pci_config_retry_limit(rt2x00dev, libconf);
0552     if (flags & IEEE80211_CONF_CHANGE_PS)
0553         rt2400pci_config_ps(rt2x00dev, libconf);
0554 }
0555 
0556 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
0557                 const int cw_min, const int cw_max)
0558 {
0559     u32 reg;
0560 
0561     reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
0562     rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
0563     rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
0564     rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
0565 }
0566 
0567 /*
0568  * Link tuning
0569  */
0570 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
0571                  struct link_qual *qual)
0572 {
0573     u32 reg;
0574     u8 bbp;
0575 
0576     /*
0577      * Update FCS error count from register.
0578      */
0579     reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
0580     qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
0581 
0582     /*
0583      * Update False CCA count from register.
0584      */
0585     bbp = rt2400pci_bbp_read(rt2x00dev, 39);
0586     qual->false_cca = bbp;
0587 }
0588 
0589 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
0590                      struct link_qual *qual, u8 vgc_level)
0591 {
0592     if (qual->vgc_level_reg != vgc_level) {
0593         rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
0594         qual->vgc_level = vgc_level;
0595         qual->vgc_level_reg = vgc_level;
0596     }
0597 }
0598 
0599 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
0600                   struct link_qual *qual)
0601 {
0602     rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
0603 }
0604 
0605 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
0606                  struct link_qual *qual, const u32 count)
0607 {
0608     /*
0609      * The link tuner should not run longer then 60 seconds,
0610      * and should run once every 2 seconds.
0611      */
0612     if (count > 60 || !(count & 1))
0613         return;
0614 
0615     /*
0616      * Base r13 link tuning on the false cca count.
0617      */
0618     if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
0619         rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
0620     else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
0621         rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
0622 }
0623 
0624 /*
0625  * Queue handlers.
0626  */
0627 static void rt2400pci_start_queue(struct data_queue *queue)
0628 {
0629     struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
0630     u32 reg;
0631 
0632     switch (queue->qid) {
0633     case QID_RX:
0634         reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
0635         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
0636         rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
0637         break;
0638     case QID_BEACON:
0639         reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
0640         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
0641         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
0642         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
0643         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
0644         break;
0645     default:
0646         break;
0647     }
0648 }
0649 
0650 static void rt2400pci_kick_queue(struct data_queue *queue)
0651 {
0652     struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
0653     u32 reg;
0654 
0655     switch (queue->qid) {
0656     case QID_AC_VO:
0657         reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
0658         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
0659         rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
0660         break;
0661     case QID_AC_VI:
0662         reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
0663         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
0664         rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
0665         break;
0666     case QID_ATIM:
0667         reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
0668         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
0669         rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
0670         break;
0671     default:
0672         break;
0673     }
0674 }
0675 
0676 static void rt2400pci_stop_queue(struct data_queue *queue)
0677 {
0678     struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
0679     u32 reg;
0680 
0681     switch (queue->qid) {
0682     case QID_AC_VO:
0683     case QID_AC_VI:
0684     case QID_ATIM:
0685         reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
0686         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
0687         rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
0688         break;
0689     case QID_RX:
0690         reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
0691         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
0692         rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
0693         break;
0694     case QID_BEACON:
0695         reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
0696         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
0697         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
0698         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
0699         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
0700 
0701         /*
0702          * Wait for possibly running tbtt tasklets.
0703          */
0704         tasklet_kill(&rt2x00dev->tbtt_tasklet);
0705         break;
0706     default:
0707         break;
0708     }
0709 }
0710 
0711 /*
0712  * Initialization functions.
0713  */
0714 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
0715 {
0716     struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
0717     u32 word;
0718 
0719     if (entry->queue->qid == QID_RX) {
0720         word = rt2x00_desc_read(entry_priv->desc, 0);
0721 
0722         return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
0723     } else {
0724         word = rt2x00_desc_read(entry_priv->desc, 0);
0725 
0726         return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
0727                 rt2x00_get_field32(word, TXD_W0_VALID));
0728     }
0729 }
0730 
0731 static void rt2400pci_clear_entry(struct queue_entry *entry)
0732 {
0733     struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
0734     struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
0735     u32 word;
0736 
0737     if (entry->queue->qid == QID_RX) {
0738         word = rt2x00_desc_read(entry_priv->desc, 2);
0739         rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
0740         rt2x00_desc_write(entry_priv->desc, 2, word);
0741 
0742         word = rt2x00_desc_read(entry_priv->desc, 1);
0743         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
0744         rt2x00_desc_write(entry_priv->desc, 1, word);
0745 
0746         word = rt2x00_desc_read(entry_priv->desc, 0);
0747         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
0748         rt2x00_desc_write(entry_priv->desc, 0, word);
0749     } else {
0750         word = rt2x00_desc_read(entry_priv->desc, 0);
0751         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
0752         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
0753         rt2x00_desc_write(entry_priv->desc, 0, word);
0754     }
0755 }
0756 
0757 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
0758 {
0759     struct queue_entry_priv_mmio *entry_priv;
0760     u32 reg;
0761 
0762     /*
0763      * Initialize registers.
0764      */
0765     reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2);
0766     rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
0767     rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
0768     rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
0769     rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
0770     rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
0771 
0772     entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
0773     reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3);
0774     rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
0775                entry_priv->desc_dma);
0776     rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
0777 
0778     entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
0779     reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5);
0780     rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
0781                entry_priv->desc_dma);
0782     rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
0783 
0784     entry_priv = rt2x00dev->atim->entries[0].priv_data;
0785     reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4);
0786     rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
0787                entry_priv->desc_dma);
0788     rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
0789 
0790     entry_priv = rt2x00dev->bcn->entries[0].priv_data;
0791     reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6);
0792     rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
0793                entry_priv->desc_dma);
0794     rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
0795 
0796     reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1);
0797     rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
0798     rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
0799     rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
0800 
0801     entry_priv = rt2x00dev->rx->entries[0].priv_data;
0802     reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2);
0803     rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
0804                entry_priv->desc_dma);
0805     rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
0806 
0807     return 0;
0808 }
0809 
0810 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
0811 {
0812     u32 reg;
0813 
0814     rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
0815     rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
0816     rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20);
0817     rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
0818 
0819     reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR);
0820     rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
0821     rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
0822     rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
0823     rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
0824 
0825     reg = rt2x00mmio_register_read(rt2x00dev, CSR9);
0826     rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
0827                (rt2x00dev->rx->data_size / 128));
0828     rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
0829 
0830     reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
0831     rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
0832     rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
0833     rt2x00_set_field32(&reg, CSR14_TBCN, 0);
0834     rt2x00_set_field32(&reg, CSR14_TCFP, 0);
0835     rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
0836     rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
0837     rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
0838     rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
0839     rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
0840 
0841     rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000);
0842 
0843     reg = rt2x00mmio_register_read(rt2x00dev, ARCSR0);
0844     rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
0845     rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
0846     rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
0847     rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
0848     rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);
0849 
0850     reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3);
0851     rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
0852     rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
0853     rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
0854     rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
0855     rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
0856     rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
0857     rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
0858 
0859     rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
0860 
0861     if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
0862         return -EBUSY;
0863 
0864     rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223);
0865     rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
0866 
0867     reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2);
0868     rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
0869     rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
0870 
0871     reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR);
0872     rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
0873     rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
0874     rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
0875     rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
0876     rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
0877 
0878     reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
0879     rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
0880     rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
0881     rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
0882     rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
0883 
0884     reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
0885     rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
0886     rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
0887     rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
0888 
0889     /*
0890      * We must clear the FCS and FIFO error count.
0891      * These registers are cleared on read,
0892      * so we may pass a useless variable to store the value.
0893      */
0894     reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
0895     reg = rt2x00mmio_register_read(rt2x00dev, CNT4);
0896 
0897     return 0;
0898 }
0899 
0900 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
0901 {
0902     unsigned int i;
0903     u8 value;
0904 
0905     for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
0906         value = rt2400pci_bbp_read(rt2x00dev, 0);
0907         if ((value != 0xff) && (value != 0x00))
0908             return 0;
0909         udelay(REGISTER_BUSY_DELAY);
0910     }
0911 
0912     rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
0913     return -EACCES;
0914 }
0915 
0916 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
0917 {
0918     unsigned int i;
0919     u16 eeprom;
0920     u8 reg_id;
0921     u8 value;
0922 
0923     if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
0924         return -EACCES;
0925 
0926     rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
0927     rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
0928     rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
0929     rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
0930     rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
0931     rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
0932     rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
0933     rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
0934     rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
0935     rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
0936     rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
0937     rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
0938     rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
0939     rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
0940 
0941     for (i = 0; i < EEPROM_BBP_SIZE; i++) {
0942         eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i);
0943 
0944         if (eeprom != 0xffff && eeprom != 0x0000) {
0945             reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
0946             value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
0947             rt2400pci_bbp_write(rt2x00dev, reg_id, value);
0948         }
0949     }
0950 
0951     return 0;
0952 }
0953 
0954 /*
0955  * Device state switch handlers.
0956  */
0957 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
0958                  enum dev_state state)
0959 {
0960     int mask = (state == STATE_RADIO_IRQ_OFF);
0961     u32 reg;
0962     unsigned long flags;
0963 
0964     /*
0965      * When interrupts are being enabled, the interrupt registers
0966      * should clear the register to assure a clean state.
0967      */
0968     if (state == STATE_RADIO_IRQ_ON) {
0969         reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
0970         rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
0971     }
0972 
0973     /*
0974      * Only toggle the interrupts bits we are going to use.
0975      * Non-checked interrupt bits are disabled by default.
0976      */
0977     spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
0978 
0979     reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
0980     rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
0981     rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
0982     rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
0983     rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
0984     rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
0985     rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
0986 
0987     spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
0988 
0989     if (state == STATE_RADIO_IRQ_OFF) {
0990         /*
0991          * Ensure that all tasklets are finished before
0992          * disabling the interrupts.
0993          */
0994         tasklet_kill(&rt2x00dev->txstatus_tasklet);
0995         tasklet_kill(&rt2x00dev->rxdone_tasklet);
0996         tasklet_kill(&rt2x00dev->tbtt_tasklet);
0997     }
0998 }
0999 
1000 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1001 {
1002     /*
1003      * Initialize all registers.
1004      */
1005     if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
1006              rt2400pci_init_registers(rt2x00dev) ||
1007              rt2400pci_init_bbp(rt2x00dev)))
1008         return -EIO;
1009 
1010     return 0;
1011 }
1012 
1013 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1014 {
1015     /*
1016      * Disable power
1017      */
1018     rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
1019 }
1020 
1021 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1022                    enum dev_state state)
1023 {
1024     u32 reg, reg2;
1025     unsigned int i;
1026     char put_to_sleep;
1027     char bbp_state;
1028     char rf_state;
1029 
1030     put_to_sleep = (state != STATE_AWAKE);
1031 
1032     reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1033     rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1034     rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1035     rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1036     rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1037     rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1038 
1039     /*
1040      * Device is not guaranteed to be in the requested state yet.
1041      * We must wait until the register indicates that the
1042      * device has entered the correct state.
1043      */
1044     for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1045         reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1046         bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1047         rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1048         if (bbp_state == state && rf_state == state)
1049             return 0;
1050         rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1051         msleep(10);
1052     }
1053 
1054     return -EBUSY;
1055 }
1056 
1057 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1058                       enum dev_state state)
1059 {
1060     int retval = 0;
1061 
1062     switch (state) {
1063     case STATE_RADIO_ON:
1064         retval = rt2400pci_enable_radio(rt2x00dev);
1065         break;
1066     case STATE_RADIO_OFF:
1067         rt2400pci_disable_radio(rt2x00dev);
1068         break;
1069     case STATE_RADIO_IRQ_ON:
1070     case STATE_RADIO_IRQ_OFF:
1071         rt2400pci_toggle_irq(rt2x00dev, state);
1072         break;
1073     case STATE_DEEP_SLEEP:
1074     case STATE_SLEEP:
1075     case STATE_STANDBY:
1076     case STATE_AWAKE:
1077         retval = rt2400pci_set_state(rt2x00dev, state);
1078         break;
1079     default:
1080         retval = -ENOTSUPP;
1081         break;
1082     }
1083 
1084     if (unlikely(retval))
1085         rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1086                state, retval);
1087 
1088     return retval;
1089 }
1090 
1091 /*
1092  * TX descriptor initialization
1093  */
1094 static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1095                     struct txentry_desc *txdesc)
1096 {
1097     struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1098     struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1099     __le32 *txd = entry_priv->desc;
1100     u32 word;
1101 
1102     /*
1103      * Start writing the descriptor words.
1104      */
1105     word = rt2x00_desc_read(txd, 1);
1106     rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1107     rt2x00_desc_write(txd, 1, word);
1108 
1109     word = rt2x00_desc_read(txd, 2);
1110     rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1111     rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1112     rt2x00_desc_write(txd, 2, word);
1113 
1114     word = rt2x00_desc_read(txd, 3);
1115     rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1116     rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1117     rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1118     rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1119     rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1120     rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1121     rt2x00_desc_write(txd, 3, word);
1122 
1123     word = rt2x00_desc_read(txd, 4);
1124     rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
1125                txdesc->u.plcp.length_low);
1126     rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1127     rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1128     rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
1129                txdesc->u.plcp.length_high);
1130     rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1131     rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1132     rt2x00_desc_write(txd, 4, word);
1133 
1134     /*
1135      * Writing TXD word 0 must the last to prevent a race condition with
1136      * the device, whereby the device may take hold of the TXD before we
1137      * finished updating it.
1138      */
1139     word = rt2x00_desc_read(txd, 0);
1140     rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1141     rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1142     rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1143                test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1144     rt2x00_set_field32(&word, TXD_W0_ACK,
1145                test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1146     rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1147                test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1148     rt2x00_set_field32(&word, TXD_W0_RTS,
1149                test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1150     rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1151     rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1152                test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1153     rt2x00_desc_write(txd, 0, word);
1154 
1155     /*
1156      * Register descriptor details in skb frame descriptor.
1157      */
1158     skbdesc->desc = txd;
1159     skbdesc->desc_len = TXD_DESC_SIZE;
1160 }
1161 
1162 /*
1163  * TX data initialization
1164  */
1165 static void rt2400pci_write_beacon(struct queue_entry *entry,
1166                    struct txentry_desc *txdesc)
1167 {
1168     struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1169     u32 reg;
1170 
1171     /*
1172      * Disable beaconing while we are reloading the beacon data,
1173      * otherwise we might be sending out invalid data.
1174      */
1175     reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
1176     rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1177     rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1178 
1179     if (rt2x00queue_map_txskb(entry)) {
1180         rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
1181         goto out;
1182     }
1183     /*
1184      * Enable beaconing again.
1185      */
1186     rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1187     /*
1188      * Write the TX descriptor for the beacon.
1189      */
1190     rt2400pci_write_tx_desc(entry, txdesc);
1191 
1192     /*
1193      * Dump beacon to userspace through debugfs.
1194      */
1195     rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1196 out:
1197     /*
1198      * Enable beaconing again.
1199      */
1200     rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1201     rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1202 }
1203 
1204 /*
1205  * RX control handlers
1206  */
1207 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1208                   struct rxdone_entry_desc *rxdesc)
1209 {
1210     struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1211     struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1212     u32 word0;
1213     u32 word2;
1214     u32 word3;
1215     u32 word4;
1216     u64 tsf;
1217     u32 rx_low;
1218     u32 rx_high;
1219 
1220     word0 = rt2x00_desc_read(entry_priv->desc, 0);
1221     word2 = rt2x00_desc_read(entry_priv->desc, 2);
1222     word3 = rt2x00_desc_read(entry_priv->desc, 3);
1223     word4 = rt2x00_desc_read(entry_priv->desc, 4);
1224 
1225     if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1226         rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1227     if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1228         rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1229 
1230     /*
1231      * We only get the lower 32bits from the timestamp,
1232      * to get the full 64bits we must complement it with
1233      * the timestamp from get_tsf().
1234      * Note that when a wraparound of the lower 32bits
1235      * has occurred between the frame arrival and the get_tsf()
1236      * call, we must decrease the higher 32bits with 1 to get
1237      * to correct value.
1238      */
1239     tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
1240     rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1241     rx_high = upper_32_bits(tsf);
1242 
1243     if ((u32)tsf <= rx_low)
1244         rx_high--;
1245 
1246     /*
1247      * Obtain the status about this packet.
1248      * The signal is the PLCP value, and needs to be stripped
1249      * of the preamble bit (0x08).
1250      */
1251     rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1252     rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1253     rxdesc->rssi = rt2x00_get_field32(word3, RXD_W3_RSSI) -
1254         entry->queue->rt2x00dev->rssi_offset;
1255     rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1256 
1257     rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1258     if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1259         rxdesc->dev_flags |= RXDONE_MY_BSS;
1260 }
1261 
1262 /*
1263  * Interrupt functions.
1264  */
1265 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1266                  const enum data_queue_qid queue_idx)
1267 {
1268     struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1269     struct queue_entry_priv_mmio *entry_priv;
1270     struct queue_entry *entry;
1271     struct txdone_entry_desc txdesc;
1272     u32 word;
1273 
1274     while (!rt2x00queue_empty(queue)) {
1275         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1276         entry_priv = entry->priv_data;
1277         word = rt2x00_desc_read(entry_priv->desc, 0);
1278 
1279         if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1280             !rt2x00_get_field32(word, TXD_W0_VALID))
1281             break;
1282 
1283         /*
1284          * Obtain the status about this packet.
1285          */
1286         txdesc.flags = 0;
1287         switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1288         case 0: /* Success */
1289         case 1: /* Success with retry */
1290             __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1291             break;
1292         case 2: /* Failure, excessive retries */
1293             __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1294             fallthrough;    /* this is a failed frame! */
1295         default: /* Failure */
1296             __set_bit(TXDONE_FAILURE, &txdesc.flags);
1297         }
1298         txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1299 
1300         rt2x00lib_txdone(entry, &txdesc);
1301     }
1302 }
1303 
1304 static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1305                           struct rt2x00_field32 irq_field)
1306 {
1307     u32 reg;
1308 
1309     /*
1310      * Enable a single interrupt. The interrupt mask register
1311      * access needs locking.
1312      */
1313     spin_lock_irq(&rt2x00dev->irqmask_lock);
1314 
1315     reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1316     rt2x00_set_field32(&reg, irq_field, 0);
1317     rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1318 
1319     spin_unlock_irq(&rt2x00dev->irqmask_lock);
1320 }
1321 
1322 static void rt2400pci_txstatus_tasklet(struct tasklet_struct *t)
1323 {
1324     struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1325                             txstatus_tasklet);
1326     u32 reg;
1327 
1328     /*
1329      * Handle all tx queues.
1330      */
1331     rt2400pci_txdone(rt2x00dev, QID_ATIM);
1332     rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1333     rt2400pci_txdone(rt2x00dev, QID_AC_VI);
1334 
1335     /*
1336      * Enable all TXDONE interrupts again.
1337      */
1338     if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1339         spin_lock_irq(&rt2x00dev->irqmask_lock);
1340 
1341         reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1342         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1343         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1344         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1345         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1346 
1347         spin_unlock_irq(&rt2x00dev->irqmask_lock);
1348     }
1349 }
1350 
1351 static void rt2400pci_tbtt_tasklet(struct tasklet_struct *t)
1352 {
1353     struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet);
1354     rt2x00lib_beacondone(rt2x00dev);
1355     if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1356         rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1357 }
1358 
1359 static void rt2400pci_rxdone_tasklet(struct tasklet_struct *t)
1360 {
1361     struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1362                             rxdone_tasklet);
1363     if (rt2x00mmio_rxdone(rt2x00dev))
1364         tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1365     else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1366         rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1367 }
1368 
1369 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1370 {
1371     struct rt2x00_dev *rt2x00dev = dev_instance;
1372     u32 reg, mask;
1373 
1374     /*
1375      * Get the interrupt sources & saved to local variable.
1376      * Write register value back to clear pending interrupts.
1377      */
1378     reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
1379     rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1380 
1381     if (!reg)
1382         return IRQ_NONE;
1383 
1384     if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1385         return IRQ_HANDLED;
1386 
1387     mask = reg;
1388 
1389     /*
1390      * Schedule tasklets for interrupt handling.
1391      */
1392     if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1393         tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1394 
1395     if (rt2x00_get_field32(reg, CSR7_RXDONE))
1396         tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1397 
1398     if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1399         rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1400         rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1401         tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1402         /*
1403          * Mask out all txdone interrupts.
1404          */
1405         rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1406         rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1407         rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1408     }
1409 
1410     /*
1411      * Disable all interrupts for which a tasklet was scheduled right now,
1412      * the tasklet will reenable the appropriate interrupts.
1413      */
1414     spin_lock(&rt2x00dev->irqmask_lock);
1415 
1416     reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1417     reg |= mask;
1418     rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1419 
1420     spin_unlock(&rt2x00dev->irqmask_lock);
1421 
1422 
1423 
1424     return IRQ_HANDLED;
1425 }
1426 
1427 /*
1428  * Device probe functions.
1429  */
1430 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1431 {
1432     struct eeprom_93cx6 eeprom;
1433     u32 reg;
1434     u16 word;
1435     u8 *mac;
1436 
1437     reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
1438 
1439     eeprom.data = rt2x00dev;
1440     eeprom.register_read = rt2400pci_eepromregister_read;
1441     eeprom.register_write = rt2400pci_eepromregister_write;
1442     eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1443         PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1444     eeprom.reg_data_in = 0;
1445     eeprom.reg_data_out = 0;
1446     eeprom.reg_data_clock = 0;
1447     eeprom.reg_chip_select = 0;
1448 
1449     eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1450                    EEPROM_SIZE / sizeof(u16));
1451 
1452     /*
1453      * Start validation of the data that has been read.
1454      */
1455     mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1456     rt2x00lib_set_mac_address(rt2x00dev, mac);
1457 
1458     word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1459     if (word == 0xffff) {
1460         rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n");
1461         return -EINVAL;
1462     }
1463 
1464     return 0;
1465 }
1466 
1467 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1468 {
1469     u32 reg;
1470     u16 value;
1471     u16 eeprom;
1472 
1473     /*
1474      * Read EEPROM word for configuration.
1475      */
1476     eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1477 
1478     /*
1479      * Identify RF chipset.
1480      */
1481     value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1482     reg = rt2x00mmio_register_read(rt2x00dev, CSR0);
1483     rt2x00_set_chip(rt2x00dev, RT2460, value,
1484             rt2x00_get_field32(reg, CSR0_REVISION));
1485 
1486     if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1487         rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1488         return -ENODEV;
1489     }
1490 
1491     /*
1492      * Identify default antenna configuration.
1493      */
1494     rt2x00dev->default_ant.tx =
1495         rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1496     rt2x00dev->default_ant.rx =
1497         rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1498 
1499     /*
1500      * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1501      * I am not 100% sure about this, but the legacy drivers do not
1502      * indicate antenna swapping in software is required when
1503      * diversity is enabled.
1504      */
1505     if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1506         rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1507     if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1508         rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1509 
1510     /*
1511      * Store led mode, for correct led behaviour.
1512      */
1513 #ifdef CONFIG_RT2X00_LIB_LEDS
1514     value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1515 
1516     rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1517     if (value == LED_MODE_TXRX_ACTIVITY ||
1518         value == LED_MODE_DEFAULT ||
1519         value == LED_MODE_ASUS)
1520         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1521                    LED_TYPE_ACTIVITY);
1522 #endif /* CONFIG_RT2X00_LIB_LEDS */
1523 
1524     /*
1525      * Detect if this device has an hardware controlled radio.
1526      */
1527     if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1528         __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1529 
1530     /*
1531      * Check if the BBP tuning should be enabled.
1532      */
1533     if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1534         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1535 
1536     return 0;
1537 }
1538 
1539 /*
1540  * RF value list for RF2420 & RF2421
1541  * Supports: 2.4 GHz
1542  */
1543 static const struct rf_channel rf_vals_b[] = {
1544     { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1545     { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1546     { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1547     { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1548     { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1549     { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1550     { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1551     { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1552     { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1553     { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1554     { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1555     { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1556     { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1557     { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1558 };
1559 
1560 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1561 {
1562     struct hw_mode_spec *spec = &rt2x00dev->spec;
1563     struct channel_info *info;
1564     char *tx_power;
1565     unsigned int i;
1566 
1567     /*
1568      * Initialize all hw fields.
1569      */
1570     ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
1571     ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
1572     ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
1573     ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
1574 
1575     SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1576     SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1577                 rt2x00_eeprom_addr(rt2x00dev,
1578                            EEPROM_MAC_ADDR_0));
1579 
1580     /*
1581      * Initialize hw_mode information.
1582      */
1583     spec->supported_bands = SUPPORT_BAND_2GHZ;
1584     spec->supported_rates = SUPPORT_RATE_CCK;
1585 
1586     spec->num_channels = ARRAY_SIZE(rf_vals_b);
1587     spec->channels = rf_vals_b;
1588 
1589     /*
1590      * Create channel information array
1591      */
1592     info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1593     if (!info)
1594         return -ENOMEM;
1595 
1596     spec->channels_info = info;
1597 
1598     tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1599     for (i = 0; i < 14; i++) {
1600         info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1601         info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1602     }
1603 
1604     return 0;
1605 }
1606 
1607 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1608 {
1609     int retval;
1610     u32 reg;
1611 
1612     /*
1613      * Allocate eeprom data.
1614      */
1615     retval = rt2400pci_validate_eeprom(rt2x00dev);
1616     if (retval)
1617         return retval;
1618 
1619     retval = rt2400pci_init_eeprom(rt2x00dev);
1620     if (retval)
1621         return retval;
1622 
1623     /*
1624      * Enable rfkill polling by setting GPIO direction of the
1625      * rfkill switch GPIO pin correctly.
1626      */
1627     reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
1628     rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
1629     rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1630 
1631     /*
1632      * Initialize hw specifications.
1633      */
1634     retval = rt2400pci_probe_hw_mode(rt2x00dev);
1635     if (retval)
1636         return retval;
1637 
1638     /*
1639      * This device requires the atim queue and DMA-mapped skbs.
1640      */
1641     __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1642     __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1643     __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1644 
1645     /*
1646      * Set the rssi offset.
1647      */
1648     rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1649 
1650     return 0;
1651 }
1652 
1653 /*
1654  * IEEE80211 stack callback functions.
1655  */
1656 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1657                  struct ieee80211_vif *vif,
1658                  unsigned int link_id, u16 queue,
1659                  const struct ieee80211_tx_queue_params *params)
1660 {
1661     struct rt2x00_dev *rt2x00dev = hw->priv;
1662 
1663     /*
1664      * We don't support variating cw_min and cw_max variables
1665      * per queue. So by default we only configure the TX queue,
1666      * and ignore all other configurations.
1667      */
1668     if (queue != 0)
1669         return -EINVAL;
1670 
1671     if (rt2x00mac_conf_tx(hw, vif, link_id, queue, params))
1672         return -EINVAL;
1673 
1674     /*
1675      * Write configuration to register.
1676      */
1677     rt2400pci_config_cw(rt2x00dev,
1678                 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1679 
1680     return 0;
1681 }
1682 
1683 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
1684                  struct ieee80211_vif *vif)
1685 {
1686     struct rt2x00_dev *rt2x00dev = hw->priv;
1687     u64 tsf;
1688     u32 reg;
1689 
1690     reg = rt2x00mmio_register_read(rt2x00dev, CSR17);
1691     tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1692     reg = rt2x00mmio_register_read(rt2x00dev, CSR16);
1693     tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1694 
1695     return tsf;
1696 }
1697 
1698 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1699 {
1700     struct rt2x00_dev *rt2x00dev = hw->priv;
1701     u32 reg;
1702 
1703     reg = rt2x00mmio_register_read(rt2x00dev, CSR15);
1704     return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1705 }
1706 
1707 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1708     .tx         = rt2x00mac_tx,
1709     .start          = rt2x00mac_start,
1710     .stop           = rt2x00mac_stop,
1711     .add_interface      = rt2x00mac_add_interface,
1712     .remove_interface   = rt2x00mac_remove_interface,
1713     .config         = rt2x00mac_config,
1714     .configure_filter   = rt2x00mac_configure_filter,
1715     .sw_scan_start      = rt2x00mac_sw_scan_start,
1716     .sw_scan_complete   = rt2x00mac_sw_scan_complete,
1717     .get_stats      = rt2x00mac_get_stats,
1718     .bss_info_changed   = rt2x00mac_bss_info_changed,
1719     .conf_tx        = rt2400pci_conf_tx,
1720     .get_tsf        = rt2400pci_get_tsf,
1721     .tx_last_beacon     = rt2400pci_tx_last_beacon,
1722     .rfkill_poll        = rt2x00mac_rfkill_poll,
1723     .flush          = rt2x00mac_flush,
1724     .set_antenna        = rt2x00mac_set_antenna,
1725     .get_antenna        = rt2x00mac_get_antenna,
1726     .get_ringparam      = rt2x00mac_get_ringparam,
1727     .tx_frames_pending  = rt2x00mac_tx_frames_pending,
1728 };
1729 
1730 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1731     .irq_handler        = rt2400pci_interrupt,
1732     .txstatus_tasklet   = rt2400pci_txstatus_tasklet,
1733     .tbtt_tasklet       = rt2400pci_tbtt_tasklet,
1734     .rxdone_tasklet     = rt2400pci_rxdone_tasklet,
1735     .probe_hw       = rt2400pci_probe_hw,
1736     .initialize     = rt2x00mmio_initialize,
1737     .uninitialize       = rt2x00mmio_uninitialize,
1738     .get_entry_state    = rt2400pci_get_entry_state,
1739     .clear_entry        = rt2400pci_clear_entry,
1740     .set_device_state   = rt2400pci_set_device_state,
1741     .rfkill_poll        = rt2400pci_rfkill_poll,
1742     .link_stats     = rt2400pci_link_stats,
1743     .reset_tuner        = rt2400pci_reset_tuner,
1744     .link_tuner     = rt2400pci_link_tuner,
1745     .start_queue        = rt2400pci_start_queue,
1746     .kick_queue     = rt2400pci_kick_queue,
1747     .stop_queue     = rt2400pci_stop_queue,
1748     .flush_queue        = rt2x00mmio_flush_queue,
1749     .write_tx_desc      = rt2400pci_write_tx_desc,
1750     .write_beacon       = rt2400pci_write_beacon,
1751     .fill_rxdone        = rt2400pci_fill_rxdone,
1752     .config_filter      = rt2400pci_config_filter,
1753     .config_intf        = rt2400pci_config_intf,
1754     .config_erp     = rt2400pci_config_erp,
1755     .config_ant     = rt2400pci_config_ant,
1756     .config         = rt2400pci_config,
1757 };
1758 
1759 static void rt2400pci_queue_init(struct data_queue *queue)
1760 {
1761     switch (queue->qid) {
1762     case QID_RX:
1763         queue->limit = 24;
1764         queue->data_size = DATA_FRAME_SIZE;
1765         queue->desc_size = RXD_DESC_SIZE;
1766         queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1767         break;
1768 
1769     case QID_AC_VO:
1770     case QID_AC_VI:
1771     case QID_AC_BE:
1772     case QID_AC_BK:
1773         queue->limit = 24;
1774         queue->data_size = DATA_FRAME_SIZE;
1775         queue->desc_size = TXD_DESC_SIZE;
1776         queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1777         break;
1778 
1779     case QID_BEACON:
1780         queue->limit = 1;
1781         queue->data_size = MGMT_FRAME_SIZE;
1782         queue->desc_size = TXD_DESC_SIZE;
1783         queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1784         break;
1785 
1786     case QID_ATIM:
1787         queue->limit = 8;
1788         queue->data_size = DATA_FRAME_SIZE;
1789         queue->desc_size = TXD_DESC_SIZE;
1790         queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1791         break;
1792 
1793     default:
1794         BUG();
1795         break;
1796     }
1797 }
1798 
1799 static const struct rt2x00_ops rt2400pci_ops = {
1800     .name           = KBUILD_MODNAME,
1801     .max_ap_intf        = 1,
1802     .eeprom_size        = EEPROM_SIZE,
1803     .rf_size        = RF_SIZE,
1804     .tx_queues      = NUM_TX_QUEUES,
1805     .queue_init     = rt2400pci_queue_init,
1806     .lib            = &rt2400pci_rt2x00_ops,
1807     .hw         = &rt2400pci_mac80211_ops,
1808 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1809     .debugfs        = &rt2400pci_rt2x00debug,
1810 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1811 };
1812 
1813 /*
1814  * RT2400pci module information.
1815  */
1816 static const struct pci_device_id rt2400pci_device_table[] = {
1817     { PCI_DEVICE(0x1814, 0x0101) },
1818     { 0, }
1819 };
1820 
1821 
1822 MODULE_AUTHOR(DRV_PROJECT);
1823 MODULE_VERSION(DRV_VERSION);
1824 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1825 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1826 MODULE_LICENSE("GPL");
1827 
1828 static int rt2400pci_probe(struct pci_dev *pci_dev,
1829                const struct pci_device_id *id)
1830 {
1831     return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
1832 }
1833 
1834 static struct pci_driver rt2400pci_driver = {
1835     .name       = KBUILD_MODNAME,
1836     .id_table   = rt2400pci_device_table,
1837     .probe      = rt2400pci_probe,
1838     .remove     = rt2x00pci_remove,
1839     .driver.pm  = &rt2x00pci_pm_ops,
1840 };
1841 
1842 module_pci_driver(rt2400pci_driver);
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