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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /* Copyright (c) 2018 Quantenna Communications */
0003 
0004 #include <linux/kernel.h>
0005 #include <linux/firmware.h>
0006 #include <linux/pci.h>
0007 #include <linux/vmalloc.h>
0008 #include <linux/delay.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/sched.h>
0011 #include <linux/completion.h>
0012 #include <linux/crc32.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/circ_buf.h>
0015 #include <linux/log2.h>
0016 
0017 #include "pcie_priv.h"
0018 #include "pearl_pcie_regs.h"
0019 #include "pearl_pcie_ipc.h"
0020 #include "qtn_hw_ids.h"
0021 #include "core.h"
0022 #include "bus.h"
0023 #include "shm_ipc.h"
0024 #include "debug.h"
0025 
0026 #define PEARL_TX_BD_SIZE_DEFAULT    32
0027 #define PEARL_RX_BD_SIZE_DEFAULT    256
0028 
0029 struct qtnf_pearl_bda {
0030     __le16 bda_len;
0031     __le16 bda_version;
0032     __le32 bda_pci_endian;
0033     __le32 bda_ep_state;
0034     __le32 bda_rc_state;
0035     __le32 bda_dma_mask;
0036     __le32 bda_msi_addr;
0037     __le32 bda_flashsz;
0038     u8 bda_boardname[PCIE_BDA_NAMELEN];
0039     __le32 bda_rc_msi_enabled;
0040     u8 bda_hhbm_list[PCIE_HHBM_MAX_SIZE];
0041     __le32 bda_dsbw_start_index;
0042     __le32 bda_dsbw_end_index;
0043     __le32 bda_dsbw_total_bytes;
0044     __le32 bda_rc_tx_bd_base;
0045     __le32 bda_rc_tx_bd_num;
0046     u8 bda_pcie_mac[QTN_ENET_ADDR_LENGTH];
0047     struct qtnf_shm_ipc_region bda_shm_reg1 __aligned(4096); /* host TX */
0048     struct qtnf_shm_ipc_region bda_shm_reg2 __aligned(4096); /* host RX */
0049 } __packed;
0050 
0051 struct qtnf_pearl_tx_bd {
0052     __le32 addr;
0053     __le32 addr_h;
0054     __le32 info;
0055     __le32 info_h;
0056 } __packed;
0057 
0058 struct qtnf_pearl_rx_bd {
0059     __le32 addr;
0060     __le32 addr_h;
0061     __le32 info;
0062     __le32 info_h;
0063     __le32 next_ptr;
0064     __le32 next_ptr_h;
0065 } __packed;
0066 
0067 struct qtnf_pearl_fw_hdr {
0068     u8 boardflg[8];
0069     __le32 fwsize;
0070     __le32 seqnum;
0071     __le32 type;
0072     __le32 pktlen;
0073     __le32 crc;
0074 } __packed;
0075 
0076 struct qtnf_pcie_pearl_state {
0077     struct qtnf_pcie_bus_priv base;
0078 
0079     /* lock for irq configuration changes */
0080     spinlock_t irq_lock;
0081 
0082     struct qtnf_pearl_bda __iomem *bda;
0083     void __iomem *pcie_reg_base;
0084 
0085     struct qtnf_pearl_tx_bd *tx_bd_vbase;
0086     dma_addr_t tx_bd_pbase;
0087 
0088     struct qtnf_pearl_rx_bd *rx_bd_vbase;
0089     dma_addr_t rx_bd_pbase;
0090 
0091     dma_addr_t bd_table_paddr;
0092     void *bd_table_vaddr;
0093     u32 bd_table_len;
0094     u32 pcie_irq_mask;
0095     u32 pcie_irq_rx_count;
0096     u32 pcie_irq_tx_count;
0097     u32 pcie_irq_uf_count;
0098 };
0099 
0100 static inline void qtnf_init_hdp_irqs(struct qtnf_pcie_pearl_state *ps)
0101 {
0102     unsigned long flags;
0103 
0104     spin_lock_irqsave(&ps->irq_lock, flags);
0105     ps->pcie_irq_mask = (PCIE_HDP_INT_RX_BITS | PCIE_HDP_INT_TX_BITS);
0106     spin_unlock_irqrestore(&ps->irq_lock, flags);
0107 }
0108 
0109 static inline void qtnf_enable_hdp_irqs(struct qtnf_pcie_pearl_state *ps)
0110 {
0111     unsigned long flags;
0112 
0113     spin_lock_irqsave(&ps->irq_lock, flags);
0114     writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
0115     spin_unlock_irqrestore(&ps->irq_lock, flags);
0116 }
0117 
0118 static inline void qtnf_disable_hdp_irqs(struct qtnf_pcie_pearl_state *ps)
0119 {
0120     unsigned long flags;
0121 
0122     spin_lock_irqsave(&ps->irq_lock, flags);
0123     writel(0x0, PCIE_HDP_INT_EN(ps->pcie_reg_base));
0124     spin_unlock_irqrestore(&ps->irq_lock, flags);
0125 }
0126 
0127 static inline void qtnf_en_rxdone_irq(struct qtnf_pcie_pearl_state *ps)
0128 {
0129     unsigned long flags;
0130 
0131     spin_lock_irqsave(&ps->irq_lock, flags);
0132     ps->pcie_irq_mask |= PCIE_HDP_INT_RX_BITS;
0133     writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
0134     spin_unlock_irqrestore(&ps->irq_lock, flags);
0135 }
0136 
0137 static inline void qtnf_dis_rxdone_irq(struct qtnf_pcie_pearl_state *ps)
0138 {
0139     unsigned long flags;
0140 
0141     spin_lock_irqsave(&ps->irq_lock, flags);
0142     ps->pcie_irq_mask &= ~PCIE_HDP_INT_RX_BITS;
0143     writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
0144     spin_unlock_irqrestore(&ps->irq_lock, flags);
0145 }
0146 
0147 static inline void qtnf_en_txdone_irq(struct qtnf_pcie_pearl_state *ps)
0148 {
0149     unsigned long flags;
0150 
0151     spin_lock_irqsave(&ps->irq_lock, flags);
0152     ps->pcie_irq_mask |= PCIE_HDP_INT_TX_BITS;
0153     writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
0154     spin_unlock_irqrestore(&ps->irq_lock, flags);
0155 }
0156 
0157 static inline void qtnf_dis_txdone_irq(struct qtnf_pcie_pearl_state *ps)
0158 {
0159     unsigned long flags;
0160 
0161     spin_lock_irqsave(&ps->irq_lock, flags);
0162     ps->pcie_irq_mask &= ~PCIE_HDP_INT_TX_BITS;
0163     writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
0164     spin_unlock_irqrestore(&ps->irq_lock, flags);
0165 }
0166 
0167 static void qtnf_deassert_intx(struct qtnf_pcie_pearl_state *ps)
0168 {
0169     void __iomem *reg = ps->base.sysctl_bar + PEARL_PCIE_CFG0_OFFSET;
0170     u32 cfg;
0171 
0172     cfg = readl(reg);
0173     cfg &= ~PEARL_ASSERT_INTX;
0174     qtnf_non_posted_write(cfg, reg);
0175 }
0176 
0177 static void qtnf_pearl_reset_ep(struct qtnf_pcie_pearl_state *ps)
0178 {
0179     const u32 data = QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_EP_RESET);
0180     void __iomem *reg = ps->base.sysctl_bar +
0181                 QTN_PEARL_SYSCTL_LHOST_IRQ_OFFSET;
0182 
0183     qtnf_non_posted_write(data, reg);
0184     msleep(QTN_EP_RESET_WAIT_MS);
0185     pci_restore_state(ps->base.pdev);
0186 }
0187 
0188 static void qtnf_pcie_pearl_ipc_gen_ep_int(void *arg)
0189 {
0190     const struct qtnf_pcie_pearl_state *ps = arg;
0191     const u32 data = QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_IPC_IRQ);
0192     void __iomem *reg = ps->base.sysctl_bar +
0193                 QTN_PEARL_SYSCTL_LHOST_IRQ_OFFSET;
0194 
0195     qtnf_non_posted_write(data, reg);
0196 }
0197 
0198 static int qtnf_is_state(__le32 __iomem *reg, u32 state)
0199 {
0200     u32 s = readl(reg);
0201 
0202     return s & state;
0203 }
0204 
0205 static void qtnf_set_state(__le32 __iomem *reg, u32 state)
0206 {
0207     u32 s = readl(reg);
0208 
0209     qtnf_non_posted_write(state | s, reg);
0210 }
0211 
0212 static void qtnf_clear_state(__le32 __iomem *reg, u32 state)
0213 {
0214     u32 s = readl(reg);
0215 
0216     qtnf_non_posted_write(s & ~state, reg);
0217 }
0218 
0219 static int qtnf_poll_state(__le32 __iomem *reg, u32 state, u32 delay_in_ms)
0220 {
0221     u32 timeout = 0;
0222 
0223     while ((qtnf_is_state(reg, state) == 0)) {
0224         usleep_range(1000, 1200);
0225         if (++timeout > delay_in_ms)
0226             return -1;
0227     }
0228 
0229     return 0;
0230 }
0231 
0232 static int pearl_alloc_bd_table(struct qtnf_pcie_pearl_state *ps)
0233 {
0234     struct qtnf_pcie_bus_priv *priv = &ps->base;
0235     dma_addr_t paddr;
0236     void *vaddr;
0237     int len;
0238 
0239     len = priv->tx_bd_num * sizeof(struct qtnf_pearl_tx_bd) +
0240         priv->rx_bd_num * sizeof(struct qtnf_pearl_rx_bd);
0241 
0242     vaddr = dmam_alloc_coherent(&priv->pdev->dev, len, &paddr, GFP_KERNEL);
0243     if (!vaddr)
0244         return -ENOMEM;
0245 
0246     /* tx bd */
0247 
0248     ps->bd_table_vaddr = vaddr;
0249     ps->bd_table_paddr = paddr;
0250     ps->bd_table_len = len;
0251 
0252     ps->tx_bd_vbase = vaddr;
0253     ps->tx_bd_pbase = paddr;
0254 
0255     pr_debug("TX descriptor table: vaddr=0x%p paddr=%pad\n", vaddr, &paddr);
0256 
0257     priv->tx_bd_r_index = 0;
0258     priv->tx_bd_w_index = 0;
0259 
0260     /* rx bd */
0261 
0262     vaddr = ((struct qtnf_pearl_tx_bd *)vaddr) + priv->tx_bd_num;
0263     paddr += priv->tx_bd_num * sizeof(struct qtnf_pearl_tx_bd);
0264 
0265     ps->rx_bd_vbase = vaddr;
0266     ps->rx_bd_pbase = paddr;
0267 
0268 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
0269     writel(QTN_HOST_HI32(paddr),
0270            PCIE_HDP_TX_HOST_Q_BASE_H(ps->pcie_reg_base));
0271 #endif
0272     writel(QTN_HOST_LO32(paddr),
0273            PCIE_HDP_TX_HOST_Q_BASE_L(ps->pcie_reg_base));
0274     writel(priv->rx_bd_num | (sizeof(struct qtnf_pearl_rx_bd)) << 16,
0275            PCIE_HDP_TX_HOST_Q_SZ_CTRL(ps->pcie_reg_base));
0276 
0277     pr_debug("RX descriptor table: vaddr=0x%p paddr=%pad\n", vaddr, &paddr);
0278 
0279     return 0;
0280 }
0281 
0282 static int pearl_skb2rbd_attach(struct qtnf_pcie_pearl_state *ps, u16 index)
0283 {
0284     struct qtnf_pcie_bus_priv *priv = &ps->base;
0285     struct qtnf_pearl_rx_bd *rxbd;
0286     struct sk_buff *skb;
0287     dma_addr_t paddr;
0288 
0289     skb = netdev_alloc_skb_ip_align(NULL, SKB_BUF_SIZE);
0290     if (!skb) {
0291         priv->rx_skb[index] = NULL;
0292         return -ENOMEM;
0293     }
0294 
0295     priv->rx_skb[index] = skb;
0296     rxbd = &ps->rx_bd_vbase[index];
0297 
0298     paddr = dma_map_single(&priv->pdev->dev, skb->data, SKB_BUF_SIZE,
0299                    DMA_FROM_DEVICE);
0300     if (dma_mapping_error(&priv->pdev->dev, paddr)) {
0301         pr_err("skb DMA mapping error: %pad\n", &paddr);
0302         return -ENOMEM;
0303     }
0304 
0305     /* keep rx skb paddrs in rx buffer descriptors for cleanup purposes */
0306     rxbd->addr = cpu_to_le32(QTN_HOST_LO32(paddr));
0307     rxbd->addr_h = cpu_to_le32(QTN_HOST_HI32(paddr));
0308     rxbd->info = 0x0;
0309 
0310     priv->rx_bd_w_index = index;
0311 
0312     /* sync up all descriptor updates */
0313     wmb();
0314 
0315 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
0316     writel(QTN_HOST_HI32(paddr),
0317            PCIE_HDP_HHBM_BUF_PTR_H(ps->pcie_reg_base));
0318 #endif
0319     writel(QTN_HOST_LO32(paddr),
0320            PCIE_HDP_HHBM_BUF_PTR(ps->pcie_reg_base));
0321 
0322     writel(index, PCIE_HDP_TX_HOST_Q_WR_PTR(ps->pcie_reg_base));
0323     return 0;
0324 }
0325 
0326 static int pearl_alloc_rx_buffers(struct qtnf_pcie_pearl_state *ps)
0327 {
0328     u16 i;
0329     int ret = 0;
0330 
0331     memset(ps->rx_bd_vbase, 0x0,
0332            ps->base.rx_bd_num * sizeof(struct qtnf_pearl_rx_bd));
0333 
0334     for (i = 0; i < ps->base.rx_bd_num; i++) {
0335         ret = pearl_skb2rbd_attach(ps, i);
0336         if (ret)
0337             break;
0338     }
0339 
0340     return ret;
0341 }
0342 
0343 /* all rx/tx activity should have ceased before calling this function */
0344 static void qtnf_pearl_free_xfer_buffers(struct qtnf_pcie_pearl_state *ps)
0345 {
0346     struct qtnf_pcie_bus_priv *priv = &ps->base;
0347     struct qtnf_pearl_tx_bd *txbd;
0348     struct qtnf_pearl_rx_bd *rxbd;
0349     struct sk_buff *skb;
0350     dma_addr_t paddr;
0351     int i;
0352 
0353     /* free rx buffers */
0354     for (i = 0; i < priv->rx_bd_num; i++) {
0355         if (priv->rx_skb && priv->rx_skb[i]) {
0356             rxbd = &ps->rx_bd_vbase[i];
0357             skb = priv->rx_skb[i];
0358             paddr = QTN_HOST_ADDR(le32_to_cpu(rxbd->addr_h),
0359                           le32_to_cpu(rxbd->addr));
0360             dma_unmap_single(&priv->pdev->dev, paddr,
0361                      SKB_BUF_SIZE, DMA_FROM_DEVICE);
0362             dev_kfree_skb_any(skb);
0363             priv->rx_skb[i] = NULL;
0364         }
0365     }
0366 
0367     /* free tx buffers */
0368     for (i = 0; i < priv->tx_bd_num; i++) {
0369         if (priv->tx_skb && priv->tx_skb[i]) {
0370             txbd = &ps->tx_bd_vbase[i];
0371             skb = priv->tx_skb[i];
0372             paddr = QTN_HOST_ADDR(le32_to_cpu(txbd->addr_h),
0373                           le32_to_cpu(txbd->addr));
0374             dma_unmap_single(&priv->pdev->dev, paddr, skb->len,
0375                      DMA_TO_DEVICE);
0376             dev_kfree_skb_any(skb);
0377             priv->tx_skb[i] = NULL;
0378         }
0379     }
0380 }
0381 
0382 static int pearl_hhbm_init(struct qtnf_pcie_pearl_state *ps)
0383 {
0384     u32 val;
0385 
0386     val = readl(PCIE_HHBM_CONFIG(ps->pcie_reg_base));
0387     val |= HHBM_CONFIG_SOFT_RESET;
0388     writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base));
0389     usleep_range(50, 100);
0390     val &= ~HHBM_CONFIG_SOFT_RESET;
0391 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
0392     val |= HHBM_64BIT;
0393 #endif
0394     writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base));
0395     writel(ps->base.rx_bd_num, PCIE_HHBM_Q_LIMIT_REG(ps->pcie_reg_base));
0396 
0397     return 0;
0398 }
0399 
0400 static int qtnf_pcie_pearl_init_xfer(struct qtnf_pcie_pearl_state *ps,
0401                      unsigned int tx_bd_size,
0402                      unsigned int rx_bd_size)
0403 {
0404     struct qtnf_pcie_bus_priv *priv = &ps->base;
0405     int ret;
0406     u32 val;
0407 
0408     if (tx_bd_size == 0)
0409         tx_bd_size = PEARL_TX_BD_SIZE_DEFAULT;
0410 
0411     val = tx_bd_size * sizeof(struct qtnf_pearl_tx_bd);
0412 
0413     if (!is_power_of_2(tx_bd_size) || val > PCIE_HHBM_MAX_SIZE) {
0414         pr_warn("invalid tx_bd_size value %u, use default %u\n",
0415             tx_bd_size, PEARL_TX_BD_SIZE_DEFAULT);
0416         priv->tx_bd_num = PEARL_TX_BD_SIZE_DEFAULT;
0417     } else {
0418         priv->tx_bd_num = tx_bd_size;
0419     }
0420 
0421     if (rx_bd_size == 0)
0422         rx_bd_size = PEARL_RX_BD_SIZE_DEFAULT;
0423 
0424     val = rx_bd_size * sizeof(dma_addr_t);
0425 
0426     if (!is_power_of_2(rx_bd_size) || val > PCIE_HHBM_MAX_SIZE) {
0427         pr_warn("invalid rx_bd_size value %u, use default %u\n",
0428             rx_bd_size, PEARL_RX_BD_SIZE_DEFAULT);
0429         priv->rx_bd_num = PEARL_RX_BD_SIZE_DEFAULT;
0430     } else {
0431         priv->rx_bd_num = rx_bd_size;
0432     }
0433 
0434     priv->rx_bd_w_index = 0;
0435     priv->rx_bd_r_index = 0;
0436 
0437     ret = pearl_hhbm_init(ps);
0438     if (ret) {
0439         pr_err("failed to init h/w queues\n");
0440         return ret;
0441     }
0442 
0443     ret = qtnf_pcie_alloc_skb_array(priv);
0444     if (ret) {
0445         pr_err("failed to allocate skb array\n");
0446         return ret;
0447     }
0448 
0449     ret = pearl_alloc_bd_table(ps);
0450     if (ret) {
0451         pr_err("failed to allocate bd table\n");
0452         return ret;
0453     }
0454 
0455     ret = pearl_alloc_rx_buffers(ps);
0456     if (ret) {
0457         pr_err("failed to allocate rx buffers\n");
0458         return ret;
0459     }
0460 
0461     return ret;
0462 }
0463 
0464 static void qtnf_pearl_data_tx_reclaim(struct qtnf_pcie_pearl_state *ps)
0465 {
0466     struct qtnf_pcie_bus_priv *priv = &ps->base;
0467     struct qtnf_pearl_tx_bd *txbd;
0468     struct sk_buff *skb;
0469     unsigned long flags;
0470     dma_addr_t paddr;
0471     u32 tx_done_index;
0472     int count = 0;
0473     int i;
0474 
0475     spin_lock_irqsave(&priv->tx_reclaim_lock, flags);
0476 
0477     tx_done_index = readl(PCIE_HDP_RX0DMA_CNT(ps->pcie_reg_base))
0478             & (priv->tx_bd_num - 1);
0479 
0480     i = priv->tx_bd_r_index;
0481 
0482     while (CIRC_CNT(tx_done_index, i, priv->tx_bd_num)) {
0483         skb = priv->tx_skb[i];
0484         if (likely(skb)) {
0485             txbd = &ps->tx_bd_vbase[i];
0486             paddr = QTN_HOST_ADDR(le32_to_cpu(txbd->addr_h),
0487                           le32_to_cpu(txbd->addr));
0488             dma_unmap_single(&priv->pdev->dev, paddr, skb->len,
0489                      DMA_TO_DEVICE);
0490 
0491             if (skb->dev) {
0492                 dev_sw_netstats_tx_add(skb->dev, 1, skb->len);
0493                 if (unlikely(priv->tx_stopped)) {
0494                     qtnf_wake_all_queues(skb->dev);
0495                     priv->tx_stopped = 0;
0496                 }
0497             }
0498 
0499             dev_kfree_skb_any(skb);
0500         }
0501 
0502         priv->tx_skb[i] = NULL;
0503         count++;
0504 
0505         if (++i >= priv->tx_bd_num)
0506             i = 0;
0507     }
0508 
0509     priv->tx_reclaim_done += count;
0510     priv->tx_reclaim_req++;
0511     priv->tx_bd_r_index = i;
0512 
0513     spin_unlock_irqrestore(&priv->tx_reclaim_lock, flags);
0514 }
0515 
0516 static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_state *ps)
0517 {
0518     struct qtnf_pcie_bus_priv *priv = &ps->base;
0519 
0520     if (!CIRC_SPACE(priv->tx_bd_w_index, priv->tx_bd_r_index,
0521             priv->tx_bd_num)) {
0522         qtnf_pearl_data_tx_reclaim(ps);
0523 
0524         if (!CIRC_SPACE(priv->tx_bd_w_index, priv->tx_bd_r_index,
0525                 priv->tx_bd_num)) {
0526             pr_warn_ratelimited("reclaim full Tx queue\n");
0527             priv->tx_full_count++;
0528             return 0;
0529         }
0530     }
0531 
0532     return 1;
0533 }
0534 
0535 static int qtnf_pcie_skb_send(struct qtnf_bus *bus, struct sk_buff *skb)
0536 {
0537     struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
0538     struct qtnf_pcie_bus_priv *priv = &ps->base;
0539     dma_addr_t txbd_paddr, skb_paddr;
0540     struct qtnf_pearl_tx_bd *txbd;
0541     unsigned long flags;
0542     int len, i;
0543     u32 info;
0544     int ret = 0;
0545 
0546     spin_lock_irqsave(&priv->tx_lock, flags);
0547 
0548     if (!qtnf_tx_queue_ready(ps)) {
0549         if (skb->dev) {
0550             netif_tx_stop_all_queues(skb->dev);
0551             priv->tx_stopped = 1;
0552         }
0553 
0554         spin_unlock_irqrestore(&priv->tx_lock, flags);
0555         return NETDEV_TX_BUSY;
0556     }
0557 
0558     i = priv->tx_bd_w_index;
0559     priv->tx_skb[i] = skb;
0560     len = skb->len;
0561 
0562     skb_paddr = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
0563                    DMA_TO_DEVICE);
0564     if (dma_mapping_error(&priv->pdev->dev, skb_paddr)) {
0565         pr_err("skb DMA mapping error: %pad\n", &skb_paddr);
0566         ret = -ENOMEM;
0567         goto tx_done;
0568     }
0569 
0570     txbd = &ps->tx_bd_vbase[i];
0571     txbd->addr = cpu_to_le32(QTN_HOST_LO32(skb_paddr));
0572     txbd->addr_h = cpu_to_le32(QTN_HOST_HI32(skb_paddr));
0573 
0574     info = (len & QTN_PCIE_TX_DESC_LEN_MASK) << QTN_PCIE_TX_DESC_LEN_SHIFT;
0575     txbd->info = cpu_to_le32(info);
0576 
0577     /* sync up all descriptor updates before passing them to EP */
0578     dma_wmb();
0579 
0580     /* write new TX descriptor to PCIE_RX_FIFO on EP */
0581     txbd_paddr = ps->tx_bd_pbase + i * sizeof(struct qtnf_pearl_tx_bd);
0582 
0583 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
0584     writel(QTN_HOST_HI32(txbd_paddr),
0585            PCIE_HDP_HOST_WR_DESC0_H(ps->pcie_reg_base));
0586 #endif
0587     writel(QTN_HOST_LO32(txbd_paddr),
0588            PCIE_HDP_HOST_WR_DESC0(ps->pcie_reg_base));
0589 
0590     if (++i >= priv->tx_bd_num)
0591         i = 0;
0592 
0593     priv->tx_bd_w_index = i;
0594 
0595 tx_done:
0596     if (ret) {
0597         pr_err_ratelimited("drop skb\n");
0598         if (skb->dev)
0599             skb->dev->stats.tx_dropped++;
0600         dev_kfree_skb_any(skb);
0601     }
0602 
0603     priv->tx_done_count++;
0604     spin_unlock_irqrestore(&priv->tx_lock, flags);
0605 
0606     qtnf_pearl_data_tx_reclaim(ps);
0607 
0608     return NETDEV_TX_OK;
0609 }
0610 
0611 static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb,
0612                  unsigned int macid, unsigned int vifid)
0613 {
0614     return qtnf_pcie_skb_send(bus, skb);
0615 }
0616 
0617 static int qtnf_pcie_data_tx_meta(struct qtnf_bus *bus, struct sk_buff *skb,
0618                   unsigned int macid, unsigned int vifid)
0619 {
0620     struct qtnf_frame_meta_info *meta;
0621     int tail_need = sizeof(*meta) - skb_tailroom(skb);
0622     int ret;
0623 
0624     if (tail_need > 0 && pskb_expand_head(skb, 0, tail_need, GFP_ATOMIC)) {
0625         skb->dev->stats.tx_dropped++;
0626         dev_kfree_skb_any(skb);
0627         return NETDEV_TX_OK;
0628     }
0629 
0630     meta = skb_put(skb, sizeof(*meta));
0631     meta->magic_s = HBM_FRAME_META_MAGIC_PATTERN_S;
0632     meta->magic_e = HBM_FRAME_META_MAGIC_PATTERN_E;
0633     meta->macid = macid;
0634     meta->ifidx = vifid;
0635 
0636     ret = qtnf_pcie_skb_send(bus, skb);
0637     if (unlikely(ret == NETDEV_TX_BUSY))
0638         __skb_trim(skb, skb->len - sizeof(*meta));
0639 
0640     return ret;
0641 }
0642 
0643 static irqreturn_t qtnf_pcie_pearl_interrupt(int irq, void *data)
0644 {
0645     struct qtnf_bus *bus = (struct qtnf_bus *)data;
0646     struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
0647     struct qtnf_pcie_bus_priv *priv = &ps->base;
0648     u32 status;
0649 
0650     priv->pcie_irq_count++;
0651     status = readl(PCIE_HDP_INT_STATUS(ps->pcie_reg_base));
0652 
0653     qtnf_shm_ipc_irq_handler(&priv->shm_ipc_ep_in);
0654     qtnf_shm_ipc_irq_handler(&priv->shm_ipc_ep_out);
0655 
0656     if (!(status & ps->pcie_irq_mask))
0657         goto irq_done;
0658 
0659     if (status & PCIE_HDP_INT_RX_BITS)
0660         ps->pcie_irq_rx_count++;
0661 
0662     if (status & PCIE_HDP_INT_TX_BITS)
0663         ps->pcie_irq_tx_count++;
0664 
0665     if (status & PCIE_HDP_INT_HHBM_UF)
0666         ps->pcie_irq_uf_count++;
0667 
0668     if (status & PCIE_HDP_INT_RX_BITS) {
0669         qtnf_dis_rxdone_irq(ps);
0670         napi_schedule(&bus->mux_napi);
0671     }
0672 
0673     if (status & PCIE_HDP_INT_TX_BITS) {
0674         qtnf_dis_txdone_irq(ps);
0675         tasklet_hi_schedule(&priv->reclaim_tq);
0676     }
0677 
0678 irq_done:
0679     /* H/W workaround: clean all bits, not only enabled */
0680     qtnf_non_posted_write(~0U, PCIE_HDP_INT_STATUS(ps->pcie_reg_base));
0681 
0682     if (!priv->msi_enabled)
0683         qtnf_deassert_intx(ps);
0684 
0685     return IRQ_HANDLED;
0686 }
0687 
0688 static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_state *ps)
0689 {
0690     u16 index = ps->base.rx_bd_r_index;
0691     struct qtnf_pearl_rx_bd *rxbd;
0692     u32 descw;
0693 
0694     rxbd = &ps->rx_bd_vbase[index];
0695     descw = le32_to_cpu(rxbd->info);
0696 
0697     if (descw & QTN_TXDONE_MASK)
0698         return 1;
0699 
0700     return 0;
0701 }
0702 
0703 static int qtnf_pcie_pearl_rx_poll(struct napi_struct *napi, int budget)
0704 {
0705     struct qtnf_bus *bus = container_of(napi, struct qtnf_bus, mux_napi);
0706     struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
0707     struct qtnf_pcie_bus_priv *priv = &ps->base;
0708     struct net_device *ndev = NULL;
0709     struct sk_buff *skb = NULL;
0710     int processed = 0;
0711     struct qtnf_pearl_rx_bd *rxbd;
0712     dma_addr_t skb_paddr;
0713     int consume;
0714     u32 descw;
0715     u32 psize;
0716     u16 r_idx;
0717     u16 w_idx;
0718     int ret;
0719 
0720     while (processed < budget) {
0721         if (!qtnf_rx_data_ready(ps))
0722             goto rx_out;
0723 
0724         r_idx = priv->rx_bd_r_index;
0725         rxbd = &ps->rx_bd_vbase[r_idx];
0726         descw = le32_to_cpu(rxbd->info);
0727 
0728         skb = priv->rx_skb[r_idx];
0729         psize = QTN_GET_LEN(descw);
0730         consume = 1;
0731 
0732         if (!(descw & QTN_TXDONE_MASK)) {
0733             pr_warn("skip invalid rxbd[%d]\n", r_idx);
0734             consume = 0;
0735         }
0736 
0737         if (!skb) {
0738             pr_warn("skip missing rx_skb[%d]\n", r_idx);
0739             consume = 0;
0740         }
0741 
0742         if (skb && (skb_tailroom(skb) <  psize)) {
0743             pr_err("skip packet with invalid length: %u > %u\n",
0744                    psize, skb_tailroom(skb));
0745             consume = 0;
0746         }
0747 
0748         if (skb) {
0749             skb_paddr = QTN_HOST_ADDR(le32_to_cpu(rxbd->addr_h),
0750                           le32_to_cpu(rxbd->addr));
0751             dma_unmap_single(&priv->pdev->dev, skb_paddr,
0752                      SKB_BUF_SIZE, DMA_FROM_DEVICE);
0753         }
0754 
0755         if (consume) {
0756             skb_put(skb, psize);
0757             ndev = qtnf_classify_skb(bus, skb);
0758             if (likely(ndev)) {
0759                 dev_sw_netstats_rx_add(ndev, skb->len);
0760                 skb->protocol = eth_type_trans(skb, ndev);
0761                 napi_gro_receive(napi, skb);
0762             } else {
0763                 pr_debug("drop untagged skb\n");
0764                 bus->mux_dev.stats.rx_dropped++;
0765                 dev_kfree_skb_any(skb);
0766             }
0767         } else {
0768             if (skb) {
0769                 bus->mux_dev.stats.rx_dropped++;
0770                 dev_kfree_skb_any(skb);
0771             }
0772         }
0773 
0774         priv->rx_skb[r_idx] = NULL;
0775         if (++r_idx >= priv->rx_bd_num)
0776             r_idx = 0;
0777 
0778         priv->rx_bd_r_index = r_idx;
0779 
0780         /* repalce processed buffer by a new one */
0781         w_idx = priv->rx_bd_w_index;
0782         while (CIRC_SPACE(priv->rx_bd_w_index, priv->rx_bd_r_index,
0783                   priv->rx_bd_num) > 0) {
0784             if (++w_idx >= priv->rx_bd_num)
0785                 w_idx = 0;
0786 
0787             ret = pearl_skb2rbd_attach(ps, w_idx);
0788             if (ret) {
0789                 pr_err("failed to allocate new rx_skb[%d]\n",
0790                        w_idx);
0791                 break;
0792             }
0793         }
0794 
0795         processed++;
0796     }
0797 
0798 rx_out:
0799     if (processed < budget) {
0800         napi_complete(napi);
0801         qtnf_en_rxdone_irq(ps);
0802     }
0803 
0804     return processed;
0805 }
0806 
0807 static void
0808 qtnf_pcie_data_tx_timeout(struct qtnf_bus *bus, struct net_device *ndev)
0809 {
0810     struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus);
0811 
0812     tasklet_hi_schedule(&ps->base.reclaim_tq);
0813 }
0814 
0815 static void qtnf_pcie_data_rx_start(struct qtnf_bus *bus)
0816 {
0817     struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus);
0818 
0819     qtnf_enable_hdp_irqs(ps);
0820     napi_enable(&bus->mux_napi);
0821 }
0822 
0823 static void qtnf_pcie_data_rx_stop(struct qtnf_bus *bus)
0824 {
0825     struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus);
0826 
0827     napi_disable(&bus->mux_napi);
0828     qtnf_disable_hdp_irqs(ps);
0829 }
0830 
0831 static void qtnf_pearl_tx_use_meta_info_set(struct qtnf_bus *bus, bool use_meta)
0832 {
0833     if (use_meta)
0834         bus->bus_ops->data_tx = qtnf_pcie_data_tx_meta;
0835     else
0836         bus->bus_ops->data_tx = qtnf_pcie_data_tx;
0837 }
0838 
0839 static struct qtnf_bus_ops qtnf_pcie_pearl_bus_ops = {
0840     /* control path methods */
0841     .control_tx = qtnf_pcie_control_tx,
0842 
0843     /* data path methods */
0844     .data_tx        = qtnf_pcie_data_tx,
0845     .data_tx_timeout    = qtnf_pcie_data_tx_timeout,
0846     .data_tx_use_meta_set   = qtnf_pearl_tx_use_meta_info_set,
0847     .data_rx_start      = qtnf_pcie_data_rx_start,
0848     .data_rx_stop       = qtnf_pcie_data_rx_stop,
0849 };
0850 
0851 static int qtnf_dbg_irq_stats(struct seq_file *s, void *data)
0852 {
0853     struct qtnf_bus *bus = dev_get_drvdata(s->private);
0854     struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
0855     u32 reg = readl(PCIE_HDP_INT_EN(ps->pcie_reg_base));
0856     u32 status;
0857 
0858     seq_printf(s, "pcie_irq_count(%u)\n", ps->base.pcie_irq_count);
0859     seq_printf(s, "pcie_irq_tx_count(%u)\n", ps->pcie_irq_tx_count);
0860     status = reg &  PCIE_HDP_INT_TX_BITS;
0861     seq_printf(s, "pcie_irq_tx_status(%s)\n",
0862            (status == PCIE_HDP_INT_TX_BITS) ? "EN" : "DIS");
0863     seq_printf(s, "pcie_irq_rx_count(%u)\n", ps->pcie_irq_rx_count);
0864     status = reg &  PCIE_HDP_INT_RX_BITS;
0865     seq_printf(s, "pcie_irq_rx_status(%s)\n",
0866            (status == PCIE_HDP_INT_RX_BITS) ? "EN" : "DIS");
0867     seq_printf(s, "pcie_irq_uf_count(%u)\n", ps->pcie_irq_uf_count);
0868     status = reg &  PCIE_HDP_INT_HHBM_UF;
0869     seq_printf(s, "pcie_irq_hhbm_uf_status(%s)\n",
0870            (status == PCIE_HDP_INT_HHBM_UF) ? "EN" : "DIS");
0871 
0872     return 0;
0873 }
0874 
0875 static int qtnf_dbg_hdp_stats(struct seq_file *s, void *data)
0876 {
0877     struct qtnf_bus *bus = dev_get_drvdata(s->private);
0878     struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
0879     struct qtnf_pcie_bus_priv *priv = &ps->base;
0880 
0881     seq_printf(s, "tx_full_count(%u)\n", priv->tx_full_count);
0882     seq_printf(s, "tx_done_count(%u)\n", priv->tx_done_count);
0883     seq_printf(s, "tx_reclaim_done(%u)\n", priv->tx_reclaim_done);
0884     seq_printf(s, "tx_reclaim_req(%u)\n", priv->tx_reclaim_req);
0885 
0886     seq_printf(s, "tx_bd_r_index(%u)\n", priv->tx_bd_r_index);
0887     seq_printf(s, "tx_bd_p_index(%u)\n",
0888            readl(PCIE_HDP_RX0DMA_CNT(ps->pcie_reg_base))
0889             & (priv->tx_bd_num - 1));
0890     seq_printf(s, "tx_bd_w_index(%u)\n", priv->tx_bd_w_index);
0891     seq_printf(s, "tx queue len(%u)\n",
0892            CIRC_CNT(priv->tx_bd_w_index, priv->tx_bd_r_index,
0893                 priv->tx_bd_num));
0894 
0895     seq_printf(s, "rx_bd_r_index(%u)\n", priv->rx_bd_r_index);
0896     seq_printf(s, "rx_bd_p_index(%u)\n",
0897            readl(PCIE_HDP_TX0DMA_CNT(ps->pcie_reg_base))
0898             & (priv->rx_bd_num - 1));
0899     seq_printf(s, "rx_bd_w_index(%u)\n", priv->rx_bd_w_index);
0900     seq_printf(s, "rx alloc queue len(%u)\n",
0901            CIRC_SPACE(priv->rx_bd_w_index, priv->rx_bd_r_index,
0902                   priv->rx_bd_num));
0903 
0904     return 0;
0905 }
0906 
0907 static int qtnf_ep_fw_send(struct pci_dev *pdev, uint32_t size,
0908                int blk, const u8 *pblk, const u8 *fw)
0909 {
0910     struct qtnf_bus *bus = pci_get_drvdata(pdev);
0911 
0912     struct qtnf_pearl_fw_hdr *hdr;
0913     u8 *pdata;
0914 
0915     int hds = sizeof(*hdr);
0916     struct sk_buff *skb = NULL;
0917     int len = 0;
0918     int ret;
0919 
0920     skb = __dev_alloc_skb(QTN_PCIE_FW_BUFSZ, GFP_KERNEL);
0921     if (!skb)
0922         return -ENOMEM;
0923 
0924     skb->len = QTN_PCIE_FW_BUFSZ;
0925     skb->dev = NULL;
0926 
0927     hdr = (struct qtnf_pearl_fw_hdr *)skb->data;
0928     memcpy(hdr->boardflg, QTN_PCIE_BOARDFLG, strlen(QTN_PCIE_BOARDFLG));
0929     hdr->fwsize = cpu_to_le32(size);
0930     hdr->seqnum = cpu_to_le32(blk);
0931 
0932     if (blk)
0933         hdr->type = cpu_to_le32(QTN_FW_DSUB);
0934     else
0935         hdr->type = cpu_to_le32(QTN_FW_DBEGIN);
0936 
0937     pdata = skb->data + hds;
0938 
0939     len = QTN_PCIE_FW_BUFSZ - hds;
0940     if (pblk >= (fw + size - len)) {
0941         len = fw + size - pblk;
0942         hdr->type = cpu_to_le32(QTN_FW_DEND);
0943     }
0944 
0945     hdr->pktlen = cpu_to_le32(len);
0946     memcpy(pdata, pblk, len);
0947     hdr->crc = cpu_to_le32(~crc32(0, pdata, len));
0948 
0949     ret = qtnf_pcie_skb_send(bus, skb);
0950 
0951     return (ret == NETDEV_TX_OK) ? len : 0;
0952 }
0953 
0954 static int
0955 qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *ps, const u8 *fw, u32 fw_size)
0956 {
0957     int blk_size = QTN_PCIE_FW_BUFSZ - sizeof(struct qtnf_pearl_fw_hdr);
0958     int blk_count = fw_size / blk_size + ((fw_size % blk_size) ? 1 : 0);
0959     const u8 *pblk = fw;
0960     int threshold = 0;
0961     int blk = 0;
0962     int len;
0963 
0964     pr_debug("FW upload started: fw_addr=0x%p size=%d\n", fw, fw_size);
0965 
0966     while (blk < blk_count) {
0967         if (++threshold > 10000) {
0968             pr_err("FW upload failed: too many retries\n");
0969             return -ETIMEDOUT;
0970         }
0971 
0972         len = qtnf_ep_fw_send(ps->base.pdev, fw_size, blk, pblk, fw);
0973         if (len <= 0)
0974             continue;
0975 
0976         if (!((blk + 1) & QTN_PCIE_FW_DLMASK) ||
0977             (blk == (blk_count - 1))) {
0978             qtnf_set_state(&ps->bda->bda_rc_state,
0979                        QTN_RC_FW_SYNC);
0980             if (qtnf_poll_state(&ps->bda->bda_ep_state,
0981                         QTN_EP_FW_SYNC,
0982                         QTN_FW_DL_TIMEOUT_MS)) {
0983                 pr_err("FW upload failed: SYNC timed out\n");
0984                 return -ETIMEDOUT;
0985             }
0986 
0987             qtnf_clear_state(&ps->bda->bda_ep_state,
0988                      QTN_EP_FW_SYNC);
0989 
0990             if (qtnf_is_state(&ps->bda->bda_ep_state,
0991                       QTN_EP_FW_RETRY)) {
0992                 if (blk == (blk_count - 1)) {
0993                     int last_round =
0994                         blk_count & QTN_PCIE_FW_DLMASK;
0995                     blk -= last_round;
0996                     pblk -= ((last_round - 1) *
0997                         blk_size + len);
0998                 } else {
0999                     blk -= QTN_PCIE_FW_DLMASK;
1000                     pblk -= QTN_PCIE_FW_DLMASK * blk_size;
1001                 }
1002 
1003                 qtnf_clear_state(&ps->bda->bda_ep_state,
1004                          QTN_EP_FW_RETRY);
1005 
1006                 pr_warn("FW upload retry: block #%d\n", blk);
1007                 continue;
1008             }
1009 
1010             qtnf_pearl_data_tx_reclaim(ps);
1011         }
1012 
1013         pblk += len;
1014         blk++;
1015     }
1016 
1017     pr_debug("FW upload completed: totally sent %d blocks\n", blk);
1018     return 0;
1019 }
1020 
1021 static void qtnf_pearl_fw_work_handler(struct work_struct *work)
1022 {
1023     struct qtnf_bus *bus = container_of(work, struct qtnf_bus, fw_work);
1024     struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus);
1025     u32 state = QTN_RC_FW_LOADRDY | QTN_RC_FW_QLINK;
1026     const char *fwname = QTN_PCI_PEARL_FW_NAME;
1027     struct pci_dev *pdev = ps->base.pdev;
1028     const struct firmware *fw;
1029     int ret;
1030 
1031     if (ps->base.flashboot) {
1032         state |= QTN_RC_FW_FLASHBOOT;
1033     } else {
1034         ret = request_firmware(&fw, fwname, &pdev->dev);
1035         if (ret < 0) {
1036             pr_err("failed to get firmware %s\n", fwname);
1037             goto fw_load_exit;
1038         }
1039     }
1040 
1041     qtnf_set_state(&ps->bda->bda_rc_state, state);
1042 
1043     if (qtnf_poll_state(&ps->bda->bda_ep_state, QTN_EP_FW_LOADRDY,
1044                 QTN_FW_DL_TIMEOUT_MS)) {
1045         pr_err("card is not ready\n");
1046 
1047         if (!ps->base.flashboot)
1048             release_firmware(fw);
1049 
1050         goto fw_load_exit;
1051     }
1052 
1053     qtnf_clear_state(&ps->bda->bda_ep_state, QTN_EP_FW_LOADRDY);
1054 
1055     if (ps->base.flashboot) {
1056         pr_info("booting firmware from flash\n");
1057 
1058     } else {
1059         pr_info("starting firmware upload: %s\n", fwname);
1060 
1061         ret = qtnf_ep_fw_load(ps, fw->data, fw->size);
1062         release_firmware(fw);
1063         if (ret) {
1064             pr_err("firmware upload error\n");
1065             goto fw_load_exit;
1066         }
1067     }
1068 
1069     if (qtnf_poll_state(&ps->bda->bda_ep_state, QTN_EP_FW_DONE,
1070                 QTN_FW_DL_TIMEOUT_MS)) {
1071         pr_err("firmware bringup timed out\n");
1072         goto fw_load_exit;
1073     }
1074 
1075     if (qtnf_poll_state(&ps->bda->bda_ep_state,
1076                 QTN_EP_FW_QLINK_DONE, QTN_FW_QLINK_TIMEOUT_MS)) {
1077         pr_err("firmware runtime failure\n");
1078         goto fw_load_exit;
1079     }
1080 
1081     pr_info("firmware is up and running\n");
1082 
1083     ret = qtnf_pcie_fw_boot_done(bus);
1084     if (ret)
1085         goto fw_load_exit;
1086 
1087     qtnf_debugfs_add_entry(bus, "hdp_stats", qtnf_dbg_hdp_stats);
1088     qtnf_debugfs_add_entry(bus, "irq_stats", qtnf_dbg_irq_stats);
1089 
1090 fw_load_exit:
1091     put_device(&pdev->dev);
1092 }
1093 
1094 static void qtnf_pearl_reclaim_tasklet_fn(struct tasklet_struct *t)
1095 {
1096     struct qtnf_pcie_pearl_state *ps = from_tasklet(ps, t, base.reclaim_tq);
1097 
1098     qtnf_pearl_data_tx_reclaim(ps);
1099     qtnf_en_txdone_irq(ps);
1100 }
1101 
1102 static u64 qtnf_pearl_dma_mask_get(void)
1103 {
1104 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1105     return DMA_BIT_MASK(64);
1106 #else
1107     return DMA_BIT_MASK(32);
1108 #endif
1109 }
1110 
1111 static int qtnf_pcie_pearl_probe(struct qtnf_bus *bus, unsigned int tx_bd_size,
1112                  unsigned int rx_bd_size)
1113 {
1114     struct qtnf_shm_ipc_int ipc_int;
1115     struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
1116     struct pci_dev *pdev = ps->base.pdev;
1117     int ret;
1118 
1119     bus->bus_ops = &qtnf_pcie_pearl_bus_ops;
1120     spin_lock_init(&ps->irq_lock);
1121     INIT_WORK(&bus->fw_work, qtnf_pearl_fw_work_handler);
1122 
1123     ps->pcie_reg_base = ps->base.dmareg_bar;
1124     ps->bda = ps->base.epmem_bar;
1125     writel(ps->base.msi_enabled, &ps->bda->bda_rc_msi_enabled);
1126 
1127     ret = qtnf_pcie_pearl_init_xfer(ps, tx_bd_size, rx_bd_size);
1128     if (ret) {
1129         pr_err("PCIE xfer init failed\n");
1130         return ret;
1131     }
1132 
1133     /* init default irq settings */
1134     qtnf_init_hdp_irqs(ps);
1135 
1136     /* start with disabled irqs */
1137     qtnf_disable_hdp_irqs(ps);
1138 
1139     ret = devm_request_irq(&pdev->dev, pdev->irq,
1140                    &qtnf_pcie_pearl_interrupt, 0,
1141                    "qtnf_pearl_irq", (void *)bus);
1142     if (ret) {
1143         pr_err("failed to request pcie irq %d\n", pdev->irq);
1144         qtnf_pearl_free_xfer_buffers(ps);
1145         return ret;
1146     }
1147 
1148     tasklet_setup(&ps->base.reclaim_tq, qtnf_pearl_reclaim_tasklet_fn);
1149     netif_napi_add_weight(&bus->mux_dev, &bus->mux_napi,
1150                   qtnf_pcie_pearl_rx_poll, 10);
1151 
1152     ipc_int.fn = qtnf_pcie_pearl_ipc_gen_ep_int;
1153     ipc_int.arg = ps;
1154     qtnf_pcie_init_shm_ipc(&ps->base, &ps->bda->bda_shm_reg1,
1155                    &ps->bda->bda_shm_reg2, &ipc_int);
1156 
1157     return 0;
1158 }
1159 
1160 static void qtnf_pcie_pearl_remove(struct qtnf_bus *bus)
1161 {
1162     struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus);
1163 
1164     qtnf_pearl_reset_ep(ps);
1165     qtnf_pearl_free_xfer_buffers(ps);
1166 }
1167 
1168 #ifdef CONFIG_PM_SLEEP
1169 static int qtnf_pcie_pearl_suspend(struct qtnf_bus *bus)
1170 {
1171     return -EOPNOTSUPP;
1172 }
1173 
1174 static int qtnf_pcie_pearl_resume(struct qtnf_bus *bus)
1175 {
1176     return 0;
1177 }
1178 #endif
1179 
1180 struct qtnf_bus *qtnf_pcie_pearl_alloc(struct pci_dev *pdev)
1181 {
1182     struct qtnf_bus *bus;
1183     struct qtnf_pcie_pearl_state *ps;
1184 
1185     bus = devm_kzalloc(&pdev->dev, sizeof(*bus) + sizeof(*ps), GFP_KERNEL);
1186     if (!bus)
1187         return NULL;
1188 
1189     ps = get_bus_priv(bus);
1190     ps->base.probe_cb = qtnf_pcie_pearl_probe;
1191     ps->base.remove_cb = qtnf_pcie_pearl_remove;
1192     ps->base.dma_mask_get_cb = qtnf_pearl_dma_mask_get;
1193 #ifdef CONFIG_PM_SLEEP
1194     ps->base.resume_cb = qtnf_pcie_pearl_resume;
1195     ps->base.suspend_cb = qtnf_pcie_pearl_suspend;
1196 #endif
1197 
1198     return bus;
1199 }
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