0001
0002
0003
0004
0005
0006 #define PURELIFI_BYTE_NUM_ALIGNMENT 4
0007 #define ETH_ALEN 6
0008 #define AP_USER_LIMIT 8
0009
0010 #define PLF_VNDR_FPGA_STATE_REQ 0x30
0011 #define PLF_VNDR_FPGA_SET_REQ 0x33
0012 #define PLF_VNDR_FPGA_SET_CMD 0x34
0013 #define PLF_VNDR_FPGA_STATE_CMD 0x35
0014
0015 #define PLF_VNDR_XL_FW_CMD 0x80
0016 #define PLF_VNDR_XL_DATA_CMD 0x81
0017 #define PLF_VNDR_XL_FILE_CMD 0x82
0018 #define PLF_VNDR_XL_EX_CMD 0x83
0019
0020 #define PLF_MAC_VENDOR_REQUEST 0x36
0021 #define PLF_SERIAL_NUMBER_VENDOR_REQUEST 0x37
0022 #define PLF_FIRMWARE_VERSION_VENDOR_REQUEST 0x39
0023 #define PLF_SERIAL_LEN 14
0024 #define PLF_FW_VER_LEN 8
0025
0026 struct rx_status {
0027 __be16 rssi;
0028 u8 rate_idx;
0029 u8 pad;
0030 __be64 crc_error_count;
0031 } __packed;
0032
0033 enum plf_usb_req_enum {
0034 USB_REQ_TEST_WR = 0,
0035 USB_REQ_MAC_WR = 1,
0036 USB_REQ_POWER_WR = 2,
0037 USB_REQ_RXTX_WR = 3,
0038 USB_REQ_BEACON_WR = 4,
0039 USB_REQ_BEACON_INTERVAL_WR = 5,
0040 USB_REQ_RTS_CTS_RATE_WR = 6,
0041 USB_REQ_HASH_WR = 7,
0042 USB_REQ_DATA_TX = 8,
0043 USB_REQ_RATE_WR = 9,
0044 USB_REQ_SET_FREQ = 15
0045 };
0046
0047 struct plf_usb_req {
0048 __be32 id;
0049 __be32 len;
0050 u8 buf[512];
0051 };
0052