microchip/wilc1000/wlan.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
0004  * All rights reserved.
0005  */
0006
0007 #ifndef WILC_WLAN_H
0008 #define WILC_WLAN_H
0009
0010 #include <linux/types.h>
0011 #include <linux/bitfield.h>
0012
0013 /********************************************
0014  *
0015  *      Mac eth header length
0016  *
0017  ********************************************/
0018 #define MAX_MAC_HDR_LEN         26 /* QOS_MAC_HDR_LEN */
0019 #define SUB_MSDU_HEADER_LENGTH      14
0020 #define SNAP_HDR_LEN            8
0021 #define ETHERNET_HDR_LEN        14
0022 #define WORD_ALIGNMENT_PAD      0
0023
0024 #define ETH_ETHERNET_HDR_OFFSET     (MAX_MAC_HDR_LEN + \
0025                      SUB_MSDU_HEADER_LENGTH + \
0026                      SNAP_HDR_LEN - \
0027                      ETHERNET_HDR_LEN + \
0028                      WORD_ALIGNMENT_PAD)
0029
0030 #define HOST_HDR_OFFSET         4
0031 #define ETHERNET_HDR_LEN        14
0032 #define IP_HDR_LEN          20
0033 #define IP_HDR_OFFSET           ETHERNET_HDR_LEN
0034 #define UDP_HDR_OFFSET          (IP_HDR_LEN + IP_HDR_OFFSET)
0035 #define UDP_HDR_LEN         8
0036 #define UDP_DATA_OFFSET         (UDP_HDR_OFFSET + UDP_HDR_LEN)
0037 #define ETH_CONFIG_PKT_HDR_LEN      UDP_DATA_OFFSET
0038
0039 #define ETH_CONFIG_PKT_HDR_OFFSET   (ETH_ETHERNET_HDR_OFFSET + \
0040                      ETH_CONFIG_PKT_HDR_LEN)
0041
0042 /********************************************
0043  *
0044  *      Register Defines
0045  *
0046  ********************************************/
0047 #define WILC_PERIPH_REG_BASE        0x1000
0048 #define WILC_CHANGING_VIR_IF        0x108c
0049 #define WILC_CHIPID         WILC_PERIPH_REG_BASE
0050 #define WILC_GLB_RESET_0        (WILC_PERIPH_REG_BASE + 0x400)
0051 #define WILC_PIN_MUX_0          (WILC_PERIPH_REG_BASE + 0x408)
0052 #define WILC_HOST_TX_CTRL       (WILC_PERIPH_REG_BASE + 0x6c)
0053 #define WILC_HOST_RX_CTRL_0     (WILC_PERIPH_REG_BASE + 0x70)
0054 #define WILC_HOST_RX_CTRL_1     (WILC_PERIPH_REG_BASE + 0x74)
0055 #define WILC_HOST_VMM_CTL       (WILC_PERIPH_REG_BASE + 0x78)
0056 #define WILC_HOST_RX_CTRL       (WILC_PERIPH_REG_BASE + 0x80)
0057 #define WILC_HOST_RX_EXTRA_SIZE     (WILC_PERIPH_REG_BASE + 0x84)
0058 #define WILC_HOST_TX_CTRL_1     (WILC_PERIPH_REG_BASE + 0x88)
0059 #define WILC_MISC           (WILC_PERIPH_REG_BASE + 0x428)
0060 #define WILC_INTR_REG_BASE      (WILC_PERIPH_REG_BASE + 0xa00)
0061 #define WILC_INTR_ENABLE        WILC_INTR_REG_BASE
0062 #define WILC_INTR2_ENABLE       (WILC_INTR_REG_BASE + 4)
0063
0064 #define WILC_INTR_POLARITY      (WILC_INTR_REG_BASE + 0x10)
0065 #define WILC_INTR_TYPE          (WILC_INTR_REG_BASE + 0x20)
0066 #define WILC_INTR_CLEAR         (WILC_INTR_REG_BASE + 0x30)
0067 #define WILC_INTR_STATUS        (WILC_INTR_REG_BASE + 0x40)
0068
0069 #define WILC_RF_REVISION_ID     0x13f4
0070
0071 #define WILC_VMM_TBL_SIZE       64
0072 #define WILC_VMM_TX_TBL_BASE        0x150400
0073 #define WILC_VMM_RX_TBL_BASE        0x150500
0074
0075 #define WILC_VMM_BASE           0x150000
0076 #define WILC_VMM_CORE_CTL       WILC_VMM_BASE
0077 #define WILC_VMM_TBL_CTL        (WILC_VMM_BASE + 0x4)
0078 #define WILC_VMM_TBL_ENTRY      (WILC_VMM_BASE + 0x8)
0079 #define WILC_VMM_TBL0_SIZE      (WILC_VMM_BASE + 0xc)
0080 #define WILC_VMM_TO_HOST_SIZE       (WILC_VMM_BASE + 0x10)
0081 #define WILC_VMM_CORE_CFG       (WILC_VMM_BASE + 0x14)
0082 #define WILC_VMM_TBL_ACTIVE     (WILC_VMM_BASE + 040)
0083 #define WILC_VMM_TBL_STATUS     (WILC_VMM_BASE + 0x44)
0084
0085 #define WILC_SPI_REG_BASE       0xe800
0086 #define WILC_SPI_CTL            WILC_SPI_REG_BASE
0087 #define WILC_SPI_MASTER_DMA_ADDR    (WILC_SPI_REG_BASE + 0x4)
0088 #define WILC_SPI_MASTER_DMA_COUNT   (WILC_SPI_REG_BASE + 0x8)
0089 #define WILC_SPI_SLAVE_DMA_ADDR     (WILC_SPI_REG_BASE + 0xc)
0090 #define WILC_SPI_SLAVE_DMA_COUNT    (WILC_SPI_REG_BASE + 0x10)
0091 #define WILC_SPI_TX_MODE        (WILC_SPI_REG_BASE + 0x20)
0092 #define WILC_SPI_PROTOCOL_CONFIG    (WILC_SPI_REG_BASE + 0x24)
0093 #define WILC_SPI_INTR_CTL       (WILC_SPI_REG_BASE + 0x2c)
0094 #define WILC_SPI_INT_STATUS     (WILC_SPI_REG_BASE + 0x40)
0095 #define WILC_SPI_INT_CLEAR      (WILC_SPI_REG_BASE + 0x44)
0096
0097 #define WILC_SPI_WAKEUP_REG     0x1
0098 #define WILC_SPI_WAKEUP_BIT     BIT(1)
0099
0100 #define WILC_SPI_CLK_STATUS_REG        0x0f
0101 #define WILC_SPI_CLK_STATUS_BIT        BIT(2)
0102 #define WILC_SPI_HOST_TO_FW_REG     0x0b
0103 #define WILC_SPI_HOST_TO_FW_BIT     BIT(0)
0104
0105 #define WILC_SPI_FW_TO_HOST_REG     0x10
0106 #define WILC_SPI_FW_TO_HOST_BIT     BIT(0)
0107
0108 #define WILC_SPI_PROTOCOL_OFFSET    (WILC_SPI_PROTOCOL_CONFIG - \
0109                      WILC_SPI_REG_BASE)
0110
0111 #define WILC_SPI_CLOCKLESS_ADDR_LIMIT   0x30
0112
0113 /* Functions IO enables bits */
0114 #define WILC_SDIO_CCCR_IO_EN_FUNC1  BIT(1)
0115
0116 /* Function/Interrupt enables bits */
0117 #define WILC_SDIO_CCCR_IEN_MASTER   BIT(0)
0118 #define WILC_SDIO_CCCR_IEN_FUNC1    BIT(1)
0119
0120 /* Abort CCCR register bits */
0121 #define WILC_SDIO_CCCR_ABORT_RESET  BIT(3)
0122
0123 /* Vendor specific CCCR registers */
0124 #define WILC_SDIO_WAKEUP_REG        0xf0
0125 #define WILC_SDIO_WAKEUP_BIT        BIT(0)
0126
0127 #define WILC_SDIO_CLK_STATUS_REG    0xf1
0128 #define WILC_SDIO_CLK_STATUS_BIT    BIT(0)
0129
0130 #define WILC_SDIO_INTERRUPT_DATA_SZ_REG 0xf2 /* Read size (2 bytes) */
0131
0132 #define WILC_SDIO_VMM_TBL_CTRL_REG  0xf6
0133 #define WILC_SDIO_IRQ_FLAG_REG      0xf7
0134 #define WILC_SDIO_IRQ_CLEAR_FLAG_REG    0xf8
0135
0136 #define WILC_SDIO_HOST_TO_FW_REG    0xfa
0137 #define WILC_SDIO_HOST_TO_FW_BIT    BIT(0)
0138
0139 #define WILC_SDIO_FW_TO_HOST_REG    0xfc
0140 #define WILC_SDIO_FW_TO_HOST_BIT    BIT(0)
0141
0142 /* Function 1 specific FBR register */
0143 #define WILC_SDIO_FBR_CSA_REG       0x10C /* CSA pointer (3 bytes) */
0144 #define WILC_SDIO_FBR_DATA_REG      0x10F
0145
0146 #define WILC_SDIO_F1_DATA_REG       0x0
0147 #define WILC_SDIO_EXT_IRQ_FLAG_REG  0x4
0148
0149 #define WILC_AHB_DATA_MEM_BASE      0x30000
0150 #define WILC_AHB_SHARE_MEM_BASE     0xd0000
0151
0152 #define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE
0153 #define WILC_VMM_TBL_RX_SHADOW_SIZE 256
0154
0155 #define WILC_FW_HOST_COMM       0x13c0
0156 #define WILC_GP_REG_0           0x149c
0157 #define WILC_GP_REG_1           0x14a0
0158
0159 #define WILC_HAVE_SDIO_IRQ_GPIO     BIT(0)
0160 #define WILC_HAVE_USE_PMU       BIT(1)
0161 #define WILC_HAVE_SLEEP_CLK_SRC_RTC BIT(2)
0162 #define WILC_HAVE_SLEEP_CLK_SRC_XO  BIT(3)
0163 #define WILC_HAVE_EXT_PA_INV_TX_RX  BIT(4)
0164 #define WILC_HAVE_LEGACY_RF_SETTINGS    BIT(5)
0165 #define WILC_HAVE_XTAL_24       BIT(6)
0166 #define WILC_HAVE_DISABLE_WILC_UART BIT(7)
0167 #define WILC_HAVE_USE_IRQ_AS_HOST_WAKE  BIT(8)
0168
0169 #define WILC_CORTUS_INTERRUPT_BASE  0x10A8
0170 #define WILC_CORTUS_INTERRUPT_1     (WILC_CORTUS_INTERRUPT_BASE + 0x4)
0171 #define WILC_CORTUS_INTERRUPT_2     (WILC_CORTUS_INTERRUPT_BASE + 0x8)
0172
0173 /* tx control register 1 to 4 for RX */
0174 #define WILC_REG_4_TO_1_RX      0x1e1c
0175
0176 /* tx control register 1 to 4 for TX Bank_0 */
0177 #define WILC_REG_4_TO_1_TX_BANK0    0x1e9c
0178
0179 #define WILC_CORTUS_RESET_MUX_SEL   0x1118
0180 #define WILC_CORTUS_BOOT_REGISTER   0xc0000
0181
0182 #define WILC_CORTUS_BOOT_FROM_IRAM  0x71
0183
0184 #define WILC_1000_BASE_ID       0x100000
0185
0186 #define WILC_1000_BASE_ID_2A        0x1002A0
0187 #define WILC_1000_BASE_ID_2A_REV1   (WILC_1000_BASE_ID_2A + 1)
0188
0189 #define WILC_1000_BASE_ID_2B        0x1002B0
0190 #define WILC_1000_BASE_ID_2B_REV1   (WILC_1000_BASE_ID_2B + 1)
0191 #define WILC_1000_BASE_ID_2B_REV2   (WILC_1000_BASE_ID_2B + 2)
0192
0193 #define WILC_CHIP_REV_FIELD     GENMASK(11, 0)
0194
0195 /********************************************
0196  *
0197  *      Wlan Defines
0198  *
0199  ********************************************/
0200 #define WILC_CFG_PKT        1
0201 #define WILC_NET_PKT        0
0202 #define WILC_MGMT_PKT       2
0203
0204 #define WILC_CFG_SET        1
0205 #define WILC_CFG_QUERY      0
0206
0207 #define WILC_CFG_RSP        1
0208 #define WILC_CFG_RSP_STATUS 2
0209 #define WILC_CFG_RSP_SCAN   3
0210
0211 #define WILC_ABORT_REQ_BIT      BIT(31)
0212
0213 #define WILC_RX_BUFF_SIZE   (96 * 1024)
0214 #define WILC_TX_BUFF_SIZE   (64 * 1024)
0215
0216 #define NQUEUES         4
0217 #define AC_BUFFER_SIZE      1000
0218
0219 #define VO_AC_COUNT_FIELD       GENMASK(31, 25)
0220 #define VO_AC_ACM_STAT_FIELD        BIT(24)
0221 #define VI_AC_COUNT_FIELD       GENMASK(23, 17)
0222 #define VI_AC_ACM_STAT_FIELD        BIT(16)
0223 #define BE_AC_COUNT_FIELD       GENMASK(15, 9)
0224 #define BE_AC_ACM_STAT_FIELD        BIT(8)
0225 #define BK_AC_COUNT_FIELD       GENMASK(7, 3)
0226 #define BK_AC_ACM_STAT_FIELD        BIT(1)
0227
0228 #define WILC_PKT_HDR_CONFIG_FIELD   BIT(31)
0229 #define WILC_PKT_HDR_OFFSET_FIELD   GENMASK(30, 22)
0230 #define WILC_PKT_HDR_TOTAL_LEN_FIELD    GENMASK(21, 11)
0231 #define WILC_PKT_HDR_LEN_FIELD      GENMASK(10, 0)
0232
0233 #define WILC_INTERRUPT_DATA_SIZE    GENMASK(14, 0)
0234
0235 #define WILC_VMM_BUFFER_SIZE        GENMASK(9, 0)
0236
0237 #define WILC_VMM_HDR_TYPE       BIT(31)
0238 #define WILC_VMM_HDR_MGMT_FIELD     BIT(30)
0239 #define WILC_VMM_HDR_PKT_SIZE       GENMASK(29, 15)
0240 #define WILC_VMM_HDR_BUFF_SIZE      GENMASK(14, 0)
0241
0242 #define WILC_VMM_ENTRY_COUNT        GENMASK(8, 3)
0243 #define WILC_VMM_ENTRY_AVAILABLE    BIT(2)
0244 /*******************************************/
0245 /*        E0 and later Interrupt flags.    */
0246 /*******************************************/
0247 /*******************************************/
0248 /*        E0 and later Interrupt flags.    */
0249 /*           IRQ Status word               */
0250 /* 15:0 = DMA count in words.              */
0251 /* 16: INT0 flag                           */
0252 /* 17: INT1 flag                           */
0253 /* 18: INT2 flag                           */
0254 /* 19: INT3 flag                           */
0255 /* 20: INT4 flag                           */
0256 /* 21: INT5 flag                           */
0257 /*******************************************/
0258 #define IRG_FLAGS_OFFSET    16
0259 #define IRQ_DMA_WD_CNT_MASK GENMASK(IRG_FLAGS_OFFSET - 1, 0)
0260 #define INT_0           BIT(IRG_FLAGS_OFFSET)
0261 #define INT_1           BIT(IRG_FLAGS_OFFSET + 1)
0262 #define INT_2           BIT(IRG_FLAGS_OFFSET + 2)
0263 #define INT_3           BIT(IRG_FLAGS_OFFSET + 3)
0264 #define INT_4           BIT(IRG_FLAGS_OFFSET + 4)
0265 #define INT_5           BIT(IRG_FLAGS_OFFSET + 5)
0266 #define MAX_NUM_INT     5
0267 #define IRG_FLAGS_MASK      GENMASK(IRG_FLAGS_OFFSET + MAX_NUM_INT, \
0268                     IRG_FLAGS_OFFSET)
0269
0270 /*******************************************/
0271 /*        E0 and later Interrupt flags.    */
0272 /*           IRQ Clear word                */
0273 /* 0: Clear INT0                           */
0274 /* 1: Clear INT1                           */
0275 /* 2: Clear INT2                           */
0276 /* 3: Clear INT3                           */
0277 /* 4: Clear INT4                           */
0278 /* 5: Clear INT5                           */
0279 /* 6: Select VMM table 1                   */
0280 /* 7: Select VMM table 2                   */
0281 /* 8: Enable VMM                           */
0282 /*******************************************/
0283 #define CLR_INT0        BIT(0)
0284 #define CLR_INT1        BIT(1)
0285 #define CLR_INT2        BIT(2)
0286 #define CLR_INT3        BIT(3)
0287 #define CLR_INT4        BIT(4)
0288 #define CLR_INT5        BIT(5)
0289 #define SEL_VMM_TBL0        BIT(6)
0290 #define SEL_VMM_TBL1        BIT(7)
0291 #define EN_VMM          BIT(8)
0292
0293 #define DATA_INT_EXT        INT_0
0294 #define ALL_INT_EXT     DATA_INT_EXT
0295 #define NUM_INT_EXT     1
0296 #define UNHANDLED_IRQ_MASK  GENMASK(MAX_NUM_INT - 1, NUM_INT_EXT)
0297
0298 #define DATA_INT_CLR        CLR_INT0
0299
0300 #define ENABLE_RX_VMM       (SEL_VMM_TBL1 | EN_VMM)
0301 #define ENABLE_TX_VMM       (SEL_VMM_TBL0 | EN_VMM)
0302 /* time for expiring the completion of cfg packets */
0303 #define WILC_CFG_PKTS_TIMEOUT   msecs_to_jiffies(3000)
0304
0305 #define IS_MANAGMEMENT      0x100
0306 #define IS_MANAGMEMENT_CALLBACK 0x080
0307 #define IS_MGMT_STATUS_SUCCES   0x040
0308 #define IS_MGMT_AUTH_PKT       0x010
0309
0310 #define WILC_WID_TYPE       GENMASK(15, 12)
0311 #define WILC_VMM_ENTRY_FULL_RETRY   1
0312 /********************************************
0313  *
0314  *      Tx/Rx Queue Structure
0315  *
0316  ********************************************/
0317 enum ip_pkt_priority {
0318     AC_VO_Q = 0,
0319     AC_VI_Q = 1,
0320     AC_BE_Q = 2,
0321     AC_BK_Q = 3
0322 };
0323
0324 struct txq_entry_t {
0325     struct list_head list;
0326     int type;
0327     u8 q_num;
0328     int ack_idx;
0329     u8 *buffer;
0330     int buffer_size;
0331     void *priv;
0332     int status;
0333     struct wilc_vif *vif;
0334     void (*tx_complete_func)(void *priv, int status);
0335 };
0336
0337 struct txq_fw_recv_queue_stat {
0338     u8 acm;
0339     u8 count;
0340 };
0341
0342 struct txq_handle {
0343     struct txq_entry_t txq_head;
0344     u16 count;
0345     struct txq_fw_recv_queue_stat fw;
0346 };
0347
0348 struct rxq_entry_t {
0349     struct list_head list;
0350     u8 *buffer;
0351     int buffer_size;
0352 };
0353
0354 /********************************************
0355  *
0356  *      Host IF Structure
0357  *
0358  ********************************************/
0359 struct wilc;
0360 struct wilc_hif_func {
0361     int (*hif_init)(struct wilc *wilc, bool resume);
0362     int (*hif_deinit)(struct wilc *wilc);
0363     int (*hif_read_reg)(struct wilc *wilc, u32 addr, u32 *data);
0364     int (*hif_write_reg)(struct wilc *wilc, u32 addr, u32 data);
0365     int (*hif_block_rx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
0366     int (*hif_block_tx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
0367     int (*hif_read_int)(struct wilc *wilc, u32 *int_status);
0368     int (*hif_clear_int_ext)(struct wilc *wilc, u32 val);
0369     int (*hif_read_size)(struct wilc *wilc, u32 *size);
0370     int (*hif_block_tx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
0371     int (*hif_block_rx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
0372     int (*hif_sync_ext)(struct wilc *wilc, int nint);
0373     int (*enable_interrupt)(struct wilc *nic);
0374     void (*disable_interrupt)(struct wilc *nic);
0375     int (*hif_reset)(struct wilc *wilc);
0376     bool (*hif_is_init)(struct wilc *wilc);
0377 };
0378
0379 #define WILC_MAX_CFG_FRAME_SIZE     1468
0380
0381 struct tx_complete_data {
0382     int size;
0383     void *buff;
0384     struct sk_buff *skb;
0385 };
0386
0387 struct wilc_cfg_cmd_hdr {
0388     u8 cmd_type;
0389     u8 seq_no;
0390     __le16 total_len;
0391     __le32 driver_handler;
0392 };
0393
0394 struct wilc_cfg_frame {
0395     struct wilc_cfg_cmd_hdr hdr;
0396     u8 frame[WILC_MAX_CFG_FRAME_SIZE];
0397 };
0398
0399 struct wilc_cfg_rsp {
0400     u8 type;
0401     u8 seq_no;
0402 };
0403
0404 struct wilc_vif;
0405
0406 int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer,
0407                 u32 buffer_size);
0408 int wilc_wlan_start(struct wilc *wilc);
0409 int wilc_wlan_stop(struct wilc *wilc, struct wilc_vif *vif);
0410 int wilc_wlan_txq_add_net_pkt(struct net_device *dev,
0411                   struct tx_complete_data *tx_data, u8 *buffer,
0412                   u32 buffer_size,
0413                   void (*tx_complete_fn)(void *, int));
0414 int wilc_wlan_handle_txq(struct wilc *wl, u32 *txq_count);
0415 void wilc_handle_isr(struct wilc *wilc);
0416 void wilc_wlan_cleanup(struct net_device *dev);
0417 int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer,
0418               u32 buffer_size, int commit, u32 drv_handler);
0419 int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit,
0420               u32 drv_handler);
0421 int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer,
0422                    u32 buffer_size, void (*func)(void *, int));
0423 void wilc_enable_tcp_ack_filter(struct wilc_vif *vif, bool value);
0424 int wilc_wlan_get_num_conn_ifcs(struct wilc *wilc);
0425 netdev_tx_t wilc_mac_xmit(struct sk_buff *skb, struct net_device *dev);
0426
0427 void wilc_wfi_p2p_rx(struct wilc_vif *vif, u8 *buff, u32 size);
0428 bool wilc_wfi_mgmt_frame_rx(struct wilc_vif *vif, u8 *buff, u32 size);
0429 void host_wakeup_notify(struct wilc *wilc);
0430 void host_sleep_notify(struct wilc *wilc);
0431 void chip_allow_sleep(struct wilc *wilc);
0432 void chip_wakeup(struct wilc *wilc);
0433 int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids,
0434              u32 count);
0435 int wilc_wlan_init(struct net_device *dev);
0436 u32 wilc_get_chipid(struct wilc *wilc, bool update);
0437 #endif