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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
0004  * All rights reserved.
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/spi/spi.h>
0009 #include <linux/crc7.h>
0010 #include <linux/crc-itu-t.h>
0011 #include <linux/gpio/consumer.h>
0012 
0013 #include "netdev.h"
0014 #include "cfg80211.h"
0015 
0016 #define SPI_MODALIAS        "wilc1000_spi"
0017 
0018 static bool enable_crc7;    /* protect SPI commands with CRC7 */
0019 module_param(enable_crc7, bool, 0644);
0020 MODULE_PARM_DESC(enable_crc7,
0021          "Enable CRC7 checksum to protect command transfers\n"
0022          "\t\t\tagainst corruption during the SPI transfer.\n"
0023          "\t\t\tCommand transfers are short and the CPU-cycle cost\n"
0024          "\t\t\tof enabling this is small.");
0025 
0026 static bool enable_crc16;   /* protect SPI data with CRC16 */
0027 module_param(enable_crc16, bool, 0644);
0028 MODULE_PARM_DESC(enable_crc16,
0029          "Enable CRC16 checksum to protect data transfers\n"
0030          "\t\t\tagainst corruption during the SPI transfer.\n"
0031          "\t\t\tData transfers can be large and the CPU-cycle cost\n"
0032          "\t\t\tof enabling this may be substantial.");
0033 
0034 /*
0035  * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or
0036  * more zero bytes between the command response and the DATA Start tag
0037  * (0xf3).  This behavior appears to be undocumented in "ATWILC1000
0038  * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4
0039  * zero bytes when the SPI bus operates at 48MHz and none when it
0040  * operates at 1MHz.
0041  */
0042 #define WILC_SPI_RSP_HDR_EXTRA_DATA 8
0043 
0044 struct wilc_spi {
0045     bool isinit;        /* true if SPI protocol has been configured */
0046     bool probing_crc;   /* true if we're probing chip's CRC config */
0047     bool crc7_enabled;  /* true if crc7 is currently enabled */
0048     bool crc16_enabled; /* true if crc16 is currently enabled */
0049     struct wilc_gpios {
0050         struct gpio_desc *enable;   /* ENABLE GPIO or NULL */
0051         struct gpio_desc *reset;    /* RESET GPIO or NULL */
0052     } gpios;
0053 };
0054 
0055 static const struct wilc_hif_func wilc_hif_spi;
0056 
0057 static int wilc_spi_reset(struct wilc *wilc);
0058 
0059 /********************************************
0060  *
0061  *      Spi protocol Function
0062  *
0063  ********************************************/
0064 
0065 #define CMD_DMA_WRITE               0xc1
0066 #define CMD_DMA_READ                0xc2
0067 #define CMD_INTERNAL_WRITE          0xc3
0068 #define CMD_INTERNAL_READ           0xc4
0069 #define CMD_TERMINATE               0xc5
0070 #define CMD_REPEAT              0xc6
0071 #define CMD_DMA_EXT_WRITE           0xc7
0072 #define CMD_DMA_EXT_READ            0xc8
0073 #define CMD_SINGLE_WRITE            0xc9
0074 #define CMD_SINGLE_READ             0xca
0075 #define CMD_RESET               0xcf
0076 
0077 #define SPI_ENABLE_VMM_RETRY_LIMIT      2
0078 
0079 /* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */
0080 #define RSP_START_FIELD             GENMASK(7, 4)
0081 #define RSP_TYPE_FIELD              GENMASK(3, 0)
0082 
0083 /* SPI response values for the response fields: */
0084 #define RSP_START_TAG               0xc
0085 #define RSP_TYPE_FIRST_PACKET           0x1
0086 #define RSP_TYPE_INNER_PACKET           0x2
0087 #define RSP_TYPE_LAST_PACKET            0x3
0088 #define RSP_STATE_NO_ERROR          0x00
0089 
0090 #define PROTOCOL_REG_PKT_SZ_MASK        GENMASK(6, 4)
0091 #define PROTOCOL_REG_CRC16_MASK         GENMASK(3, 3)
0092 #define PROTOCOL_REG_CRC7_MASK          GENMASK(2, 2)
0093 
0094 /*
0095  * The SPI data packet size may be any integer power of two in the
0096  * range from 256 to 8192 bytes.
0097  */
0098 #define DATA_PKT_LOG_SZ_MIN         8   /* 256 B */
0099 #define DATA_PKT_LOG_SZ_MAX         13  /* 8 KiB */
0100 
0101 /*
0102  * Select the data packet size (log2 of number of bytes): Use the
0103  * maximum data packet size.  We only retransmit complete packets, so
0104  * there is no benefit from using smaller data packets.
0105  */
0106 #define DATA_PKT_LOG_SZ             DATA_PKT_LOG_SZ_MAX
0107 #define DATA_PKT_SZ             (1 << DATA_PKT_LOG_SZ)
0108 
0109 #define WILC_SPI_COMMAND_STAT_SUCCESS       0
0110 #define WILC_GET_RESP_HDR_START(h)      (((h) >> 4) & 0xf)
0111 
0112 struct wilc_spi_cmd {
0113     u8 cmd_type;
0114     union {
0115         struct {
0116             u8 addr[3];
0117             u8 crc[];
0118         } __packed simple_cmd;
0119         struct {
0120             u8 addr[3];
0121             u8 size[2];
0122             u8 crc[];
0123         } __packed dma_cmd;
0124         struct {
0125             u8 addr[3];
0126             u8 size[3];
0127             u8 crc[];
0128         } __packed dma_cmd_ext;
0129         struct {
0130             u8 addr[2];
0131             __be32 data;
0132             u8 crc[];
0133         } __packed internal_w_cmd;
0134         struct {
0135             u8 addr[3];
0136             __be32 data;
0137             u8 crc[];
0138         } __packed w_cmd;
0139     } u;
0140 } __packed;
0141 
0142 struct wilc_spi_read_rsp_data {
0143     u8 header;
0144     u8 data[4];
0145     u8 crc[];
0146 } __packed;
0147 
0148 struct wilc_spi_rsp_data {
0149     u8 rsp_cmd_type;
0150     u8 status;
0151     u8 data[];
0152 } __packed;
0153 
0154 struct wilc_spi_special_cmd_rsp {
0155     u8 skip_byte;
0156     u8 rsp_cmd_type;
0157     u8 status;
0158 } __packed;
0159 
0160 static int wilc_parse_gpios(struct wilc *wilc)
0161 {
0162     struct spi_device *spi = to_spi_device(wilc->dev);
0163     struct wilc_spi *spi_priv = wilc->bus_data;
0164     struct wilc_gpios *gpios = &spi_priv->gpios;
0165 
0166     /* get ENABLE pin and deassert it (if it is defined): */
0167     gpios->enable = devm_gpiod_get_optional(&spi->dev,
0168                         "enable", GPIOD_OUT_LOW);
0169     /* get RESET pin and assert it (if it is defined): */
0170     if (gpios->enable) {
0171         /* if enable pin exists, reset must exist as well */
0172         gpios->reset = devm_gpiod_get(&spi->dev,
0173                           "reset", GPIOD_OUT_HIGH);
0174         if (IS_ERR(gpios->reset)) {
0175             dev_err(&spi->dev, "missing reset gpio.\n");
0176             return PTR_ERR(gpios->reset);
0177         }
0178     } else {
0179         gpios->reset = devm_gpiod_get_optional(&spi->dev,
0180                                "reset", GPIOD_OUT_HIGH);
0181     }
0182     return 0;
0183 }
0184 
0185 static void wilc_wlan_power(struct wilc *wilc, bool on)
0186 {
0187     struct wilc_spi *spi_priv = wilc->bus_data;
0188     struct wilc_gpios *gpios = &spi_priv->gpios;
0189 
0190     if (on) {
0191         /* assert ENABLE: */
0192         gpiod_set_value(gpios->enable, 1);
0193         mdelay(5);
0194         /* assert RESET: */
0195         gpiod_set_value(gpios->reset, 1);
0196     } else {
0197         /* deassert RESET: */
0198         gpiod_set_value(gpios->reset, 0);
0199         /* deassert ENABLE: */
0200         gpiod_set_value(gpios->enable, 0);
0201     }
0202 }
0203 
0204 static int wilc_bus_probe(struct spi_device *spi)
0205 {
0206     int ret;
0207     struct wilc *wilc;
0208     struct wilc_spi *spi_priv;
0209 
0210     spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL);
0211     if (!spi_priv)
0212         return -ENOMEM;
0213 
0214     ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi);
0215     if (ret)
0216         goto free;
0217 
0218     spi_set_drvdata(spi, wilc);
0219     wilc->dev = &spi->dev;
0220     wilc->bus_data = spi_priv;
0221     wilc->dev_irq_num = spi->irq;
0222 
0223     ret = wilc_parse_gpios(wilc);
0224     if (ret < 0)
0225         goto netdev_cleanup;
0226 
0227     wilc->rtc_clk = devm_clk_get_optional(&spi->dev, "rtc");
0228     if (IS_ERR(wilc->rtc_clk)) {
0229         ret = PTR_ERR(wilc->rtc_clk);
0230         goto netdev_cleanup;
0231     }
0232     clk_prepare_enable(wilc->rtc_clk);
0233 
0234     return 0;
0235 
0236 netdev_cleanup:
0237     wilc_netdev_cleanup(wilc);
0238 free:
0239     kfree(spi_priv);
0240     return ret;
0241 }
0242 
0243 static void wilc_bus_remove(struct spi_device *spi)
0244 {
0245     struct wilc *wilc = spi_get_drvdata(spi);
0246     struct wilc_spi *spi_priv = wilc->bus_data;
0247 
0248     clk_disable_unprepare(wilc->rtc_clk);
0249     wilc_netdev_cleanup(wilc);
0250     kfree(spi_priv);
0251 }
0252 
0253 static const struct of_device_id wilc_of_match[] = {
0254     { .compatible = "microchip,wilc1000", },
0255     { /* sentinel */ }
0256 };
0257 MODULE_DEVICE_TABLE(of, wilc_of_match);
0258 
0259 static const struct spi_device_id wilc_spi_id[] = {
0260     { "wilc1000", 0 },
0261     { /* sentinel */ }
0262 };
0263 MODULE_DEVICE_TABLE(spi, wilc_spi_id);
0264 
0265 static struct spi_driver wilc_spi_driver = {
0266     .driver = {
0267         .name = SPI_MODALIAS,
0268         .of_match_table = wilc_of_match,
0269     },
0270     .id_table = wilc_spi_id,
0271     .probe =  wilc_bus_probe,
0272     .remove = wilc_bus_remove,
0273 };
0274 module_spi_driver(wilc_spi_driver);
0275 MODULE_LICENSE("GPL");
0276 
0277 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
0278 {
0279     struct spi_device *spi = to_spi_device(wilc->dev);
0280     int ret;
0281     struct spi_message msg;
0282 
0283     if (len > 0 && b) {
0284         struct spi_transfer tr = {
0285             .tx_buf = b,
0286             .len = len,
0287             .delay = {
0288                 .value = 0,
0289                 .unit = SPI_DELAY_UNIT_USECS
0290             },
0291         };
0292         char *r_buffer = kzalloc(len, GFP_KERNEL);
0293 
0294         if (!r_buffer)
0295             return -ENOMEM;
0296 
0297         tr.rx_buf = r_buffer;
0298         dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
0299 
0300         memset(&msg, 0, sizeof(msg));
0301         spi_message_init(&msg);
0302         msg.spi = spi;
0303         spi_message_add_tail(&tr, &msg);
0304 
0305         ret = spi_sync(spi, &msg);
0306         if (ret < 0)
0307             dev_err(&spi->dev, "SPI transaction failed\n");
0308 
0309         kfree(r_buffer);
0310     } else {
0311         dev_err(&spi->dev,
0312             "can't write data with the following length: %d\n",
0313             len);
0314         ret = -EINVAL;
0315     }
0316 
0317     return ret;
0318 }
0319 
0320 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
0321 {
0322     struct spi_device *spi = to_spi_device(wilc->dev);
0323     int ret;
0324 
0325     if (rlen > 0) {
0326         struct spi_message msg;
0327         struct spi_transfer tr = {
0328             .rx_buf = rb,
0329             .len = rlen,
0330             .delay = {
0331                 .value = 0,
0332                 .unit = SPI_DELAY_UNIT_USECS
0333             },
0334 
0335         };
0336         char *t_buffer = kzalloc(rlen, GFP_KERNEL);
0337 
0338         if (!t_buffer)
0339             return -ENOMEM;
0340 
0341         tr.tx_buf = t_buffer;
0342 
0343         memset(&msg, 0, sizeof(msg));
0344         spi_message_init(&msg);
0345         msg.spi = spi;
0346         spi_message_add_tail(&tr, &msg);
0347 
0348         ret = spi_sync(spi, &msg);
0349         if (ret < 0)
0350             dev_err(&spi->dev, "SPI transaction failed\n");
0351         kfree(t_buffer);
0352     } else {
0353         dev_err(&spi->dev,
0354             "can't read data with the following length: %u\n",
0355             rlen);
0356         ret = -EINVAL;
0357     }
0358 
0359     return ret;
0360 }
0361 
0362 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
0363 {
0364     struct spi_device *spi = to_spi_device(wilc->dev);
0365     int ret;
0366 
0367     if (rlen > 0) {
0368         struct spi_message msg;
0369         struct spi_transfer tr = {
0370             .rx_buf = rb,
0371             .tx_buf = wb,
0372             .len = rlen,
0373             .bits_per_word = 8,
0374             .delay = {
0375                 .value = 0,
0376                 .unit = SPI_DELAY_UNIT_USECS
0377             },
0378 
0379         };
0380 
0381         memset(&msg, 0, sizeof(msg));
0382         spi_message_init(&msg);
0383         msg.spi = spi;
0384 
0385         spi_message_add_tail(&tr, &msg);
0386         ret = spi_sync(spi, &msg);
0387         if (ret < 0)
0388             dev_err(&spi->dev, "SPI transaction failed\n");
0389     } else {
0390         dev_err(&spi->dev,
0391             "can't read data with the following length: %u\n",
0392             rlen);
0393         ret = -EINVAL;
0394     }
0395 
0396     return ret;
0397 }
0398 
0399 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
0400 {
0401     struct spi_device *spi = to_spi_device(wilc->dev);
0402     struct wilc_spi *spi_priv = wilc->bus_data;
0403     int ix, nbytes;
0404     int result = 0;
0405     u8 cmd, order, crc[2];
0406     u16 crc_calc;
0407 
0408     /*
0409      * Data
0410      */
0411     ix = 0;
0412     do {
0413         if (sz <= DATA_PKT_SZ) {
0414             nbytes = sz;
0415             order = 0x3;
0416         } else {
0417             nbytes = DATA_PKT_SZ;
0418             if (ix == 0)
0419                 order = 0x1;
0420             else
0421                 order = 0x02;
0422         }
0423 
0424         /*
0425          * Write command
0426          */
0427         cmd = 0xf0;
0428         cmd |= order;
0429 
0430         if (wilc_spi_tx(wilc, &cmd, 1)) {
0431             dev_err(&spi->dev,
0432                 "Failed data block cmd write, bus error...\n");
0433             result = -EINVAL;
0434             break;
0435         }
0436 
0437         /*
0438          * Write data
0439          */
0440         if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
0441             dev_err(&spi->dev,
0442                 "Failed data block write, bus error...\n");
0443             result = -EINVAL;
0444             break;
0445         }
0446 
0447         /*
0448          * Write CRC
0449          */
0450         if (spi_priv->crc16_enabled) {
0451             crc_calc = crc_itu_t(0xffff, &b[ix], nbytes);
0452             crc[0] = crc_calc >> 8;
0453             crc[1] = crc_calc;
0454             if (wilc_spi_tx(wilc, crc, 2)) {
0455                 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
0456                 result = -EINVAL;
0457                 break;
0458             }
0459         }
0460 
0461         /*
0462          * No need to wait for response
0463          */
0464         ix += nbytes;
0465         sz -= nbytes;
0466     } while (sz);
0467 
0468     return result;
0469 }
0470 
0471 /********************************************
0472  *
0473  *      Spi Internal Read/Write Function
0474  *
0475  ********************************************/
0476 static u8 wilc_get_crc7(u8 *buffer, u32 len)
0477 {
0478     return crc7_be(0xfe, buffer, len);
0479 }
0480 
0481 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b,
0482                 u8 clockless)
0483 {
0484     struct spi_device *spi = to_spi_device(wilc->dev);
0485     struct wilc_spi *spi_priv = wilc->bus_data;
0486     u8 wb[32], rb[32];
0487     int cmd_len, resp_len, i;
0488     u16 crc_calc, crc_recv;
0489     struct wilc_spi_cmd *c;
0490     struct wilc_spi_rsp_data *r;
0491     struct wilc_spi_read_rsp_data *r_data;
0492 
0493     memset(wb, 0x0, sizeof(wb));
0494     memset(rb, 0x0, sizeof(rb));
0495     c = (struct wilc_spi_cmd *)wb;
0496     c->cmd_type = cmd;
0497     if (cmd == CMD_SINGLE_READ) {
0498         c->u.simple_cmd.addr[0] = adr >> 16;
0499         c->u.simple_cmd.addr[1] = adr >> 8;
0500         c->u.simple_cmd.addr[2] = adr;
0501     } else if (cmd == CMD_INTERNAL_READ) {
0502         c->u.simple_cmd.addr[0] = adr >> 8;
0503         if (clockless == 1)
0504             c->u.simple_cmd.addr[0] |= BIT(7);
0505         c->u.simple_cmd.addr[1] = adr;
0506         c->u.simple_cmd.addr[2] = 0x0;
0507     } else {
0508         dev_err(&spi->dev, "cmd [%x] not supported\n", cmd);
0509         return -EINVAL;
0510     }
0511 
0512     cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
0513     resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA;
0514 
0515     if (spi_priv->crc7_enabled) {
0516         c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
0517         cmd_len += 1;
0518         resp_len += 2;
0519     }
0520 
0521     if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
0522         dev_err(&spi->dev,
0523             "spi buffer size too small (%d) (%d) (%zu)\n",
0524             cmd_len, resp_len, ARRAY_SIZE(wb));
0525         return -EINVAL;
0526     }
0527 
0528     if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
0529         dev_err(&spi->dev, "Failed cmd write, bus error...\n");
0530         return -EINVAL;
0531     }
0532 
0533     r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
0534     if (r->rsp_cmd_type != cmd && !clockless) {
0535         if (!spi_priv->probing_crc)
0536             dev_err(&spi->dev,
0537                 "Failed cmd, cmd (%02x), resp (%02x)\n",
0538                 cmd, r->rsp_cmd_type);
0539         return -EINVAL;
0540     }
0541 
0542     if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) {
0543         dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
0544             r->status);
0545         return -EINVAL;
0546     }
0547 
0548     for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i)
0549         if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf)
0550             break;
0551 
0552     if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) {
0553         dev_err(&spi->dev, "Error, data start missing\n");
0554         return -EINVAL;
0555     }
0556 
0557     r_data = (struct wilc_spi_read_rsp_data *)&r->data[i];
0558 
0559     if (b)
0560         memcpy(b, r_data->data, 4);
0561 
0562     if (!clockless && spi_priv->crc16_enabled) {
0563         crc_recv = (r_data->crc[0] << 8) | r_data->crc[1];
0564         crc_calc = crc_itu_t(0xffff, r_data->data, 4);
0565         if (crc_recv != crc_calc) {
0566             dev_err(&spi->dev, "%s: bad CRC 0x%04x "
0567                 "(calculated 0x%04x)\n", __func__,
0568                 crc_recv, crc_calc);
0569             return -EINVAL;
0570         }
0571     }
0572 
0573     return 0;
0574 }
0575 
0576 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data,
0577                   u8 clockless)
0578 {
0579     struct spi_device *spi = to_spi_device(wilc->dev);
0580     struct wilc_spi *spi_priv = wilc->bus_data;
0581     u8 wb[32], rb[32];
0582     int cmd_len, resp_len;
0583     struct wilc_spi_cmd *c;
0584     struct wilc_spi_rsp_data *r;
0585 
0586     memset(wb, 0x0, sizeof(wb));
0587     memset(rb, 0x0, sizeof(rb));
0588     c = (struct wilc_spi_cmd *)wb;
0589     c->cmd_type = cmd;
0590     if (cmd == CMD_INTERNAL_WRITE) {
0591         c->u.internal_w_cmd.addr[0] = adr >> 8;
0592         if (clockless == 1)
0593             c->u.internal_w_cmd.addr[0] |= BIT(7);
0594 
0595         c->u.internal_w_cmd.addr[1] = adr;
0596         c->u.internal_w_cmd.data = cpu_to_be32(data);
0597         cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc);
0598         if (spi_priv->crc7_enabled)
0599             c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
0600     } else if (cmd == CMD_SINGLE_WRITE) {
0601         c->u.w_cmd.addr[0] = adr >> 16;
0602         c->u.w_cmd.addr[1] = adr >> 8;
0603         c->u.w_cmd.addr[2] = adr;
0604         c->u.w_cmd.data = cpu_to_be32(data);
0605         cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc);
0606         if (spi_priv->crc7_enabled)
0607             c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
0608     } else {
0609         dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd);
0610         return -EINVAL;
0611     }
0612 
0613     if (spi_priv->crc7_enabled)
0614         cmd_len += 1;
0615 
0616     resp_len = sizeof(*r);
0617 
0618     if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
0619         dev_err(&spi->dev,
0620             "spi buffer size too small (%d) (%d) (%zu)\n",
0621             cmd_len, resp_len, ARRAY_SIZE(wb));
0622         return -EINVAL;
0623     }
0624 
0625     if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
0626         dev_err(&spi->dev, "Failed cmd write, bus error...\n");
0627         return -EINVAL;
0628     }
0629 
0630     r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
0631     /*
0632      * Clockless registers operations might return unexptected responses,
0633      * even if successful.
0634      */
0635     if (r->rsp_cmd_type != cmd && !clockless) {
0636         dev_err(&spi->dev,
0637             "Failed cmd response, cmd (%02x), resp (%02x)\n",
0638             cmd, r->rsp_cmd_type);
0639         return -EINVAL;
0640     }
0641 
0642     if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) {
0643         dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
0644             r->status);
0645         return -EINVAL;
0646     }
0647 
0648     return 0;
0649 }
0650 
0651 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz)
0652 {
0653     struct spi_device *spi = to_spi_device(wilc->dev);
0654     struct wilc_spi *spi_priv = wilc->bus_data;
0655     u16 crc_recv, crc_calc;
0656     u8 wb[32], rb[32];
0657     int cmd_len, resp_len;
0658     int retry, ix = 0;
0659     u8 crc[2];
0660     struct wilc_spi_cmd *c;
0661     struct wilc_spi_rsp_data *r;
0662 
0663     memset(wb, 0x0, sizeof(wb));
0664     memset(rb, 0x0, sizeof(rb));
0665     c = (struct wilc_spi_cmd *)wb;
0666     c->cmd_type = cmd;
0667     if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) {
0668         c->u.dma_cmd.addr[0] = adr >> 16;
0669         c->u.dma_cmd.addr[1] = adr >> 8;
0670         c->u.dma_cmd.addr[2] = adr;
0671         c->u.dma_cmd.size[0] = sz >> 8;
0672         c->u.dma_cmd.size[1] = sz;
0673         cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc);
0674         if (spi_priv->crc7_enabled)
0675             c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
0676     } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) {
0677         c->u.dma_cmd_ext.addr[0] = adr >> 16;
0678         c->u.dma_cmd_ext.addr[1] = adr >> 8;
0679         c->u.dma_cmd_ext.addr[2] = adr;
0680         c->u.dma_cmd_ext.size[0] = sz >> 16;
0681         c->u.dma_cmd_ext.size[1] = sz >> 8;
0682         c->u.dma_cmd_ext.size[2] = sz;
0683         cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc);
0684         if (spi_priv->crc7_enabled)
0685             c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len);
0686     } else {
0687         dev_err(&spi->dev, "dma read write cmd [%x] not supported\n",
0688             cmd);
0689         return -EINVAL;
0690     }
0691     if (spi_priv->crc7_enabled)
0692         cmd_len += 1;
0693 
0694     resp_len = sizeof(*r);
0695 
0696     if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
0697         dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n",
0698             cmd_len, resp_len, ARRAY_SIZE(wb));
0699         return -EINVAL;
0700     }
0701 
0702     if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
0703         dev_err(&spi->dev, "Failed cmd write, bus error...\n");
0704         return -EINVAL;
0705     }
0706 
0707     r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
0708     if (r->rsp_cmd_type != cmd) {
0709         dev_err(&spi->dev,
0710             "Failed cmd response, cmd (%02x), resp (%02x)\n",
0711             cmd, r->rsp_cmd_type);
0712         return -EINVAL;
0713     }
0714 
0715     if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
0716         dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
0717             r->status);
0718         return -EINVAL;
0719     }
0720 
0721     if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE)
0722         return 0;
0723 
0724     while (sz > 0) {
0725         int nbytes;
0726         u8 rsp;
0727 
0728         nbytes = min_t(u32, sz, DATA_PKT_SZ);
0729 
0730         /*
0731          * Data Response header
0732          */
0733         retry = 100;
0734         do {
0735             if (wilc_spi_rx(wilc, &rsp, 1)) {
0736                 dev_err(&spi->dev,
0737                     "Failed resp read, bus err\n");
0738                 return -EINVAL;
0739             }
0740             if (WILC_GET_RESP_HDR_START(rsp) == 0xf)
0741                 break;
0742         } while (retry--);
0743 
0744         /*
0745          * Read bytes
0746          */
0747         if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
0748             dev_err(&spi->dev,
0749                 "Failed block read, bus err\n");
0750             return -EINVAL;
0751         }
0752 
0753         /*
0754          * Read CRC
0755          */
0756         if (spi_priv->crc16_enabled) {
0757             if (wilc_spi_rx(wilc, crc, 2)) {
0758                 dev_err(&spi->dev,
0759                     "Failed block CRC read, bus err\n");
0760                 return -EINVAL;
0761             }
0762             crc_recv = (crc[0] << 8) | crc[1];
0763             crc_calc = crc_itu_t(0xffff, &b[ix], nbytes);
0764             if (crc_recv != crc_calc) {
0765                 dev_err(&spi->dev, "%s: bad CRC 0x%04x "
0766                     "(calculated 0x%04x)\n", __func__,
0767                     crc_recv, crc_calc);
0768                 return -EINVAL;
0769             }
0770         }
0771 
0772         ix += nbytes;
0773         sz -= nbytes;
0774     }
0775     return 0;
0776 }
0777 
0778 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd)
0779 {
0780     struct spi_device *spi = to_spi_device(wilc->dev);
0781     struct wilc_spi *spi_priv = wilc->bus_data;
0782     u8 wb[32], rb[32];
0783     int cmd_len, resp_len = 0;
0784     struct wilc_spi_cmd *c;
0785     struct wilc_spi_special_cmd_rsp *r;
0786 
0787     if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET)
0788         return -EINVAL;
0789 
0790     memset(wb, 0x0, sizeof(wb));
0791     memset(rb, 0x0, sizeof(rb));
0792     c = (struct wilc_spi_cmd *)wb;
0793     c->cmd_type = cmd;
0794 
0795     if (cmd == CMD_RESET)
0796         memset(c->u.simple_cmd.addr, 0xFF, 3);
0797 
0798     cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
0799     resp_len = sizeof(*r);
0800 
0801     if (spi_priv->crc7_enabled) {
0802         c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
0803         cmd_len += 1;
0804     }
0805     if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
0806         dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n",
0807             cmd_len, resp_len, ARRAY_SIZE(wb));
0808         return -EINVAL;
0809     }
0810 
0811     if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
0812         dev_err(&spi->dev, "Failed cmd write, bus error...\n");
0813         return -EINVAL;
0814     }
0815 
0816     r = (struct wilc_spi_special_cmd_rsp *)&rb[cmd_len];
0817     if (r->rsp_cmd_type != cmd) {
0818         if (!spi_priv->probing_crc)
0819             dev_err(&spi->dev,
0820                 "Failed cmd response, cmd (%02x), resp (%02x)\n",
0821                 cmd, r->rsp_cmd_type);
0822         return -EINVAL;
0823     }
0824 
0825     if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
0826         dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
0827             r->status);
0828         return -EINVAL;
0829     }
0830     return 0;
0831 }
0832 
0833 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
0834 {
0835     struct spi_device *spi = to_spi_device(wilc->dev);
0836     int result;
0837     u8 cmd = CMD_SINGLE_READ;
0838     u8 clockless = 0;
0839 
0840     if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
0841         /* Clockless register */
0842         cmd = CMD_INTERNAL_READ;
0843         clockless = 1;
0844     }
0845 
0846     result = wilc_spi_single_read(wilc, cmd, addr, data, clockless);
0847     if (result) {
0848         dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
0849         return result;
0850     }
0851 
0852     le32_to_cpus(data);
0853 
0854     return 0;
0855 }
0856 
0857 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
0858 {
0859     struct spi_device *spi = to_spi_device(wilc->dev);
0860     int result;
0861 
0862     if (size <= 4)
0863         return -EINVAL;
0864 
0865     result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size);
0866     if (result) {
0867         dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
0868         return result;
0869     }
0870 
0871     return 0;
0872 }
0873 
0874 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
0875 {
0876     struct spi_device *spi = to_spi_device(wilc->dev);
0877     int result;
0878 
0879     result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0);
0880     if (result) {
0881         dev_err(&spi->dev, "Failed internal write cmd...\n");
0882         return result;
0883     }
0884 
0885     return 0;
0886 }
0887 
0888 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
0889 {
0890     struct spi_device *spi = to_spi_device(wilc->dev);
0891     struct wilc_spi *spi_priv = wilc->bus_data;
0892     int result;
0893 
0894     result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0);
0895     if (result) {
0896         if (!spi_priv->probing_crc)
0897             dev_err(&spi->dev, "Failed internal read cmd...\n");
0898         return result;
0899     }
0900 
0901     le32_to_cpus(data);
0902 
0903     return 0;
0904 }
0905 
0906 /********************************************
0907  *
0908  *      Spi interfaces
0909  *
0910  ********************************************/
0911 
0912 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
0913 {
0914     struct spi_device *spi = to_spi_device(wilc->dev);
0915     int result;
0916     u8 cmd = CMD_SINGLE_WRITE;
0917     u8 clockless = 0;
0918 
0919     if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
0920         /* Clockless register */
0921         cmd = CMD_INTERNAL_WRITE;
0922         clockless = 1;
0923     }
0924 
0925     result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless);
0926     if (result) {
0927         dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
0928         return result;
0929     }
0930 
0931     return 0;
0932 }
0933 
0934 static int spi_data_rsp(struct wilc *wilc, u8 cmd)
0935 {
0936     struct spi_device *spi = to_spi_device(wilc->dev);
0937     int result, i;
0938     u8 rsp[4];
0939 
0940     /*
0941      * The response to data packets is two bytes long.  For
0942      * efficiency's sake, wilc_spi_write() wisely ignores the
0943      * responses for all packets but the final one.  The downside
0944      * of that optimization is that when the final data packet is
0945      * short, we may receive (part of) the response to the
0946      * second-to-last packet before the one for the final packet.
0947      * To handle this, we always read 4 bytes and then search for
0948      * the last byte that contains the "Response Start" code (0xc
0949      * in the top 4 bits).  We then know that this byte is the
0950      * first response byte of the final data packet.
0951      */
0952     result = wilc_spi_rx(wilc, rsp, sizeof(rsp));
0953     if (result) {
0954         dev_err(&spi->dev, "Failed bus error...\n");
0955         return result;
0956     }
0957 
0958     for (i = sizeof(rsp) - 2; i >= 0; --i)
0959         if (FIELD_GET(RSP_START_FIELD, rsp[i]) == RSP_START_TAG)
0960             break;
0961 
0962     if (i < 0) {
0963         dev_err(&spi->dev,
0964             "Data packet response missing (%02x %02x %02x %02x)\n",
0965             rsp[0], rsp[1], rsp[2], rsp[3]);
0966         return -1;
0967     }
0968 
0969     /* rsp[i] is the last response start byte */
0970 
0971     if (FIELD_GET(RSP_TYPE_FIELD, rsp[i]) != RSP_TYPE_LAST_PACKET
0972         || rsp[i + 1] != RSP_STATE_NO_ERROR) {
0973         dev_err(&spi->dev, "Data response error (%02x %02x)\n",
0974             rsp[i], rsp[i + 1]);
0975         return -1;
0976     }
0977     return 0;
0978 }
0979 
0980 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
0981 {
0982     struct spi_device *spi = to_spi_device(wilc->dev);
0983     int result;
0984 
0985     /*
0986      * has to be greated than 4
0987      */
0988     if (size <= 4)
0989         return -EINVAL;
0990 
0991     result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size);
0992     if (result) {
0993         dev_err(&spi->dev,
0994             "Failed cmd, write block (%08x)...\n", addr);
0995         return result;
0996     }
0997 
0998     /*
0999      * Data
1000      */
1001     result = spi_data_write(wilc, buf, size);
1002     if (result) {
1003         dev_err(&spi->dev, "Failed block data write...\n");
1004         return result;
1005     }
1006 
1007     /*
1008      * Data response
1009      */
1010     return spi_data_rsp(wilc, CMD_DMA_EXT_WRITE);
1011 }
1012 
1013 /********************************************
1014  *
1015  *      Bus interfaces
1016  *
1017  ********************************************/
1018 
1019 static int wilc_spi_reset(struct wilc *wilc)
1020 {
1021     struct spi_device *spi = to_spi_device(wilc->dev);
1022     struct wilc_spi *spi_priv = wilc->bus_data;
1023     int result;
1024 
1025     result = wilc_spi_special_cmd(wilc, CMD_RESET);
1026     if (result && !spi_priv->probing_crc)
1027         dev_err(&spi->dev, "Failed cmd reset\n");
1028 
1029     return result;
1030 }
1031 
1032 static bool wilc_spi_is_init(struct wilc *wilc)
1033 {
1034     struct wilc_spi *spi_priv = wilc->bus_data;
1035 
1036     return spi_priv->isinit;
1037 }
1038 
1039 static int wilc_spi_deinit(struct wilc *wilc)
1040 {
1041     struct wilc_spi *spi_priv = wilc->bus_data;
1042 
1043     spi_priv->isinit = false;
1044     wilc_wlan_power(wilc, false);
1045     return 0;
1046 }
1047 
1048 static int wilc_spi_init(struct wilc *wilc, bool resume)
1049 {
1050     struct spi_device *spi = to_spi_device(wilc->dev);
1051     struct wilc_spi *spi_priv = wilc->bus_data;
1052     u32 reg;
1053     u32 chipid;
1054     int ret, i;
1055 
1056     if (spi_priv->isinit) {
1057         /* Confirm we can read chipid register without error: */
1058         ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
1059         if (ret == 0)
1060             return 0;
1061 
1062         dev_err(&spi->dev, "Fail cmd read chip id...\n");
1063     }
1064 
1065     wilc_wlan_power(wilc, true);
1066 
1067     /*
1068      * configure protocol
1069      */
1070 
1071     /*
1072      * Infer the CRC settings that are currently in effect.  This
1073      * is necessary because we can't be sure that the chip has
1074      * been RESET (e.g, after module unload and reload).
1075      */
1076     spi_priv->probing_crc = true;
1077     spi_priv->crc7_enabled = enable_crc7;
1078     spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */
1079     for (i = 0; i < 2; ++i) {
1080         ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg);
1081         if (ret == 0)
1082             break;
1083         spi_priv->crc7_enabled = !enable_crc7;
1084     }
1085     if (ret) {
1086         dev_err(&spi->dev, "Failed with CRC7 on and off.\n");
1087         return ret;
1088     }
1089 
1090     /* set up the desired CRC configuration: */
1091     reg &= ~(PROTOCOL_REG_CRC7_MASK | PROTOCOL_REG_CRC16_MASK);
1092     if (enable_crc7)
1093         reg |= PROTOCOL_REG_CRC7_MASK;
1094     if (enable_crc16)
1095         reg |= PROTOCOL_REG_CRC16_MASK;
1096 
1097     /* set up the data packet size: */
1098     BUILD_BUG_ON(DATA_PKT_LOG_SZ < DATA_PKT_LOG_SZ_MIN
1099              || DATA_PKT_LOG_SZ > DATA_PKT_LOG_SZ_MAX);
1100     reg &= ~PROTOCOL_REG_PKT_SZ_MASK;
1101     reg |= FIELD_PREP(PROTOCOL_REG_PKT_SZ_MASK,
1102               DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN);
1103 
1104     /* establish the new setup: */
1105     ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg);
1106     if (ret) {
1107         dev_err(&spi->dev,
1108             "[wilc spi %d]: Failed internal write reg\n",
1109             __LINE__);
1110         return ret;
1111     }
1112     /* update our state to match new protocol settings: */
1113     spi_priv->crc7_enabled = enable_crc7;
1114     spi_priv->crc16_enabled = enable_crc16;
1115 
1116     /* re-read to make sure new settings are in effect: */
1117     spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg);
1118 
1119     spi_priv->probing_crc = false;
1120 
1121     /*
1122      * make sure can read chip id without protocol error
1123      */
1124     ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
1125     if (ret) {
1126         dev_err(&spi->dev, "Fail cmd read chip id...\n");
1127         return ret;
1128     }
1129 
1130     spi_priv->isinit = true;
1131 
1132     return 0;
1133 }
1134 
1135 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
1136 {
1137     int ret;
1138 
1139     ret = spi_internal_read(wilc,
1140                 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size);
1141     *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size);
1142 
1143     return ret;
1144 }
1145 
1146 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
1147 {
1148     return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE,
1149                  int_status);
1150 }
1151 
1152 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
1153 {
1154     int ret;
1155     int retry = SPI_ENABLE_VMM_RETRY_LIMIT;
1156     u32 check;
1157 
1158     while (retry) {
1159         ret = spi_internal_write(wilc,
1160                      WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
1161                      val);
1162         if (ret)
1163             break;
1164 
1165         ret = spi_internal_read(wilc,
1166                     WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
1167                     &check);
1168         if (ret || ((check & EN_VMM) == (val & EN_VMM)))
1169             break;
1170 
1171         retry--;
1172     }
1173     return ret;
1174 }
1175 
1176 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1177 {
1178     struct spi_device *spi = to_spi_device(wilc->dev);
1179     u32 reg;
1180     int ret, i;
1181 
1182     if (nint > MAX_NUM_INT) {
1183         dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1184         return -EINVAL;
1185     }
1186 
1187     /*
1188      * interrupt pin mux select
1189      */
1190     ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, &reg);
1191     if (ret) {
1192         dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1193             WILC_PIN_MUX_0);
1194         return ret;
1195     }
1196     reg |= BIT(8);
1197     ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1198     if (ret) {
1199         dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1200             WILC_PIN_MUX_0);
1201         return ret;
1202     }
1203 
1204     /*
1205      * interrupt enable
1206      */
1207     ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, &reg);
1208     if (ret) {
1209         dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1210             WILC_INTR_ENABLE);
1211         return ret;
1212     }
1213 
1214     for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1215         reg |= (BIT((27 + i)));
1216 
1217     ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1218     if (ret) {
1219         dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1220             WILC_INTR_ENABLE);
1221         return ret;
1222     }
1223     if (nint) {
1224         ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1225         if (ret) {
1226             dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1227                 WILC_INTR2_ENABLE);
1228             return ret;
1229         }
1230 
1231         for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1232             reg |= BIT(i);
1233 
1234         ret = wilc_spi_write_reg(wilc, WILC_INTR2_ENABLE, reg);
1235         if (ret) {
1236             dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1237                 WILC_INTR2_ENABLE);
1238             return ret;
1239         }
1240     }
1241 
1242     return 0;
1243 }
1244 
1245 /* Global spi HIF function table */
1246 static const struct wilc_hif_func wilc_hif_spi = {
1247     .hif_init = wilc_spi_init,
1248     .hif_deinit = wilc_spi_deinit,
1249     .hif_read_reg = wilc_spi_read_reg,
1250     .hif_write_reg = wilc_spi_write_reg,
1251     .hif_block_rx = wilc_spi_read,
1252     .hif_block_tx = wilc_spi_write,
1253     .hif_read_int = wilc_spi_read_int,
1254     .hif_clear_int_ext = wilc_spi_clear_int_ext,
1255     .hif_read_size = wilc_spi_read_size,
1256     .hif_block_tx_ext = wilc_spi_write,
1257     .hif_block_rx_ext = wilc_spi_read,
1258     .hif_sync_ext = wilc_spi_sync_ext,
1259     .hif_reset = wilc_spi_reset,
1260     .hif_is_init = wilc_spi_is_init,
1261 };
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