Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
0004  * All rights reserved.
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/mmc/sdio_func.h>
0009 #include <linux/mmc/sdio_ids.h>
0010 #include <linux/mmc/host.h>
0011 #include <linux/mmc/sdio.h>
0012 #include <linux/of_irq.h>
0013 
0014 #include "netdev.h"
0015 #include "cfg80211.h"
0016 
0017 #define SDIO_MODALIAS "wilc1000_sdio"
0018 
0019 static const struct sdio_device_id wilc_sdio_ids[] = {
0020     { SDIO_DEVICE(SDIO_VENDOR_ID_MICROCHIP_WILC, SDIO_DEVICE_ID_MICROCHIP_WILC1000) },
0021     { },
0022 };
0023 
0024 #define WILC_SDIO_BLOCK_SIZE 512
0025 
0026 struct wilc_sdio {
0027     bool irq_gpio;
0028     u32 block_size;
0029     bool isinit;
0030     int has_thrpt_enh3;
0031     u8 *cmd53_buf;
0032 };
0033 
0034 struct sdio_cmd52 {
0035     u32 read_write:     1;
0036     u32 function:       3;
0037     u32 raw:        1;
0038     u32 address:        17;
0039     u32 data:       8;
0040 };
0041 
0042 struct sdio_cmd53 {
0043     u32 read_write:     1;
0044     u32 function:       3;
0045     u32 block_mode:     1;
0046     u32 increment:      1;
0047     u32 address:        17;
0048     u32 count:      9;
0049     u8 *buffer;
0050     u32 block_size;
0051     bool use_global_buf;
0052 };
0053 
0054 static const struct wilc_hif_func wilc_hif_sdio;
0055 
0056 static void wilc_sdio_interrupt(struct sdio_func *func)
0057 {
0058     sdio_release_host(func);
0059     wilc_handle_isr(sdio_get_drvdata(func));
0060     sdio_claim_host(func);
0061 }
0062 
0063 static int wilc_sdio_cmd52(struct wilc *wilc, struct sdio_cmd52 *cmd)
0064 {
0065     struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev);
0066     int ret;
0067     u8 data;
0068 
0069     sdio_claim_host(func);
0070 
0071     func->num = cmd->function;
0072     if (cmd->read_write) {  /* write */
0073         if (cmd->raw) {
0074             sdio_writeb(func, cmd->data, cmd->address, &ret);
0075             data = sdio_readb(func, cmd->address, &ret);
0076             cmd->data = data;
0077         } else {
0078             sdio_writeb(func, cmd->data, cmd->address, &ret);
0079         }
0080     } else {        /* read */
0081         data = sdio_readb(func, cmd->address, &ret);
0082         cmd->data = data;
0083     }
0084 
0085     sdio_release_host(func);
0086 
0087     if (ret)
0088         dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret);
0089     return ret;
0090 }
0091 
0092 static int wilc_sdio_cmd53(struct wilc *wilc, struct sdio_cmd53 *cmd)
0093 {
0094     struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev);
0095     int size, ret;
0096     struct wilc_sdio *sdio_priv = wilc->bus_data;
0097     u8 *buf = cmd->buffer;
0098 
0099     sdio_claim_host(func);
0100 
0101     func->num = cmd->function;
0102     func->cur_blksize = cmd->block_size;
0103     if (cmd->block_mode)
0104         size = cmd->count * cmd->block_size;
0105     else
0106         size = cmd->count;
0107 
0108     if (cmd->use_global_buf) {
0109         if (size > sizeof(u32))
0110             return -EINVAL;
0111 
0112         buf = sdio_priv->cmd53_buf;
0113     }
0114 
0115     if (cmd->read_write) {  /* write */
0116         if (cmd->use_global_buf)
0117             memcpy(buf, cmd->buffer, size);
0118 
0119         ret = sdio_memcpy_toio(func, cmd->address, buf, size);
0120     } else {        /* read */
0121         ret = sdio_memcpy_fromio(func, buf, cmd->address, size);
0122 
0123         if (cmd->use_global_buf)
0124             memcpy(cmd->buffer, buf, size);
0125     }
0126 
0127     sdio_release_host(func);
0128 
0129     if (ret)
0130         dev_err(&func->dev, "%s..failed, err(%d)\n", __func__,  ret);
0131 
0132     return ret;
0133 }
0134 
0135 static int wilc_sdio_probe(struct sdio_func *func,
0136                const struct sdio_device_id *id)
0137 {
0138     struct wilc *wilc;
0139     int ret;
0140     struct wilc_sdio *sdio_priv;
0141 
0142     sdio_priv = kzalloc(sizeof(*sdio_priv), GFP_KERNEL);
0143     if (!sdio_priv)
0144         return -ENOMEM;
0145 
0146     sdio_priv->cmd53_buf = kzalloc(sizeof(u32), GFP_KERNEL);
0147     if (!sdio_priv->cmd53_buf) {
0148         ret = -ENOMEM;
0149         goto free;
0150     }
0151 
0152     ret = wilc_cfg80211_init(&wilc, &func->dev, WILC_HIF_SDIO,
0153                  &wilc_hif_sdio);
0154     if (ret)
0155         goto free;
0156 
0157     if (IS_ENABLED(CONFIG_WILC1000_HW_OOB_INTR)) {
0158         struct device_node *np = func->card->dev.of_node;
0159         int irq_num = of_irq_get(np, 0);
0160 
0161         if (irq_num > 0) {
0162             wilc->dev_irq_num = irq_num;
0163             sdio_priv->irq_gpio = true;
0164         }
0165     }
0166 
0167     sdio_set_drvdata(func, wilc);
0168     wilc->bus_data = sdio_priv;
0169     wilc->dev = &func->dev;
0170 
0171     wilc->rtc_clk = devm_clk_get_optional(&func->card->dev, "rtc");
0172     if (IS_ERR(wilc->rtc_clk)) {
0173         ret = PTR_ERR(wilc->rtc_clk);
0174         goto dispose_irq;
0175     }
0176     clk_prepare_enable(wilc->rtc_clk);
0177 
0178     dev_info(&func->dev, "Driver Initializing success\n");
0179     return 0;
0180 
0181 dispose_irq:
0182     irq_dispose_mapping(wilc->dev_irq_num);
0183     wilc_netdev_cleanup(wilc);
0184 free:
0185     kfree(sdio_priv->cmd53_buf);
0186     kfree(sdio_priv);
0187     return ret;
0188 }
0189 
0190 static void wilc_sdio_remove(struct sdio_func *func)
0191 {
0192     struct wilc *wilc = sdio_get_drvdata(func);
0193     struct wilc_sdio *sdio_priv = wilc->bus_data;
0194 
0195     clk_disable_unprepare(wilc->rtc_clk);
0196     wilc_netdev_cleanup(wilc);
0197     kfree(sdio_priv->cmd53_buf);
0198     kfree(sdio_priv);
0199 }
0200 
0201 static int wilc_sdio_reset(struct wilc *wilc)
0202 {
0203     struct sdio_cmd52 cmd;
0204     int ret;
0205     struct sdio_func *func = dev_to_sdio_func(wilc->dev);
0206 
0207     cmd.read_write = 1;
0208     cmd.function = 0;
0209     cmd.raw = 0;
0210     cmd.address = SDIO_CCCR_ABORT;
0211     cmd.data = WILC_SDIO_CCCR_ABORT_RESET;
0212     ret = wilc_sdio_cmd52(wilc, &cmd);
0213     if (ret) {
0214         dev_err(&func->dev, "Fail cmd 52, reset cmd ...\n");
0215         return ret;
0216     }
0217     return 0;
0218 }
0219 
0220 static bool wilc_sdio_is_init(struct wilc *wilc)
0221 {
0222     struct wilc_sdio *sdio_priv = wilc->bus_data;
0223 
0224     return sdio_priv->isinit;
0225 }
0226 
0227 static int wilc_sdio_suspend(struct device *dev)
0228 {
0229     struct sdio_func *func = dev_to_sdio_func(dev);
0230     struct wilc *wilc = sdio_get_drvdata(func);
0231     int ret;
0232 
0233     dev_info(dev, "sdio suspend\n");
0234     chip_wakeup(wilc);
0235 
0236     if (!IS_ERR(wilc->rtc_clk))
0237         clk_disable_unprepare(wilc->rtc_clk);
0238 
0239     if (wilc->suspend_event) {
0240         host_sleep_notify(wilc);
0241         chip_allow_sleep(wilc);
0242     }
0243 
0244     ret = wilc_sdio_reset(wilc);
0245     if (ret) {
0246         dev_err(&func->dev, "Fail reset sdio\n");
0247         return ret;
0248     }
0249     sdio_claim_host(func);
0250 
0251     return 0;
0252 }
0253 
0254 static int wilc_sdio_enable_interrupt(struct wilc *dev)
0255 {
0256     struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev);
0257     int ret = 0;
0258 
0259     sdio_claim_host(func);
0260     ret = sdio_claim_irq(func, wilc_sdio_interrupt);
0261     sdio_release_host(func);
0262 
0263     if (ret < 0) {
0264         dev_err(&func->dev, "can't claim sdio_irq, err(%d)\n", ret);
0265         ret = -EIO;
0266     }
0267     return ret;
0268 }
0269 
0270 static void wilc_sdio_disable_interrupt(struct wilc *dev)
0271 {
0272     struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev);
0273     int ret;
0274 
0275     sdio_claim_host(func);
0276     ret = sdio_release_irq(func);
0277     if (ret < 0)
0278         dev_err(&func->dev, "can't release sdio_irq, err(%d)\n", ret);
0279     sdio_release_host(func);
0280 }
0281 
0282 /********************************************
0283  *
0284  *      Function 0
0285  *
0286  ********************************************/
0287 
0288 static int wilc_sdio_set_func0_csa_address(struct wilc *wilc, u32 adr)
0289 {
0290     struct sdio_func *func = dev_to_sdio_func(wilc->dev);
0291     struct sdio_cmd52 cmd;
0292     int ret;
0293 
0294     /**
0295      *      Review: BIG ENDIAN
0296      **/
0297     cmd.read_write = 1;
0298     cmd.function = 0;
0299     cmd.raw = 0;
0300     cmd.address = WILC_SDIO_FBR_CSA_REG;
0301     cmd.data = (u8)adr;
0302     ret = wilc_sdio_cmd52(wilc, &cmd);
0303     if (ret) {
0304         dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
0305             cmd.address);
0306         return ret;
0307     }
0308 
0309     cmd.address = WILC_SDIO_FBR_CSA_REG + 1;
0310     cmd.data = (u8)(adr >> 8);
0311     ret = wilc_sdio_cmd52(wilc, &cmd);
0312     if (ret) {
0313         dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
0314             cmd.address);
0315         return ret;
0316     }
0317 
0318     cmd.address = WILC_SDIO_FBR_CSA_REG + 2;
0319     cmd.data = (u8)(adr >> 16);
0320     ret = wilc_sdio_cmd52(wilc, &cmd);
0321     if (ret) {
0322         dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
0323             cmd.address);
0324         return ret;
0325     }
0326 
0327     return 0;
0328 }
0329 
0330 static int wilc_sdio_set_block_size(struct wilc *wilc, u8 func_num,
0331                     u32 block_size)
0332 {
0333     struct sdio_func *func = dev_to_sdio_func(wilc->dev);
0334     struct sdio_cmd52 cmd;
0335     int ret;
0336 
0337     cmd.read_write = 1;
0338     cmd.function = 0;
0339     cmd.raw = 0;
0340     cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE;
0341     cmd.data = (u8)block_size;
0342     ret = wilc_sdio_cmd52(wilc, &cmd);
0343     if (ret) {
0344         dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
0345             cmd.address);
0346         return ret;
0347     }
0348 
0349     cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE +  1;
0350     cmd.data = (u8)(block_size >> 8);
0351     ret = wilc_sdio_cmd52(wilc, &cmd);
0352     if (ret) {
0353         dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
0354             cmd.address);
0355         return ret;
0356     }
0357 
0358     return 0;
0359 }
0360 
0361 /********************************************
0362  *
0363  *      Sdio interfaces
0364  *
0365  ********************************************/
0366 static int wilc_sdio_write_reg(struct wilc *wilc, u32 addr, u32 data)
0367 {
0368     struct sdio_func *func = dev_to_sdio_func(wilc->dev);
0369     struct wilc_sdio *sdio_priv = wilc->bus_data;
0370     int ret;
0371 
0372     cpu_to_le32s(&data);
0373 
0374     if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */
0375         struct sdio_cmd52 cmd;
0376 
0377         cmd.read_write = 1;
0378         cmd.function = 0;
0379         cmd.raw = 0;
0380         cmd.address = addr;
0381         cmd.data = data;
0382         ret = wilc_sdio_cmd52(wilc, &cmd);
0383         if (ret)
0384             dev_err(&func->dev,
0385                 "Failed cmd 52, read reg (%08x) ...\n", addr);
0386     } else {
0387         struct sdio_cmd53 cmd;
0388 
0389         /**
0390          *      set the AHB address
0391          **/
0392         ret = wilc_sdio_set_func0_csa_address(wilc, addr);
0393         if (ret)
0394             return ret;
0395 
0396         cmd.read_write = 1;
0397         cmd.function = 0;
0398         cmd.address = WILC_SDIO_FBR_DATA_REG;
0399         cmd.block_mode = 0;
0400         cmd.increment = 1;
0401         cmd.count = sizeof(u32);
0402         cmd.buffer = (u8 *)&data;
0403         cmd.use_global_buf = true;
0404         cmd.block_size = sdio_priv->block_size;
0405         ret = wilc_sdio_cmd53(wilc, &cmd);
0406         if (ret)
0407             dev_err(&func->dev,
0408                 "Failed cmd53, write reg (%08x)...\n", addr);
0409     }
0410 
0411     return ret;
0412 }
0413 
0414 static int wilc_sdio_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
0415 {
0416     struct sdio_func *func = dev_to_sdio_func(wilc->dev);
0417     struct wilc_sdio *sdio_priv = wilc->bus_data;
0418     u32 block_size = sdio_priv->block_size;
0419     struct sdio_cmd53 cmd;
0420     int nblk, nleft, ret;
0421 
0422     cmd.read_write = 1;
0423     if (addr > 0) {
0424         /**
0425          *      func 0 access
0426          **/
0427         cmd.function = 0;
0428         cmd.address = WILC_SDIO_FBR_DATA_REG;
0429     } else {
0430         /**
0431          *      func 1 access
0432          **/
0433         cmd.function = 1;
0434         cmd.address = WILC_SDIO_F1_DATA_REG;
0435     }
0436 
0437     size = ALIGN(size, 4);
0438     nblk = size / block_size;
0439     nleft = size % block_size;
0440 
0441     cmd.use_global_buf = false;
0442     if (nblk > 0) {
0443         cmd.block_mode = 1;
0444         cmd.increment = 1;
0445         cmd.count = nblk;
0446         cmd.buffer = buf;
0447         cmd.block_size = block_size;
0448         if (addr > 0) {
0449             ret = wilc_sdio_set_func0_csa_address(wilc, addr);
0450             if (ret)
0451                 return ret;
0452         }
0453         ret = wilc_sdio_cmd53(wilc, &cmd);
0454         if (ret) {
0455             dev_err(&func->dev,
0456                 "Failed cmd53 [%x], block send...\n", addr);
0457             return ret;
0458         }
0459         if (addr > 0)
0460             addr += nblk * block_size;
0461         buf += nblk * block_size;
0462     }
0463 
0464     if (nleft > 0) {
0465         cmd.block_mode = 0;
0466         cmd.increment = 1;
0467         cmd.count = nleft;
0468         cmd.buffer = buf;
0469 
0470         cmd.block_size = block_size;
0471 
0472         if (addr > 0) {
0473             ret = wilc_sdio_set_func0_csa_address(wilc, addr);
0474             if (ret)
0475                 return ret;
0476         }
0477         ret = wilc_sdio_cmd53(wilc, &cmd);
0478         if (ret) {
0479             dev_err(&func->dev,
0480                 "Failed cmd53 [%x], bytes send...\n", addr);
0481             return ret;
0482         }
0483     }
0484 
0485     return 0;
0486 }
0487 
0488 static int wilc_sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data)
0489 {
0490     struct sdio_func *func = dev_to_sdio_func(wilc->dev);
0491     struct wilc_sdio *sdio_priv = wilc->bus_data;
0492     int ret;
0493 
0494     if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */
0495         struct sdio_cmd52 cmd;
0496 
0497         cmd.read_write = 0;
0498         cmd.function = 0;
0499         cmd.raw = 0;
0500         cmd.address = addr;
0501         ret = wilc_sdio_cmd52(wilc, &cmd);
0502         if (ret) {
0503             dev_err(&func->dev,
0504                 "Failed cmd 52, read reg (%08x) ...\n", addr);
0505             return ret;
0506         }
0507         *data = cmd.data;
0508     } else {
0509         struct sdio_cmd53 cmd;
0510 
0511         ret = wilc_sdio_set_func0_csa_address(wilc, addr);
0512         if (ret)
0513             return ret;
0514 
0515         cmd.read_write = 0;
0516         cmd.function = 0;
0517         cmd.address = WILC_SDIO_FBR_DATA_REG;
0518         cmd.block_mode = 0;
0519         cmd.increment = 1;
0520         cmd.count = sizeof(u32);
0521         cmd.buffer = (u8 *)data;
0522         cmd.use_global_buf = true;
0523 
0524         cmd.block_size = sdio_priv->block_size;
0525         ret = wilc_sdio_cmd53(wilc, &cmd);
0526         if (ret) {
0527             dev_err(&func->dev,
0528                 "Failed cmd53, read reg (%08x)...\n", addr);
0529             return ret;
0530         }
0531     }
0532 
0533     le32_to_cpus(data);
0534     return 0;
0535 }
0536 
0537 static int wilc_sdio_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
0538 {
0539     struct sdio_func *func = dev_to_sdio_func(wilc->dev);
0540     struct wilc_sdio *sdio_priv = wilc->bus_data;
0541     u32 block_size = sdio_priv->block_size;
0542     struct sdio_cmd53 cmd;
0543     int nblk, nleft, ret;
0544 
0545     cmd.read_write = 0;
0546     if (addr > 0) {
0547         /**
0548          *      func 0 access
0549          **/
0550         cmd.function = 0;
0551         cmd.address = WILC_SDIO_FBR_DATA_REG;
0552     } else {
0553         /**
0554          *      func 1 access
0555          **/
0556         cmd.function = 1;
0557         cmd.address = WILC_SDIO_F1_DATA_REG;
0558     }
0559 
0560     size = ALIGN(size, 4);
0561     nblk = size / block_size;
0562     nleft = size % block_size;
0563 
0564     cmd.use_global_buf = false;
0565     if (nblk > 0) {
0566         cmd.block_mode = 1;
0567         cmd.increment = 1;
0568         cmd.count = nblk;
0569         cmd.buffer = buf;
0570         cmd.block_size = block_size;
0571         if (addr > 0) {
0572             ret = wilc_sdio_set_func0_csa_address(wilc, addr);
0573             if (ret)
0574                 return ret;
0575         }
0576         ret = wilc_sdio_cmd53(wilc, &cmd);
0577         if (ret) {
0578             dev_err(&func->dev,
0579                 "Failed cmd53 [%x], block read...\n", addr);
0580             return ret;
0581         }
0582         if (addr > 0)
0583             addr += nblk * block_size;
0584         buf += nblk * block_size;
0585     }       /* if (nblk > 0) */
0586 
0587     if (nleft > 0) {
0588         cmd.block_mode = 0;
0589         cmd.increment = 1;
0590         cmd.count = nleft;
0591         cmd.buffer = buf;
0592 
0593         cmd.block_size = block_size;
0594 
0595         if (addr > 0) {
0596             ret = wilc_sdio_set_func0_csa_address(wilc, addr);
0597             if (ret)
0598                 return ret;
0599         }
0600         ret = wilc_sdio_cmd53(wilc, &cmd);
0601         if (ret) {
0602             dev_err(&func->dev,
0603                 "Failed cmd53 [%x], bytes read...\n", addr);
0604             return ret;
0605         }
0606     }
0607 
0608     return 0;
0609 }
0610 
0611 /********************************************
0612  *
0613  *      Bus interfaces
0614  *
0615  ********************************************/
0616 
0617 static int wilc_sdio_deinit(struct wilc *wilc)
0618 {
0619     struct wilc_sdio *sdio_priv = wilc->bus_data;
0620 
0621     sdio_priv->isinit = false;
0622     return 0;
0623 }
0624 
0625 static int wilc_sdio_init(struct wilc *wilc, bool resume)
0626 {
0627     struct sdio_func *func = dev_to_sdio_func(wilc->dev);
0628     struct wilc_sdio *sdio_priv = wilc->bus_data;
0629     struct sdio_cmd52 cmd;
0630     int loop, ret;
0631     u32 chipid;
0632 
0633     /**
0634      *      function 0 csa enable
0635      **/
0636     cmd.read_write = 1;
0637     cmd.function = 0;
0638     cmd.raw = 1;
0639     cmd.address = SDIO_FBR_BASE(1);
0640     cmd.data = SDIO_FBR_ENABLE_CSA;
0641     ret = wilc_sdio_cmd52(wilc, &cmd);
0642     if (ret) {
0643         dev_err(&func->dev, "Fail cmd 52, enable csa...\n");
0644         return ret;
0645     }
0646 
0647     /**
0648      *      function 0 block size
0649      **/
0650     ret = wilc_sdio_set_block_size(wilc, 0, WILC_SDIO_BLOCK_SIZE);
0651     if (ret) {
0652         dev_err(&func->dev, "Fail cmd 52, set func 0 block size...\n");
0653         return ret;
0654     }
0655     sdio_priv->block_size = WILC_SDIO_BLOCK_SIZE;
0656 
0657     /**
0658      *      enable func1 IO
0659      **/
0660     cmd.read_write = 1;
0661     cmd.function = 0;
0662     cmd.raw = 1;
0663     cmd.address = SDIO_CCCR_IOEx;
0664     cmd.data = WILC_SDIO_CCCR_IO_EN_FUNC1;
0665     ret = wilc_sdio_cmd52(wilc, &cmd);
0666     if (ret) {
0667         dev_err(&func->dev,
0668             "Fail cmd 52, set IOE register...\n");
0669         return ret;
0670     }
0671 
0672     /**
0673      *      make sure func 1 is up
0674      **/
0675     cmd.read_write = 0;
0676     cmd.function = 0;
0677     cmd.raw = 0;
0678     cmd.address = SDIO_CCCR_IORx;
0679     loop = 3;
0680     do {
0681         cmd.data = 0;
0682         ret = wilc_sdio_cmd52(wilc, &cmd);
0683         if (ret) {
0684             dev_err(&func->dev,
0685                 "Fail cmd 52, get IOR register...\n");
0686             return ret;
0687         }
0688         if (cmd.data == WILC_SDIO_CCCR_IO_EN_FUNC1)
0689             break;
0690     } while (loop--);
0691 
0692     if (loop <= 0) {
0693         dev_err(&func->dev, "Fail func 1 is not ready...\n");
0694         return -EINVAL;
0695     }
0696 
0697     /**
0698      *      func 1 is ready, set func 1 block size
0699      **/
0700     ret = wilc_sdio_set_block_size(wilc, 1, WILC_SDIO_BLOCK_SIZE);
0701     if (ret) {
0702         dev_err(&func->dev, "Fail set func 1 block size...\n");
0703         return ret;
0704     }
0705 
0706     /**
0707      *      func 1 interrupt enable
0708      **/
0709     cmd.read_write = 1;
0710     cmd.function = 0;
0711     cmd.raw = 1;
0712     cmd.address = SDIO_CCCR_IENx;
0713     cmd.data = WILC_SDIO_CCCR_IEN_MASTER | WILC_SDIO_CCCR_IEN_FUNC1;
0714     ret = wilc_sdio_cmd52(wilc, &cmd);
0715     if (ret) {
0716         dev_err(&func->dev, "Fail cmd 52, set IEN register...\n");
0717         return ret;
0718     }
0719 
0720     /**
0721      *      make sure can read back chip id correctly
0722      **/
0723     if (!resume) {
0724         int rev;
0725 
0726         ret = wilc_sdio_read_reg(wilc, WILC_CHIPID, &chipid);
0727         if (ret) {
0728             dev_err(&func->dev, "Fail cmd read chip id...\n");
0729             return ret;
0730         }
0731         dev_err(&func->dev, "chipid (%08x)\n", chipid);
0732         rev = FIELD_GET(WILC_CHIP_REV_FIELD, chipid);
0733         if (rev > FIELD_GET(WILC_CHIP_REV_FIELD, WILC_1000_BASE_ID_2A))
0734             sdio_priv->has_thrpt_enh3 = 1;
0735         else
0736             sdio_priv->has_thrpt_enh3 = 0;
0737         dev_info(&func->dev, "has_thrpt_enh3 = %d...\n",
0738              sdio_priv->has_thrpt_enh3);
0739     }
0740 
0741     sdio_priv->isinit = true;
0742     return 0;
0743 }
0744 
0745 static int wilc_sdio_read_size(struct wilc *wilc, u32 *size)
0746 {
0747     u32 tmp;
0748     struct sdio_cmd52 cmd;
0749 
0750     /**
0751      *      Read DMA count in words
0752      **/
0753     cmd.read_write = 0;
0754     cmd.function = 0;
0755     cmd.raw = 0;
0756     cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG;
0757     cmd.data = 0;
0758     wilc_sdio_cmd52(wilc, &cmd);
0759     tmp = cmd.data;
0760 
0761     cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG + 1;
0762     cmd.data = 0;
0763     wilc_sdio_cmd52(wilc, &cmd);
0764     tmp |= (cmd.data << 8);
0765 
0766     *size = tmp;
0767     return 0;
0768 }
0769 
0770 static int wilc_sdio_read_int(struct wilc *wilc, u32 *int_status)
0771 {
0772     struct sdio_func *func = dev_to_sdio_func(wilc->dev);
0773     struct wilc_sdio *sdio_priv = wilc->bus_data;
0774     u32 tmp;
0775     u8 irq_flags;
0776     struct sdio_cmd52 cmd;
0777 
0778     wilc_sdio_read_size(wilc, &tmp);
0779 
0780     /**
0781      *      Read IRQ flags
0782      **/
0783     if (!sdio_priv->irq_gpio) {
0784         cmd.function = 1;
0785         cmd.address = WILC_SDIO_EXT_IRQ_FLAG_REG;
0786     } else {
0787         cmd.function = 0;
0788         cmd.address = WILC_SDIO_IRQ_FLAG_REG;
0789     }
0790     cmd.raw = 0;
0791     cmd.read_write = 0;
0792     cmd.data = 0;
0793     wilc_sdio_cmd52(wilc, &cmd);
0794     irq_flags = cmd.data;
0795     tmp |= FIELD_PREP(IRG_FLAGS_MASK, cmd.data);
0796 
0797     if (FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags))
0798         dev_err(&func->dev, "Unexpected interrupt (1) int=%lx\n",
0799             FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags));
0800 
0801     *int_status = tmp;
0802 
0803     return 0;
0804 }
0805 
0806 static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val)
0807 {
0808     struct sdio_func *func = dev_to_sdio_func(wilc->dev);
0809     struct wilc_sdio *sdio_priv = wilc->bus_data;
0810     int ret;
0811     int vmm_ctl;
0812 
0813     if (sdio_priv->has_thrpt_enh3) {
0814         u32 reg = 0;
0815 
0816         if (sdio_priv->irq_gpio)
0817             reg = val & (BIT(MAX_NUM_INT) - 1);
0818 
0819         /* select VMM table 0 */
0820         if (val & SEL_VMM_TBL0)
0821             reg |= BIT(5);
0822         /* select VMM table 1 */
0823         if (val & SEL_VMM_TBL1)
0824             reg |= BIT(6);
0825         /* enable VMM */
0826         if (val & EN_VMM)
0827             reg |= BIT(7);
0828         if (reg) {
0829             struct sdio_cmd52 cmd;
0830 
0831             cmd.read_write = 1;
0832             cmd.function = 0;
0833             cmd.raw = 0;
0834             cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG;
0835             cmd.data = reg;
0836 
0837             ret = wilc_sdio_cmd52(wilc, &cmd);
0838             if (ret) {
0839                 dev_err(&func->dev,
0840                     "Failed cmd52, set (%02x) data (%d) ...\n",
0841                     cmd.address, __LINE__);
0842                 return ret;
0843             }
0844         }
0845         return 0;
0846     }
0847     if (sdio_priv->irq_gpio) {
0848         /* has_thrpt_enh2 uses register 0xf8 to clear interrupts. */
0849         /*
0850          * Cannot clear multiple interrupts.
0851          * Must clear each interrupt individually.
0852          */
0853         u32 flags;
0854         int i;
0855 
0856         flags = val & (BIT(MAX_NUM_INT) - 1);
0857         for (i = 0; i < NUM_INT_EXT && flags; i++) {
0858             if (flags & BIT(i)) {
0859                 struct sdio_cmd52 cmd;
0860 
0861                 cmd.read_write = 1;
0862                 cmd.function = 0;
0863                 cmd.raw = 0;
0864                 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG;
0865                 cmd.data = BIT(i);
0866 
0867                 ret = wilc_sdio_cmd52(wilc, &cmd);
0868                 if (ret) {
0869                     dev_err(&func->dev,
0870                         "Failed cmd52, set (%02x) data (%d) ...\n",
0871                         cmd.address, __LINE__);
0872                     return ret;
0873                 }
0874                 flags &= ~BIT(i);
0875             }
0876         }
0877 
0878         for (i = NUM_INT_EXT; i < MAX_NUM_INT && flags; i++) {
0879             if (flags & BIT(i)) {
0880                 dev_err(&func->dev,
0881                     "Unexpected interrupt cleared %d...\n",
0882                     i);
0883                 flags &= ~BIT(i);
0884             }
0885         }
0886     }
0887 
0888     vmm_ctl = 0;
0889     /* select VMM table 0 */
0890     if (val & SEL_VMM_TBL0)
0891         vmm_ctl |= BIT(0);
0892     /* select VMM table 1 */
0893     if (val & SEL_VMM_TBL1)
0894         vmm_ctl |= BIT(1);
0895     /* enable VMM */
0896     if (val & EN_VMM)
0897         vmm_ctl |= BIT(2);
0898 
0899     if (vmm_ctl) {
0900         struct sdio_cmd52 cmd;
0901 
0902         cmd.read_write = 1;
0903         cmd.function = 0;
0904         cmd.raw = 0;
0905         cmd.address = WILC_SDIO_VMM_TBL_CTRL_REG;
0906         cmd.data = vmm_ctl;
0907         ret = wilc_sdio_cmd52(wilc, &cmd);
0908         if (ret) {
0909             dev_err(&func->dev,
0910                 "Failed cmd52, set (%02x) data (%d) ...\n",
0911                 cmd.address, __LINE__);
0912             return ret;
0913         }
0914     }
0915     return 0;
0916 }
0917 
0918 static int wilc_sdio_sync_ext(struct wilc *wilc, int nint)
0919 {
0920     struct sdio_func *func = dev_to_sdio_func(wilc->dev);
0921     struct wilc_sdio *sdio_priv = wilc->bus_data;
0922     u32 reg;
0923 
0924     if (nint > MAX_NUM_INT) {
0925         dev_err(&func->dev, "Too many interrupts (%d)...\n", nint);
0926         return -EINVAL;
0927     }
0928 
0929     /**
0930      *      Disable power sequencer
0931      **/
0932     if (wilc_sdio_read_reg(wilc, WILC_MISC, &reg)) {
0933         dev_err(&func->dev, "Failed read misc reg...\n");
0934         return -EINVAL;
0935     }
0936 
0937     reg &= ~BIT(8);
0938     if (wilc_sdio_write_reg(wilc, WILC_MISC, reg)) {
0939         dev_err(&func->dev, "Failed write misc reg...\n");
0940         return -EINVAL;
0941     }
0942 
0943     if (sdio_priv->irq_gpio) {
0944         u32 reg;
0945         int ret, i;
0946 
0947         /**
0948          *      interrupt pin mux select
0949          **/
0950         ret = wilc_sdio_read_reg(wilc, WILC_PIN_MUX_0, &reg);
0951         if (ret) {
0952             dev_err(&func->dev, "Failed read reg (%08x)...\n",
0953                 WILC_PIN_MUX_0);
0954             return ret;
0955         }
0956         reg |= BIT(8);
0957         ret = wilc_sdio_write_reg(wilc, WILC_PIN_MUX_0, reg);
0958         if (ret) {
0959             dev_err(&func->dev, "Failed write reg (%08x)...\n",
0960                 WILC_PIN_MUX_0);
0961             return ret;
0962         }
0963 
0964         /**
0965          *      interrupt enable
0966          **/
0967         ret = wilc_sdio_read_reg(wilc, WILC_INTR_ENABLE, &reg);
0968         if (ret) {
0969             dev_err(&func->dev, "Failed read reg (%08x)...\n",
0970                 WILC_INTR_ENABLE);
0971             return ret;
0972         }
0973 
0974         for (i = 0; (i < 5) && (nint > 0); i++, nint--)
0975             reg |= BIT((27 + i));
0976         ret = wilc_sdio_write_reg(wilc, WILC_INTR_ENABLE, reg);
0977         if (ret) {
0978             dev_err(&func->dev, "Failed write reg (%08x)...\n",
0979                 WILC_INTR_ENABLE);
0980             return ret;
0981         }
0982         if (nint) {
0983             ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
0984             if (ret) {
0985                 dev_err(&func->dev,
0986                     "Failed read reg (%08x)...\n",
0987                     WILC_INTR2_ENABLE);
0988                 return ret;
0989             }
0990 
0991             for (i = 0; (i < 3) && (nint > 0); i++, nint--)
0992                 reg |= BIT(i);
0993 
0994             ret = wilc_sdio_write_reg(wilc, WILC_INTR2_ENABLE, reg);
0995             if (ret) {
0996                 dev_err(&func->dev,
0997                     "Failed write reg (%08x)...\n",
0998                     WILC_INTR2_ENABLE);
0999                 return ret;
1000             }
1001         }
1002     }
1003     return 0;
1004 }
1005 
1006 /* Global sdio HIF function table */
1007 static const struct wilc_hif_func wilc_hif_sdio = {
1008     .hif_init = wilc_sdio_init,
1009     .hif_deinit = wilc_sdio_deinit,
1010     .hif_read_reg = wilc_sdio_read_reg,
1011     .hif_write_reg = wilc_sdio_write_reg,
1012     .hif_block_rx = wilc_sdio_read,
1013     .hif_block_tx = wilc_sdio_write,
1014     .hif_read_int = wilc_sdio_read_int,
1015     .hif_clear_int_ext = wilc_sdio_clear_int_ext,
1016     .hif_read_size = wilc_sdio_read_size,
1017     .hif_block_tx_ext = wilc_sdio_write,
1018     .hif_block_rx_ext = wilc_sdio_read,
1019     .hif_sync_ext = wilc_sdio_sync_ext,
1020     .enable_interrupt = wilc_sdio_enable_interrupt,
1021     .disable_interrupt = wilc_sdio_disable_interrupt,
1022     .hif_reset = wilc_sdio_reset,
1023     .hif_is_init = wilc_sdio_is_init,
1024 };
1025 
1026 static int wilc_sdio_resume(struct device *dev)
1027 {
1028     struct sdio_func *func = dev_to_sdio_func(dev);
1029     struct wilc *wilc = sdio_get_drvdata(func);
1030 
1031     dev_info(dev, "sdio resume\n");
1032     sdio_release_host(func);
1033     chip_wakeup(wilc);
1034     wilc_sdio_init(wilc, true);
1035 
1036     if (wilc->suspend_event)
1037         host_wakeup_notify(wilc);
1038 
1039     chip_allow_sleep(wilc);
1040 
1041     return 0;
1042 }
1043 
1044 static const struct of_device_id wilc_of_match[] = {
1045     { .compatible = "microchip,wilc1000", },
1046     { /* sentinel */ }
1047 };
1048 MODULE_DEVICE_TABLE(of, wilc_of_match);
1049 
1050 static const struct dev_pm_ops wilc_sdio_pm_ops = {
1051     .suspend = wilc_sdio_suspend,
1052     .resume = wilc_sdio_resume,
1053 };
1054 
1055 static struct sdio_driver wilc_sdio_driver = {
1056     .name       = SDIO_MODALIAS,
1057     .id_table   = wilc_sdio_ids,
1058     .probe      = wilc_sdio_probe,
1059     .remove     = wilc_sdio_remove,
1060     .drv = {
1061         .pm = &wilc_sdio_pm_ops,
1062         .of_match_table = wilc_of_match,
1063     }
1064 };
1065 module_driver(wilc_sdio_driver,
1066           sdio_register_driver,
1067           sdio_unregister_driver);
1068 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!