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0007 #include "mt7601u.h"
0008 #include "trace.h"
0009
0010 enum mt76_txq_id {
0011 MT_TXQ_VO = IEEE80211_AC_VO,
0012 MT_TXQ_VI = IEEE80211_AC_VI,
0013 MT_TXQ_BE = IEEE80211_AC_BE,
0014 MT_TXQ_BK = IEEE80211_AC_BK,
0015 MT_TXQ_PSD,
0016 MT_TXQ_MCU,
0017 __MT_TXQ_MAX
0018 };
0019
0020
0021 static u8 q2hwq(u8 q)
0022 {
0023 return q ^ 0x3;
0024 }
0025
0026
0027 static u8 skb2q(struct sk_buff *skb)
0028 {
0029 int qid = skb_get_queue_mapping(skb);
0030
0031 if (WARN_ON(qid >= MT_TXQ_PSD)) {
0032 qid = MT_TXQ_BE;
0033 skb_set_queue_mapping(skb, qid);
0034 }
0035
0036 return q2hwq(qid);
0037 }
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
0055 static u8 mt7601u_tx_pktid_enc(struct mt7601u_dev *dev, u8 rate, bool is_probe)
0056 {
0057 u8 encoded = (rate + 1) + is_probe * 8;
0058
0059
0060
0061
0062
0063
0064 if (is_probe && rate == 7)
0065 return encoded - 7;
0066
0067 return encoded;
0068 }
0069
0070 static void
0071 mt7601u_tx_pktid_dec(struct mt7601u_dev *dev, struct mt76_tx_status *stat)
0072 {
0073 u8 req_rate = stat->pktid;
0074 u8 eff_rate = stat->rate & 0x7;
0075
0076 req_rate -= 1;
0077
0078 if (req_rate > 7) {
0079 stat->is_probe = true;
0080 req_rate -= 8;
0081
0082
0083 if (!req_rate && eff_rate)
0084 req_rate = 7;
0085 }
0086
0087 stat->retry = req_rate - eff_rate;
0088 }
0089
0090 static void mt7601u_tx_skb_remove_dma_overhead(struct sk_buff *skb,
0091 struct ieee80211_tx_info *info)
0092 {
0093 int pkt_len = (unsigned long)info->status.status_driver_data[0];
0094
0095 skb_pull(skb, sizeof(struct mt76_txwi) + 4);
0096 if (ieee80211_get_hdrlen_from_skb(skb) % 4)
0097 mt76_remove_hdr_pad(skb);
0098
0099 skb_trim(skb, pkt_len);
0100 }
0101
0102 void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb)
0103 {
0104 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
0105
0106 mt7601u_tx_skb_remove_dma_overhead(skb, info);
0107
0108 ieee80211_tx_info_clear_status(info);
0109 info->status.rates[0].idx = -1;
0110 info->flags |= IEEE80211_TX_STAT_ACK;
0111
0112 spin_lock_bh(&dev->mac_lock);
0113 ieee80211_tx_status(dev->hw, skb);
0114 spin_unlock_bh(&dev->mac_lock);
0115 }
0116
0117 static int mt7601u_skb_rooms(struct mt7601u_dev *dev, struct sk_buff *skb)
0118 {
0119 int hdr_len = ieee80211_get_hdrlen_from_skb(skb);
0120 u32 need_head;
0121
0122 need_head = sizeof(struct mt76_txwi) + 4;
0123 if (hdr_len % 4)
0124 need_head += 2;
0125
0126 return skb_cow(skb, need_head);
0127 }
0128
0129 static struct mt76_txwi *
0130 mt7601u_push_txwi(struct mt7601u_dev *dev, struct sk_buff *skb,
0131 struct ieee80211_sta *sta, struct mt76_wcid *wcid,
0132 int pkt_len)
0133 {
0134 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
0135 struct ieee80211_tx_rate *rate = &info->control.rates[0];
0136 struct mt76_txwi *txwi;
0137 unsigned long flags;
0138 bool is_probe;
0139 u32 pkt_id;
0140 u16 rate_ctl;
0141 u8 nss;
0142
0143 txwi = skb_push(skb, sizeof(struct mt76_txwi));
0144 memset(txwi, 0, sizeof(*txwi));
0145
0146 if (!wcid->tx_rate_set)
0147 ieee80211_get_tx_rates(info->control.vif, sta, skb,
0148 info->control.rates, 1);
0149
0150 spin_lock_irqsave(&dev->lock, flags);
0151 if (rate->idx < 0 || !rate->count)
0152 rate_ctl = wcid->tx_rate;
0153 else
0154 rate_ctl = mt76_mac_tx_rate_val(dev, rate, &nss);
0155 spin_unlock_irqrestore(&dev->lock, flags);
0156 txwi->rate_ctl = cpu_to_le16(rate_ctl);
0157
0158 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
0159 txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ;
0160 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
0161 txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ;
0162
0163 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) {
0164 u8 ba_size = IEEE80211_MIN_AMPDU_BUF;
0165
0166 ba_size <<= sta->deflink.ht_cap.ampdu_factor;
0167 ba_size = min_t(int, 63, ba_size);
0168 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
0169 ba_size = 0;
0170 txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size);
0171
0172 txwi->flags =
0173 cpu_to_le16(MT_TXWI_FLAGS_AMPDU |
0174 FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY,
0175 sta->deflink.ht_cap.ampdu_density));
0176 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
0177 txwi->flags = 0;
0178 }
0179
0180 txwi->wcid = wcid->idx;
0181
0182 is_probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
0183 pkt_id = mt7601u_tx_pktid_enc(dev, rate_ctl & 0x7, is_probe);
0184 pkt_len |= FIELD_PREP(MT_TXWI_LEN_PKTID, pkt_id);
0185 txwi->len_ctl = cpu_to_le16(pkt_len);
0186
0187 return txwi;
0188 }
0189
0190 void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
0191 struct sk_buff *skb)
0192 {
0193 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
0194 struct mt7601u_dev *dev = hw->priv;
0195 struct ieee80211_vif *vif = info->control.vif;
0196 struct ieee80211_sta *sta = control->sta;
0197 struct mt76_sta *msta = NULL;
0198 struct mt76_wcid *wcid = dev->mon_wcid;
0199 struct mt76_txwi *txwi;
0200 int pkt_len = skb->len;
0201 int hw_q = skb2q(skb);
0202
0203 BUILD_BUG_ON(ARRAY_SIZE(info->status.status_driver_data) < 1);
0204 info->status.status_driver_data[0] = (void *)(unsigned long)pkt_len;
0205
0206 if (mt7601u_skb_rooms(dev, skb) || mt76_insert_hdr_pad(skb)) {
0207 ieee80211_free_txskb(dev->hw, skb);
0208 return;
0209 }
0210
0211 if (sta) {
0212 msta = (struct mt76_sta *) sta->drv_priv;
0213 wcid = &msta->wcid;
0214 } else if (vif) {
0215 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
0216
0217 wcid = &mvif->group_wcid;
0218 }
0219
0220 txwi = mt7601u_push_txwi(dev, skb, sta, wcid, pkt_len);
0221
0222 if (mt7601u_dma_enqueue_tx(dev, skb, wcid, hw_q))
0223 return;
0224
0225 trace_mt_tx(dev, skb, msta, txwi);
0226 }
0227
0228 void mt7601u_tx_stat(struct work_struct *work)
0229 {
0230 struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev,
0231 stat_work.work);
0232 struct mt76_tx_status stat;
0233 unsigned long flags;
0234 int cleaned = 0;
0235
0236 while (!test_bit(MT7601U_STATE_REMOVED, &dev->state)) {
0237 stat = mt7601u_mac_fetch_tx_status(dev);
0238 if (!stat.valid)
0239 break;
0240
0241 mt7601u_tx_pktid_dec(dev, &stat);
0242 mt76_send_tx_status(dev, &stat);
0243
0244 cleaned++;
0245 }
0246 trace_mt_tx_status_cleaned(dev, cleaned);
0247
0248 spin_lock_irqsave(&dev->tx_lock, flags);
0249 if (cleaned)
0250 queue_delayed_work(dev->stat_wq, &dev->stat_work,
0251 msecs_to_jiffies(10));
0252 else if (test_and_clear_bit(MT7601U_STATE_MORE_STATS, &dev->state))
0253 queue_delayed_work(dev->stat_wq, &dev->stat_work,
0254 msecs_to_jiffies(20));
0255 else
0256 clear_bit(MT7601U_STATE_READING_STATS, &dev->state);
0257 spin_unlock_irqrestore(&dev->tx_lock, flags);
0258 }
0259
0260 int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
0261 unsigned int link_id, u16 queue,
0262 const struct ieee80211_tx_queue_params *params)
0263 {
0264 struct mt7601u_dev *dev = hw->priv;
0265 u8 cw_min = 5, cw_max = 10, hw_q = q2hwq(queue);
0266 u32 val;
0267
0268
0269
0270
0271
0272 if (params->cw_min)
0273 cw_min = fls(params->cw_min);
0274 if (params->cw_max)
0275 cw_max = fls(params->cw_max);
0276
0277 WARN_ON(params->txop > 0xff);
0278 WARN_ON(params->aifs > 0xf);
0279 WARN_ON(cw_min > 0xf);
0280 WARN_ON(cw_max > 0xf);
0281
0282 val = FIELD_PREP(MT_EDCA_CFG_AIFSN, params->aifs) |
0283 FIELD_PREP(MT_EDCA_CFG_CWMIN, cw_min) |
0284 FIELD_PREP(MT_EDCA_CFG_CWMAX, cw_max);
0285
0286
0287
0288
0289 if (!hw_q)
0290 val |= 0x60;
0291 else
0292 val |= FIELD_PREP(MT_EDCA_CFG_TXOP, params->txop);
0293 mt76_wr(dev, MT_EDCA_CFG_AC(hw_q), val);
0294
0295 val = mt76_rr(dev, MT_WMM_TXOP(hw_q));
0296 val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(hw_q));
0297 val |= params->txop << MT_WMM_TXOP_SHIFT(hw_q);
0298 mt76_wr(dev, MT_WMM_TXOP(hw_q), val);
0299
0300 val = mt76_rr(dev, MT_WMM_AIFSN);
0301 val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(hw_q));
0302 val |= params->aifs << MT_WMM_AIFSN_SHIFT(hw_q);
0303 mt76_wr(dev, MT_WMM_AIFSN, val);
0304
0305 val = mt76_rr(dev, MT_WMM_CWMIN);
0306 val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(hw_q));
0307 val |= cw_min << MT_WMM_CWMIN_SHIFT(hw_q);
0308 mt76_wr(dev, MT_WMM_CWMIN, val);
0309
0310 val = mt76_rr(dev, MT_WMM_CWMAX);
0311 val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(hw_q));
0312 val |= cw_max << MT_WMM_CWMAX_SHIFT(hw_q);
0313 mt76_wr(dev, MT_WMM_CWMAX, val);
0314
0315 return 0;
0316 }