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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * (c) Copyright 2002-2010, Ralink Technology, Inc.
0004  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
0005  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
0006  */
0007 
0008 #include "mt7601u.h"
0009 #include "mcu.h"
0010 #include "eeprom.h"
0011 #include "trace.h"
0012 #include "initvals_phy.h"
0013 
0014 #include <linux/etherdevice.h>
0015 
0016 static void mt7601u_agc_reset(struct mt7601u_dev *dev);
0017 
0018 static int
0019 mt7601u_rf_wr(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 value)
0020 {
0021     int ret = 0;
0022 
0023     if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) ||
0024         WARN_ON(offset > 63))
0025         return -EINVAL;
0026     if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
0027         return 0;
0028 
0029     mutex_lock(&dev->reg_atomic_mutex);
0030 
0031     if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) {
0032         ret = -ETIMEDOUT;
0033         goto out;
0034     }
0035 
0036     mt7601u_wr(dev, MT_RF_CSR_CFG,
0037            FIELD_PREP(MT_RF_CSR_CFG_DATA, value) |
0038            FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |
0039            FIELD_PREP(MT_RF_CSR_CFG_REG_ID, offset) |
0040            MT_RF_CSR_CFG_WR |
0041            MT_RF_CSR_CFG_KICK);
0042     trace_rf_write(dev, bank, offset, value);
0043 out:
0044     mutex_unlock(&dev->reg_atomic_mutex);
0045 
0046     if (ret < 0)
0047         dev_err(dev->dev, "Error: RF write %02hhx:%02hhx failed:%d!!\n",
0048             bank, offset, ret);
0049 
0050     return ret;
0051 }
0052 
0053 static int
0054 mt7601u_rf_rr(struct mt7601u_dev *dev, u8 bank, u8 offset)
0055 {
0056     int ret = -ETIMEDOUT;
0057     u32 val;
0058 
0059     if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) ||
0060         WARN_ON(offset > 63))
0061         return -EINVAL;
0062     if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
0063         return 0xff;
0064 
0065     mutex_lock(&dev->reg_atomic_mutex);
0066 
0067     if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))
0068         goto out;
0069 
0070     mt7601u_wr(dev, MT_RF_CSR_CFG,
0071            FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |
0072            FIELD_PREP(MT_RF_CSR_CFG_REG_ID, offset) |
0073            MT_RF_CSR_CFG_KICK);
0074 
0075     if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))
0076         goto out;
0077 
0078     val = mt7601u_rr(dev, MT_RF_CSR_CFG);
0079     if (FIELD_GET(MT_RF_CSR_CFG_REG_ID, val) == offset &&
0080         FIELD_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank) {
0081         ret = FIELD_GET(MT_RF_CSR_CFG_DATA, val);
0082         trace_rf_read(dev, bank, offset, ret);
0083     }
0084 out:
0085     mutex_unlock(&dev->reg_atomic_mutex);
0086 
0087     if (ret < 0)
0088         dev_err(dev->dev, "Error: RF read %02hhx:%02hhx failed:%d!!\n",
0089             bank, offset, ret);
0090 
0091     return ret;
0092 }
0093 
0094 static int
0095 mt7601u_rf_rmw(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask, u8 val)
0096 {
0097     int ret;
0098 
0099     ret = mt7601u_rf_rr(dev, bank, offset);
0100     if (ret < 0)
0101         return ret;
0102     val |= ret & ~mask;
0103     ret = mt7601u_rf_wr(dev, bank, offset, val);
0104     if (ret)
0105         return ret;
0106 
0107     return val;
0108 }
0109 
0110 static int
0111 mt7601u_rf_set(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 val)
0112 {
0113     return mt7601u_rf_rmw(dev, bank, offset, 0, val);
0114 }
0115 
0116 static int
0117 mt7601u_rf_clear(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask)
0118 {
0119     return mt7601u_rf_rmw(dev, bank, offset, mask, 0);
0120 }
0121 
0122 static void mt7601u_bbp_wr(struct mt7601u_dev *dev, u8 offset, u8 val)
0123 {
0124     if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) ||
0125         test_bit(MT7601U_STATE_REMOVED, &dev->state))
0126         return;
0127 
0128     mutex_lock(&dev->reg_atomic_mutex);
0129 
0130     if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) {
0131         dev_err(dev->dev, "Error: BBP write %02hhx failed!!\n", offset);
0132         goto out;
0133     }
0134 
0135     mt7601u_wr(dev, MT_BBP_CSR_CFG,
0136            FIELD_PREP(MT_BBP_CSR_CFG_VAL, val) |
0137            FIELD_PREP(MT_BBP_CSR_CFG_REG_NUM, offset) |
0138            MT_BBP_CSR_CFG_RW_MODE | MT_BBP_CSR_CFG_BUSY);
0139     trace_bbp_write(dev, offset, val);
0140 out:
0141     mutex_unlock(&dev->reg_atomic_mutex);
0142 }
0143 
0144 static int mt7601u_bbp_rr(struct mt7601u_dev *dev, u8 offset)
0145 {
0146     u32 val;
0147     int ret = -ETIMEDOUT;
0148 
0149     if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)))
0150         return -EINVAL;
0151     if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
0152         return 0xff;
0153 
0154     mutex_lock(&dev->reg_atomic_mutex);
0155 
0156     if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000))
0157         goto out;
0158 
0159     mt7601u_wr(dev, MT_BBP_CSR_CFG,
0160            FIELD_PREP(MT_BBP_CSR_CFG_REG_NUM, offset) |
0161            MT_BBP_CSR_CFG_RW_MODE | MT_BBP_CSR_CFG_BUSY |
0162            MT_BBP_CSR_CFG_READ);
0163 
0164     if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000))
0165         goto out;
0166 
0167     val = mt7601u_rr(dev, MT_BBP_CSR_CFG);
0168     if (FIELD_GET(MT_BBP_CSR_CFG_REG_NUM, val) == offset) {
0169         ret = FIELD_GET(MT_BBP_CSR_CFG_VAL, val);
0170         trace_bbp_read(dev, offset, ret);
0171     }
0172 out:
0173     mutex_unlock(&dev->reg_atomic_mutex);
0174 
0175     if (ret < 0)
0176         dev_err(dev->dev, "Error: BBP read %02hhx failed:%d!!\n",
0177             offset, ret);
0178 
0179     return ret;
0180 }
0181 
0182 static int mt7601u_bbp_rmw(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val)
0183 {
0184     int ret;
0185 
0186     ret = mt7601u_bbp_rr(dev, offset);
0187     if (ret < 0)
0188         return ret;
0189     val |= ret & ~mask;
0190     mt7601u_bbp_wr(dev, offset, val);
0191 
0192     return val;
0193 }
0194 
0195 static u8 mt7601u_bbp_rmc(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val)
0196 {
0197     int ret;
0198 
0199     ret = mt7601u_bbp_rr(dev, offset);
0200     if (ret < 0)
0201         return ret;
0202     val |= ret & ~mask;
0203     if (ret != val)
0204         mt7601u_bbp_wr(dev, offset, val);
0205 
0206     return val;
0207 }
0208 
0209 int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev)
0210 {
0211     int i = 20;
0212     u8 val;
0213 
0214     do {
0215         val = mt7601u_bbp_rr(dev, MT_BBP_REG_VERSION);
0216         if (val && val != 0xff)
0217             break;
0218     } while (--i);
0219 
0220     if (!i) {
0221         dev_err(dev->dev, "Error: BBP is not ready\n");
0222         return -EIO;
0223     }
0224 
0225     return 0;
0226 }
0227 
0228 u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below)
0229 {
0230     return mt7601u_bbp_rmc(dev, 3, 0x20, below ? 0x20 : 0);
0231 }
0232 
0233 int mt7601u_phy_get_rssi(struct mt7601u_dev *dev,
0234              struct mt7601u_rxwi *rxwi, u16 rate)
0235 {
0236     static const s8 lna[2][2][3] = {
0237         /* main LNA */ {
0238             /* bw20 */ { -2, 15, 33 },
0239             /* bw40 */ {  0, 16, 34 }
0240         },
0241         /*  aux LNA */ {
0242             /* bw20 */ { -2, 15, 33 },
0243             /* bw40 */ { -2, 16, 34 }
0244         }
0245     };
0246     int bw = FIELD_GET(MT_RXWI_RATE_BW, rate);
0247     int aux_lna = FIELD_GET(MT_RXWI_ANT_AUX_LNA, rxwi->ant);
0248     int lna_id = FIELD_GET(MT_RXWI_GAIN_RSSI_LNA_ID, rxwi->gain);
0249     int val;
0250 
0251     if (lna_id) /* LNA id can be 0, 2, 3. */
0252         lna_id--;
0253 
0254     val = 8;
0255     val -= lna[aux_lna][bw][lna_id];
0256     val -= FIELD_GET(MT_RXWI_GAIN_RSSI_VAL, rxwi->gain);
0257     val -= dev->ee->lna_gain;
0258     val -= dev->ee->rssi_offset[0];
0259 
0260     return val;
0261 }
0262 
0263 static void mt7601u_vco_cal(struct mt7601u_dev *dev)
0264 {
0265     mt7601u_rf_wr(dev, 0, 4, 0x0a);
0266     mt7601u_rf_wr(dev, 0, 5, 0x20);
0267     mt7601u_rf_set(dev, 0, 4, BIT(7));
0268     msleep(2);
0269 }
0270 
0271 static int mt7601u_set_bw_filter(struct mt7601u_dev *dev, bool cal)
0272 {
0273     u32 filter = 0;
0274     int ret;
0275 
0276     if (!cal)
0277         filter |= 0x10000;
0278     if (dev->bw != MT_BW_20)
0279         filter |= 0x00100;
0280 
0281     /* TX */
0282     ret = mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter | 1);
0283     if (ret)
0284         return ret;
0285     /* RX */
0286     return mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter);
0287 }
0288 
0289 static int mt7601u_load_bbp_temp_table_bw(struct mt7601u_dev *dev)
0290 {
0291     const struct reg_table *t;
0292 
0293     if (WARN_ON(dev->temp_mode > MT_TEMP_MODE_LOW))
0294         return -EINVAL;
0295 
0296     t = &bbp_mode_table[dev->temp_mode][dev->bw];
0297 
0298     return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, t->regs, t->n);
0299 }
0300 
0301 static int mt7601u_bbp_temp(struct mt7601u_dev *dev, int mode, const char *name)
0302 {
0303     const struct reg_table *t;
0304     int ret;
0305 
0306     if (dev->temp_mode == mode)
0307         return 0;
0308 
0309     dev->temp_mode = mode;
0310     trace_temp_mode(dev, mode);
0311 
0312     t = bbp_mode_table[dev->temp_mode];
0313     ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,
0314                       t[2].regs, t[2].n);
0315     if (ret)
0316         return ret;
0317 
0318     return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,
0319                        t[dev->bw].regs, t[dev->bw].n);
0320 }
0321 
0322 static void mt7601u_apply_ch14_fixup(struct mt7601u_dev *dev, int hw_chan)
0323 {
0324     struct mt7601u_rate_power *t = &dev->ee->power_rate_table;
0325 
0326     if (hw_chan != 14 || dev->bw != MT_BW_20) {
0327         mt7601u_bbp_rmw(dev, 4, 0x20, 0);
0328         mt7601u_bbp_wr(dev, 178, 0xff);
0329 
0330         t->cck[0].bw20 = dev->ee->real_cck_bw20[0];
0331         t->cck[1].bw20 = dev->ee->real_cck_bw20[1];
0332     } else { /* Apply CH14 OBW fixup */
0333         mt7601u_bbp_wr(dev, 4, 0x60);
0334         mt7601u_bbp_wr(dev, 178, 0);
0335 
0336         /* Note: vendor code is buggy here for negative values */
0337         t->cck[0].bw20 = dev->ee->real_cck_bw20[0] - 2;
0338         t->cck[1].bw20 = dev->ee->real_cck_bw20[1] - 2;
0339     }
0340 }
0341 
0342 static int __mt7601u_phy_set_channel(struct mt7601u_dev *dev,
0343                      struct cfg80211_chan_def *chandef)
0344 {
0345 #define FREQ_PLAN_REGS  4
0346     static const u8 freq_plan[14][FREQ_PLAN_REGS] = {
0347         { 0x99, 0x99,   0x09,   0x50 },
0348         { 0x46, 0x44,   0x0a,   0x50 },
0349         { 0xec, 0xee,   0x0a,   0x50 },
0350         { 0x99, 0x99,   0x0b,   0x50 },
0351         { 0x46, 0x44,   0x08,   0x51 },
0352         { 0xec, 0xee,   0x08,   0x51 },
0353         { 0x99, 0x99,   0x09,   0x51 },
0354         { 0x46, 0x44,   0x0a,   0x51 },
0355         { 0xec, 0xee,   0x0a,   0x51 },
0356         { 0x99, 0x99,   0x0b,   0x51 },
0357         { 0x46, 0x44,   0x08,   0x52 },
0358         { 0xec, 0xee,   0x08,   0x52 },
0359         { 0x99, 0x99,   0x09,   0x52 },
0360         { 0x33, 0x33,   0x0b,   0x52 },
0361     };
0362     struct mt76_reg_pair channel_freq_plan[FREQ_PLAN_REGS] = {
0363         { 17, 0 }, { 18, 0 }, { 19, 0 }, { 20, 0 },
0364     };
0365     struct mt76_reg_pair bbp_settings[3] = {
0366         { 62, 0x37 - dev->ee->lna_gain },
0367         { 63, 0x37 - dev->ee->lna_gain },
0368         { 64, 0x37 - dev->ee->lna_gain },
0369     };
0370 
0371     struct ieee80211_channel *chan = chandef->chan;
0372     enum nl80211_channel_type chan_type =
0373         cfg80211_get_chandef_type(chandef);
0374     struct mt7601u_rate_power *t = &dev->ee->power_rate_table;
0375     int chan_idx;
0376     bool chan_ext_below;
0377     u8 bw;
0378     int i, ret;
0379 
0380     bw = MT_BW_20;
0381     chan_ext_below = (chan_type == NL80211_CHAN_HT40MINUS);
0382     chan_idx = chan->hw_value - 1;
0383 
0384     if (chandef->width == NL80211_CHAN_WIDTH_40) {
0385         bw = MT_BW_40;
0386 
0387         if (chan_idx > 1 && chan_type == NL80211_CHAN_HT40MINUS)
0388             chan_idx -= 2;
0389         else if (chan_idx < 12 && chan_type == NL80211_CHAN_HT40PLUS)
0390             chan_idx += 2;
0391         else
0392             dev_err(dev->dev, "Error: invalid 40MHz channel!!\n");
0393     }
0394 
0395     if (bw != dev->bw || chan_ext_below != dev->chan_ext_below) {
0396         dev_dbg(dev->dev, "Info: switching HT mode bw:%d below:%d\n",
0397             bw, chan_ext_below);
0398 
0399         mt7601u_bbp_set_bw(dev, bw);
0400 
0401         mt7601u_bbp_set_ctrlch(dev, chan_ext_below);
0402         mt7601u_mac_set_ctrlch(dev, chan_ext_below);
0403         dev->chan_ext_below = chan_ext_below;
0404     }
0405 
0406     for (i = 0; i < FREQ_PLAN_REGS; i++)
0407         channel_freq_plan[i].value = freq_plan[chan_idx][i];
0408 
0409     ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_RF,
0410                       channel_freq_plan, FREQ_PLAN_REGS);
0411     if (ret)
0412         return ret;
0413 
0414     mt7601u_rmw(dev, MT_TX_ALC_CFG_0, 0x3f3f,
0415             dev->ee->chan_pwr[chan_idx] & 0x3f);
0416 
0417     ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,
0418                       bbp_settings, ARRAY_SIZE(bbp_settings));
0419     if (ret)
0420         return ret;
0421 
0422     mt7601u_vco_cal(dev);
0423     mt7601u_bbp_set_bw(dev, bw);
0424     ret = mt7601u_set_bw_filter(dev, false);
0425     if (ret)
0426         return ret;
0427 
0428     mt7601u_apply_ch14_fixup(dev, chan->hw_value);
0429     mt7601u_wr(dev, MT_TX_PWR_CFG_0, int_to_s6(t->ofdm[1].bw20) << 24 |
0430                      int_to_s6(t->ofdm[0].bw20) << 16 |
0431                      int_to_s6(t->cck[1].bw20) << 8 |
0432                      int_to_s6(t->cck[0].bw20));
0433 
0434     if (test_bit(MT7601U_STATE_SCANNING, &dev->state))
0435         mt7601u_agc_reset(dev);
0436 
0437     dev->chandef = *chandef;
0438 
0439     return 0;
0440 }
0441 
0442 int mt7601u_phy_set_channel(struct mt7601u_dev *dev,
0443                 struct cfg80211_chan_def *chandef)
0444 {
0445     int ret;
0446 
0447     cancel_delayed_work_sync(&dev->cal_work);
0448     cancel_delayed_work_sync(&dev->freq_cal.work);
0449 
0450     mutex_lock(&dev->hw_atomic_mutex);
0451     ret = __mt7601u_phy_set_channel(dev, chandef);
0452     mutex_unlock(&dev->hw_atomic_mutex);
0453     if (ret)
0454         return ret;
0455 
0456     if (test_bit(MT7601U_STATE_SCANNING, &dev->state))
0457         return 0;
0458 
0459     ieee80211_queue_delayed_work(dev->hw, &dev->cal_work,
0460                      MT_CALIBRATE_INTERVAL);
0461     if (dev->freq_cal.enabled)
0462         ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work,
0463                          MT_FREQ_CAL_INIT_DELAY);
0464     return 0;
0465 }
0466 
0467 #define BBP_R47_FLAG        GENMASK(2, 0)
0468 #define BBP_R47_F_TSSI      0
0469 #define BBP_R47_F_PKT_T     1
0470 #define BBP_R47_F_TX_RATE   2
0471 #define BBP_R47_F_TEMP      4
0472 /**
0473  * mt7601u_bbp_r47_get - read value through BBP R47/R49 pair
0474  * @dev:    pointer to adapter structure
0475  * @reg:    value of BBP R47 before the operation
0476  * @flag:   one of the BBP_R47_F_* flags
0477  *
0478  * Convenience helper for reading values through BBP R47/R49 pair.
0479  * Takes old value of BBP R47 as @reg, because callers usually have it
0480  * cached already.
0481  *
0482  * Return: value of BBP R49.
0483  */
0484 static u8 mt7601u_bbp_r47_get(struct mt7601u_dev *dev, u8 reg, u8 flag)
0485 {
0486     flag |= reg & ~BBP_R47_FLAG;
0487     mt7601u_bbp_wr(dev, 47, flag);
0488     usleep_range(500, 700);
0489     return mt7601u_bbp_rr(dev, 49);
0490 }
0491 
0492 static s8 mt7601u_read_bootup_temp(struct mt7601u_dev *dev)
0493 {
0494     u8 bbp_val, temp;
0495     u32 rf_bp, rf_set;
0496     int i;
0497 
0498     rf_set = mt7601u_rr(dev, MT_RF_SETTING_0);
0499     rf_bp = mt7601u_rr(dev, MT_RF_BYPASS_0);
0500 
0501     mt7601u_wr(dev, MT_RF_BYPASS_0, 0);
0502     mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000010);
0503     mt7601u_wr(dev, MT_RF_BYPASS_0, 0x00000010);
0504 
0505     bbp_val = mt7601u_bbp_rmw(dev, 47, 0, 0x10);
0506 
0507     mt7601u_bbp_wr(dev, 22, 0x40);
0508 
0509     for (i = 100; i && (bbp_val & 0x10); i--)
0510         bbp_val = mt7601u_bbp_rr(dev, 47);
0511 
0512     temp = mt7601u_bbp_r47_get(dev, bbp_val, BBP_R47_F_TEMP);
0513 
0514     mt7601u_bbp_wr(dev, 22, 0);
0515 
0516     bbp_val = mt7601u_bbp_rr(dev, 21);
0517     bbp_val |= 0x02;
0518     mt7601u_bbp_wr(dev, 21, bbp_val);
0519     bbp_val &= ~0x02;
0520     mt7601u_bbp_wr(dev, 21, bbp_val);
0521 
0522     mt7601u_wr(dev, MT_RF_BYPASS_0, 0);
0523     mt7601u_wr(dev, MT_RF_SETTING_0, rf_set);
0524     mt7601u_wr(dev, MT_RF_BYPASS_0, rf_bp);
0525 
0526     trace_read_temp(dev, temp);
0527     return temp;
0528 }
0529 
0530 static s8 mt7601u_read_temp(struct mt7601u_dev *dev)
0531 {
0532     int i;
0533     u8 val;
0534     s8 temp;
0535 
0536     val = mt7601u_bbp_rmw(dev, 47, 0x7f, 0x10);
0537 
0538     /* Note: this rarely succeeds, temp can change even if it fails. */
0539     for (i = 100; i && (val & 0x10); i--)
0540         val = mt7601u_bbp_rr(dev, 47);
0541 
0542     temp = mt7601u_bbp_r47_get(dev, val, BBP_R47_F_TEMP);
0543 
0544     trace_read_temp(dev, temp);
0545     return temp;
0546 }
0547 
0548 static void mt7601u_rxdc_cal(struct mt7601u_dev *dev)
0549 {
0550     static const struct mt76_reg_pair intro[] = {
0551         { 158, 0x8d }, { 159, 0xfc },
0552         { 158, 0x8c }, { 159, 0x4c },
0553     }, outro[] = {
0554         { 158, 0x8d }, { 159, 0xe0 },
0555     };
0556     u32 mac_ctrl;
0557     int i, ret;
0558 
0559     mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL);
0560     mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX);
0561 
0562     ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,
0563                       intro, ARRAY_SIZE(intro));
0564     if (ret)
0565         dev_err(dev->dev, "%s intro failed:%d\n", __func__, ret);
0566 
0567     for (i = 20; i; i--) {
0568         usleep_range(300, 500);
0569 
0570         mt7601u_bbp_wr(dev, 158, 0x8c);
0571         if (mt7601u_bbp_rr(dev, 159) == 0x0c)
0572             break;
0573     }
0574     if (!i)
0575         dev_err(dev->dev, "%s timed out\n", __func__);
0576 
0577     mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);
0578 
0579     ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,
0580                       outro, ARRAY_SIZE(outro));
0581     if (ret)
0582         dev_err(dev->dev, "%s outro failed:%d\n", __func__, ret);
0583 
0584     mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);
0585 }
0586 
0587 void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev)
0588 {
0589     if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
0590         return;
0591 
0592     mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->curr_temp);
0593 
0594     mt7601u_rxdc_cal(dev);
0595 }
0596 
0597 /* Note: function copied from vendor driver */
0598 static s16 lin2dBd(u16 linear)
0599 {
0600     short exp = 0;
0601     unsigned int mantisa;
0602     int app, dBd;
0603 
0604     if (WARN_ON(!linear))
0605         return -10000;
0606 
0607     mantisa = linear;
0608 
0609     exp = fls(mantisa) - 16;
0610     if (exp > 0)
0611         mantisa >>= exp;
0612     else
0613         mantisa <<= abs(exp);
0614 
0615     if (mantisa <= 0xb800)
0616         app = (mantisa + (mantisa >> 3) + (mantisa >> 4) - 0x9600);
0617     else
0618         app = (mantisa - (mantisa >> 3) - (mantisa >> 6) - 0x5a00);
0619     if (app < 0)
0620         app = 0;
0621 
0622     dBd = ((15 + exp) << 15) + app;
0623     dBd = (dBd << 2) + (dBd << 1) + (dBd >> 6) + (dBd >> 7);
0624     dBd = (dBd >> 10);
0625 
0626     return dBd;
0627 }
0628 
0629 static void
0630 mt7601u_set_initial_tssi(struct mt7601u_dev *dev, s16 tssi_db, s16 tssi_hvga_db)
0631 {
0632     struct tssi_data *d = &dev->ee->tssi_data;
0633     int init_offset;
0634 
0635     init_offset = -((tssi_db * d->slope + d->offset[1]) / 4096) + 10;
0636 
0637     mt76_rmw(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
0638          int_to_s6(init_offset) & MT_TX_ALC_CFG_1_TEMP_COMP);
0639 }
0640 
0641 static void mt7601u_tssi_dc_gain_cal(struct mt7601u_dev *dev)
0642 {
0643     u8 rf_vga, rf_mixer, bbp_r47;
0644     int i, j;
0645     s8 res[4];
0646     s16 tssi_init_db, tssi_init_hvga_db;
0647 
0648     mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000030);
0649     mt7601u_wr(dev, MT_RF_BYPASS_0, 0x000c0030);
0650     mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);
0651 
0652     mt7601u_bbp_wr(dev, 58, 0);
0653     mt7601u_bbp_wr(dev, 241, 0x2);
0654     mt7601u_bbp_wr(dev, 23, 0x8);
0655     bbp_r47 = mt7601u_bbp_rr(dev, 47);
0656 
0657     /* Set VGA gain */
0658     rf_vga = mt7601u_rf_rr(dev, 5, 3);
0659     mt7601u_rf_wr(dev, 5, 3, 8);
0660 
0661     /* Mixer disable */
0662     rf_mixer = mt7601u_rf_rr(dev, 4, 39);
0663     mt7601u_rf_wr(dev, 4, 39, 0);
0664 
0665     for (i = 0; i < 4; i++) {
0666         mt7601u_rf_wr(dev, 4, 39, (i & 1) ? rf_mixer : 0);
0667 
0668         mt7601u_bbp_wr(dev, 23, (i < 2) ? 0x08 : 0x02);
0669         mt7601u_rf_wr(dev, 5, 3, (i < 2) ? 0x08 : 0x11);
0670 
0671         /* BBP TSSI initial and soft reset */
0672         mt7601u_bbp_wr(dev, 22, 0);
0673         mt7601u_bbp_wr(dev, 244, 0);
0674 
0675         mt7601u_bbp_wr(dev, 21, 1);
0676         udelay(1);
0677         mt7601u_bbp_wr(dev, 21, 0);
0678 
0679         /* TSSI measurement */
0680         mt7601u_bbp_wr(dev, 47, 0x50);
0681         mt7601u_bbp_wr(dev, (i & 1) ? 244 : 22, (i & 1) ? 0x31 : 0x40);
0682 
0683         for (j = 20; j; j--)
0684             if (!(mt7601u_bbp_rr(dev, 47) & 0x10))
0685                 break;
0686         if (!j)
0687             dev_err(dev->dev, "%s timed out\n", __func__);
0688 
0689         /* TSSI read */
0690         mt7601u_bbp_wr(dev, 47, 0x40);
0691         res[i] = mt7601u_bbp_rr(dev, 49);
0692     }
0693 
0694     tssi_init_db = lin2dBd((short)res[1] - res[0]);
0695     tssi_init_hvga_db = lin2dBd(((short)res[3] - res[2]) * 4);
0696     dev->tssi_init = res[0];
0697     dev->tssi_init_hvga = res[2];
0698     dev->tssi_init_hvga_offset_db = tssi_init_hvga_db - tssi_init_db;
0699 
0700     dev_dbg(dev->dev,
0701         "TSSI_init:%hhx db:%hx hvga:%hhx hvga_db:%hx off_db:%hx\n",
0702         dev->tssi_init, tssi_init_db, dev->tssi_init_hvga,
0703         tssi_init_hvga_db, dev->tssi_init_hvga_offset_db);
0704 
0705     mt7601u_bbp_wr(dev, 22, 0);
0706     mt7601u_bbp_wr(dev, 244, 0);
0707 
0708     mt7601u_bbp_wr(dev, 21, 1);
0709     udelay(1);
0710     mt7601u_bbp_wr(dev, 21, 0);
0711 
0712     mt7601u_wr(dev, MT_RF_BYPASS_0, 0);
0713     mt7601u_wr(dev, MT_RF_SETTING_0, 0);
0714 
0715     mt7601u_rf_wr(dev, 5, 3, rf_vga);
0716     mt7601u_rf_wr(dev, 4, 39, rf_mixer);
0717     mt7601u_bbp_wr(dev, 47, bbp_r47);
0718 
0719     mt7601u_set_initial_tssi(dev, tssi_init_db, tssi_init_hvga_db);
0720 }
0721 
0722 static int mt7601u_temp_comp(struct mt7601u_dev *dev, bool on)
0723 {
0724     int ret, temp, hi_temp = 400, lo_temp = -200;
0725 
0726     temp = (dev->raw_temp - dev->ee->ref_temp) * MT_EE_TEMPERATURE_SLOPE;
0727     dev->curr_temp = temp;
0728 
0729     /* DPD Calibration */
0730     if (temp - dev->dpd_temp > 450 || temp - dev->dpd_temp < -450) {
0731         dev->dpd_temp = temp;
0732 
0733         ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp);
0734         if (ret)
0735             return ret;
0736 
0737         mt7601u_vco_cal(dev);
0738 
0739         dev_dbg(dev->dev, "Recalibrate DPD\n");
0740     }
0741 
0742     /* PLL Lock Protect */
0743     if (temp < -50 && !dev->pll_lock_protect) { /* < 20C */
0744         dev->pll_lock_protect =  true;
0745 
0746         mt7601u_rf_wr(dev, 4, 4, 6);
0747         mt7601u_rf_clear(dev, 4, 10, 0x30);
0748 
0749         dev_dbg(dev->dev, "PLL lock protect on - too cold\n");
0750     } else if (temp > 50 && dev->pll_lock_protect) { /* > 30C */
0751         dev->pll_lock_protect = false;
0752 
0753         mt7601u_rf_wr(dev, 4, 4, 0);
0754         mt7601u_rf_rmw(dev, 4, 10, 0x30, 0x10);
0755 
0756         dev_dbg(dev->dev, "PLL lock protect off\n");
0757     }
0758 
0759     if (on) {
0760         hi_temp -= 50;
0761         lo_temp -= 50;
0762     }
0763 
0764     /* BBP CR for H, L, N temperature */
0765     if (temp > hi_temp)
0766         return mt7601u_bbp_temp(dev, MT_TEMP_MODE_HIGH, "high");
0767     else if (temp > lo_temp)
0768         return mt7601u_bbp_temp(dev, MT_TEMP_MODE_NORMAL, "normal");
0769     else
0770         return mt7601u_bbp_temp(dev, MT_TEMP_MODE_LOW, "low");
0771 }
0772 
0773 /* Note: this is used only with TSSI, we can just use trgt_pwr from eeprom. */
0774 static int mt7601u_current_tx_power(struct mt7601u_dev *dev)
0775 {
0776     return dev->ee->chan_pwr[dev->chandef.chan->hw_value - 1];
0777 }
0778 
0779 static bool mt7601u_use_hvga(struct mt7601u_dev *dev)
0780 {
0781     return !(mt7601u_current_tx_power(dev) > 20);
0782 }
0783 
0784 static s16
0785 mt7601u_phy_rf_pa_mode_val(struct mt7601u_dev *dev, int phy_mode, int tx_rate)
0786 {
0787     static const s16 decode_tb[] = { 0, 8847, -5734, -5734 };
0788     u32 reg;
0789 
0790     switch (phy_mode) {
0791     case MT_PHY_TYPE_OFDM:
0792         tx_rate += 4;
0793         fallthrough;
0794     case MT_PHY_TYPE_CCK:
0795         reg = dev->rf_pa_mode[0];
0796         break;
0797     default:
0798         reg = dev->rf_pa_mode[1];
0799         break;
0800     }
0801 
0802     return decode_tb[(reg >> (tx_rate * 2)) & 0x3];
0803 }
0804 
0805 static struct mt7601u_tssi_params
0806 mt7601u_tssi_params_get(struct mt7601u_dev *dev)
0807 {
0808     static const u8 ofdm_pkt2rate[8] = { 6, 4, 2, 0, 7, 5, 3, 1 };
0809     static const int static_power[4] = { 0, -49152, -98304, 49152 };
0810     struct mt7601u_tssi_params p;
0811     u8 bbp_r47, pkt_type, tx_rate;
0812     struct power_per_rate *rate_table;
0813 
0814     bbp_r47 = mt7601u_bbp_rr(dev, 47);
0815 
0816     p.tssi0 = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TSSI);
0817     dev->raw_temp = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TEMP);
0818     pkt_type = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_PKT_T);
0819 
0820     p.trgt_power = mt7601u_current_tx_power(dev);
0821 
0822     switch (pkt_type & 0x03) {
0823     case MT_PHY_TYPE_CCK:
0824         tx_rate = (pkt_type >> 4) & 0x03;
0825         rate_table = dev->ee->power_rate_table.cck;
0826         break;
0827 
0828     case MT_PHY_TYPE_OFDM:
0829         tx_rate = ofdm_pkt2rate[(pkt_type >> 4) & 0x07];
0830         rate_table = dev->ee->power_rate_table.ofdm;
0831         break;
0832 
0833     default:
0834         tx_rate = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TX_RATE);
0835         tx_rate &= 0x7f;
0836         rate_table = dev->ee->power_rate_table.ht;
0837         break;
0838     }
0839 
0840     if (dev->bw == MT_BW_20)
0841         p.trgt_power += rate_table[tx_rate / 2].bw20;
0842     else
0843         p.trgt_power += rate_table[tx_rate / 2].bw40;
0844 
0845     p.trgt_power <<= 12;
0846 
0847     dev_dbg(dev->dev, "tx_rate:%02hhx pwr:%08x\n", tx_rate, p.trgt_power);
0848 
0849     p.trgt_power += mt7601u_phy_rf_pa_mode_val(dev, pkt_type & 0x03,
0850                            tx_rate);
0851 
0852     /* Channel 14, cck, bw20 */
0853     if ((pkt_type & 0x03) == MT_PHY_TYPE_CCK) {
0854         if (mt7601u_bbp_rr(dev, 4) & 0x20)
0855             p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 18022 : 9830;
0856         else
0857             p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 819 : 24576;
0858     }
0859 
0860     p.trgt_power += static_power[mt7601u_bbp_rr(dev, 1) & 0x03];
0861 
0862     p.trgt_power += dev->ee->tssi_data.tx0_delta_offset;
0863 
0864     dev_dbg(dev->dev,
0865         "tssi:%02hhx t_power:%08x temp:%02hhx pkt_type:%02hhx\n",
0866         p.tssi0, p.trgt_power, dev->raw_temp, pkt_type);
0867 
0868     return p;
0869 }
0870 
0871 static bool mt7601u_tssi_read_ready(struct mt7601u_dev *dev)
0872 {
0873     return !(mt7601u_bbp_rr(dev, 47) & 0x10);
0874 }
0875 
0876 static int mt7601u_tssi_cal(struct mt7601u_dev *dev)
0877 {
0878     struct mt7601u_tssi_params params;
0879     int curr_pwr, diff_pwr;
0880     char tssi_offset;
0881     s8 tssi_init;
0882     s16 tssi_m_dc, tssi_db;
0883     bool hvga;
0884     u32 val;
0885 
0886     if (!dev->ee->tssi_enabled)
0887         return 0;
0888 
0889     hvga = mt7601u_use_hvga(dev);
0890     if (!dev->tssi_read_trig)
0891         return mt7601u_mcu_tssi_read_kick(dev, hvga);
0892 
0893     if (!mt7601u_tssi_read_ready(dev))
0894         return 0;
0895 
0896     params = mt7601u_tssi_params_get(dev);
0897 
0898     tssi_init = (hvga ? dev->tssi_init_hvga : dev->tssi_init);
0899     tssi_m_dc = params.tssi0 - tssi_init;
0900     tssi_db = lin2dBd(tssi_m_dc);
0901     dev_dbg(dev->dev, "tssi dc:%04hx db:%04hx hvga:%d\n",
0902         tssi_m_dc, tssi_db, hvga);
0903 
0904     if (dev->chandef.chan->hw_value < 5)
0905         tssi_offset = dev->ee->tssi_data.offset[0];
0906     else if (dev->chandef.chan->hw_value < 9)
0907         tssi_offset = dev->ee->tssi_data.offset[1];
0908     else
0909         tssi_offset = dev->ee->tssi_data.offset[2];
0910 
0911     if (hvga)
0912         tssi_db -= dev->tssi_init_hvga_offset_db;
0913 
0914     curr_pwr = tssi_db * dev->ee->tssi_data.slope + (tssi_offset << 9);
0915     diff_pwr = params.trgt_power - curr_pwr;
0916     dev_dbg(dev->dev, "Power curr:%08x diff:%08x\n", curr_pwr, diff_pwr);
0917 
0918     if (params.tssi0 > 126 && diff_pwr > 0) {
0919         dev_err(dev->dev, "Error: TSSI upper saturation\n");
0920         diff_pwr = 0;
0921     }
0922     if (params.tssi0 - tssi_init < 1 && diff_pwr < 0) {
0923         dev_err(dev->dev, "Error: TSSI lower saturation\n");
0924         diff_pwr = 0;
0925     }
0926 
0927     if ((dev->prev_pwr_diff ^ diff_pwr) < 0 && abs(diff_pwr) < 4096 &&
0928         (abs(diff_pwr) > abs(dev->prev_pwr_diff) ||
0929          (diff_pwr > 0 && diff_pwr == -dev->prev_pwr_diff)))
0930         diff_pwr = 0;
0931     else
0932         dev->prev_pwr_diff = diff_pwr;
0933 
0934     diff_pwr += (diff_pwr > 0) ? 2048 : -2048;
0935     diff_pwr /= 4096;
0936 
0937     dev_dbg(dev->dev, "final diff: %08x\n", diff_pwr);
0938 
0939     val = mt7601u_rr(dev, MT_TX_ALC_CFG_1);
0940     curr_pwr = s6_to_int(FIELD_GET(MT_TX_ALC_CFG_1_TEMP_COMP, val));
0941     diff_pwr += curr_pwr;
0942     val = (val & ~MT_TX_ALC_CFG_1_TEMP_COMP) | int_to_s6(diff_pwr);
0943     mt7601u_wr(dev, MT_TX_ALC_CFG_1, val);
0944 
0945     return mt7601u_mcu_tssi_read_kick(dev, hvga);
0946 }
0947 
0948 static u8 mt7601u_agc_default(struct mt7601u_dev *dev)
0949 {
0950     return (dev->ee->lna_gain - 8) * 2 + 0x34;
0951 }
0952 
0953 static void mt7601u_agc_reset(struct mt7601u_dev *dev)
0954 {
0955     u8 agc = mt7601u_agc_default(dev);
0956 
0957     mt7601u_bbp_wr(dev, 66, agc);
0958 }
0959 
0960 void mt7601u_agc_save(struct mt7601u_dev *dev)
0961 {
0962     dev->agc_save = mt7601u_bbp_rr(dev, 66);
0963 }
0964 
0965 void mt7601u_agc_restore(struct mt7601u_dev *dev)
0966 {
0967     mt7601u_bbp_wr(dev, 66, dev->agc_save);
0968 }
0969 
0970 static void mt7601u_agc_tune(struct mt7601u_dev *dev)
0971 {
0972     u8 val = mt7601u_agc_default(dev);
0973     long avg_rssi;
0974 
0975     if (test_bit(MT7601U_STATE_SCANNING, &dev->state))
0976         return;
0977 
0978     /* Note: only in STA mode and not dozing; perhaps do this only if
0979      *   there is enough rssi updates since last run?
0980      *   Rssi updates are only on beacons and U2M so should work...
0981      */
0982     spin_lock_bh(&dev->con_mon_lock);
0983     avg_rssi = ewma_rssi_read(&dev->avg_rssi);
0984     spin_unlock_bh(&dev->con_mon_lock);
0985     if (avg_rssi == 0)
0986         return;
0987 
0988     avg_rssi = -avg_rssi;
0989     if (avg_rssi <= -70)
0990         val -= 0x20;
0991     else if (avg_rssi <= -60)
0992         val -= 0x10;
0993 
0994     if (val != mt7601u_bbp_rr(dev, 66))
0995         mt7601u_bbp_wr(dev, 66, val);
0996 
0997     /* TODO: also if lost a lot of beacons try resetting
0998      *       (see RTMPSetAGCInitValue() call in mlme.c).
0999      */
1000 }
1001 
1002 static void mt7601u_phy_calibrate(struct work_struct *work)
1003 {
1004     struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev,
1005                         cal_work.work);
1006 
1007     mt7601u_agc_tune(dev);
1008     mt7601u_tssi_cal(dev);
1009     /* If TSSI calibration was run it already updated temperature. */
1010     if (!dev->ee->tssi_enabled)
1011         dev->raw_temp = mt7601u_read_temp(dev);
1012     mt7601u_temp_comp(dev, true); /* TODO: find right value for @on */
1013 
1014     ieee80211_queue_delayed_work(dev->hw, &dev->cal_work,
1015                      MT_CALIBRATE_INTERVAL);
1016 }
1017 
1018 static unsigned long
1019 __mt7601u_phy_freq_cal(struct mt7601u_dev *dev, s8 last_offset, u8 phy_mode)
1020 {
1021     u8 activate_threshold, deactivate_threshold;
1022 
1023     trace_freq_cal_offset(dev, phy_mode, last_offset);
1024 
1025     /* No beacons received - reschedule soon */
1026     if (last_offset == MT_FREQ_OFFSET_INVALID)
1027         return MT_FREQ_CAL_ADJ_INTERVAL;
1028 
1029     switch (phy_mode) {
1030     case MT_PHY_TYPE_CCK:
1031         activate_threshold = 19;
1032         deactivate_threshold = 5;
1033         break;
1034     case MT_PHY_TYPE_OFDM:
1035         activate_threshold = 102;
1036         deactivate_threshold = 32;
1037         break;
1038     case MT_PHY_TYPE_HT:
1039     case MT_PHY_TYPE_HT_GF:
1040         activate_threshold = 82;
1041         deactivate_threshold = 20;
1042         break;
1043     default:
1044         WARN_ON(1);
1045         return MT_FREQ_CAL_CHECK_INTERVAL;
1046     }
1047 
1048     if (abs(last_offset) >= activate_threshold)
1049         dev->freq_cal.adjusting = true;
1050     else if (abs(last_offset) <= deactivate_threshold)
1051         dev->freq_cal.adjusting = false;
1052 
1053     if (!dev->freq_cal.adjusting)
1054         return MT_FREQ_CAL_CHECK_INTERVAL;
1055 
1056     if (last_offset > deactivate_threshold) {
1057         if (dev->freq_cal.freq > 0)
1058             dev->freq_cal.freq--;
1059         else
1060             dev->freq_cal.adjusting = false;
1061     } else if (last_offset < -deactivate_threshold) {
1062         if (dev->freq_cal.freq < 0xbf)
1063             dev->freq_cal.freq++;
1064         else
1065             dev->freq_cal.adjusting = false;
1066     }
1067 
1068     trace_freq_cal_adjust(dev, dev->freq_cal.freq);
1069     mt7601u_rf_wr(dev, 0, 12, dev->freq_cal.freq);
1070     mt7601u_vco_cal(dev);
1071 
1072     return dev->freq_cal.adjusting ? MT_FREQ_CAL_ADJ_INTERVAL :
1073                      MT_FREQ_CAL_CHECK_INTERVAL;
1074 }
1075 
1076 static void mt7601u_phy_freq_cal(struct work_struct *work)
1077 {
1078     struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev,
1079                            freq_cal.work.work);
1080     s8 last_offset;
1081     u8 phy_mode;
1082     unsigned long delay;
1083 
1084     spin_lock_bh(&dev->con_mon_lock);
1085     last_offset = dev->bcn_freq_off;
1086     phy_mode = dev->bcn_phy_mode;
1087     spin_unlock_bh(&dev->con_mon_lock);
1088 
1089     delay = __mt7601u_phy_freq_cal(dev, last_offset, phy_mode);
1090     ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, delay);
1091 
1092     spin_lock_bh(&dev->con_mon_lock);
1093     dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID;
1094     spin_unlock_bh(&dev->con_mon_lock);
1095 }
1096 
1097 void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev,
1098                    struct ieee80211_bss_conf *info)
1099 {
1100     struct ieee80211_vif *vif = container_of(info, struct ieee80211_vif,
1101                          bss_conf);
1102 
1103     if (!vif->cfg.assoc)
1104         cancel_delayed_work_sync(&dev->freq_cal.work);
1105 
1106     /* Start/stop collecting beacon data */
1107     spin_lock_bh(&dev->con_mon_lock);
1108     ether_addr_copy(dev->ap_bssid, info->bssid);
1109     ewma_rssi_init(&dev->avg_rssi);
1110     dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID;
1111     spin_unlock_bh(&dev->con_mon_lock);
1112 
1113     dev->freq_cal.freq = dev->ee->rf_freq_off;
1114     dev->freq_cal.enabled = vif->cfg.assoc;
1115     dev->freq_cal.adjusting = false;
1116 
1117     if (vif->cfg.assoc)
1118         ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work,
1119                          MT_FREQ_CAL_INIT_DELAY);
1120 }
1121 
1122 static int mt7601u_init_cal(struct mt7601u_dev *dev)
1123 {
1124     u32 mac_ctrl;
1125     int ret;
1126 
1127     dev->raw_temp = mt7601u_read_bootup_temp(dev);
1128     dev->curr_temp = (dev->raw_temp - dev->ee->ref_temp) *
1129         MT_EE_TEMPERATURE_SLOPE;
1130     dev->dpd_temp = dev->curr_temp;
1131 
1132     mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL);
1133 
1134     ret = mt7601u_mcu_calibrate(dev, MCU_CAL_R, 0);
1135     if (ret)
1136         return ret;
1137 
1138     ret = mt7601u_rf_rr(dev, 0, 4);
1139     if (ret < 0)
1140         return ret;
1141     ret |= 0x80;
1142     ret = mt7601u_rf_wr(dev, 0, 4, ret);
1143     if (ret)
1144         return ret;
1145     msleep(2);
1146 
1147     ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXDCOC, 0);
1148     if (ret)
1149         return ret;
1150 
1151     mt7601u_rxdc_cal(dev);
1152 
1153     ret = mt7601u_set_bw_filter(dev, true);
1154     if (ret)
1155         return ret;
1156     ret = mt7601u_mcu_calibrate(dev, MCU_CAL_LOFT, 0);
1157     if (ret)
1158         return ret;
1159     ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXIQ, 0);
1160     if (ret)
1161         return ret;
1162     ret = mt7601u_mcu_calibrate(dev, MCU_CAL_RXIQ, 0);
1163     if (ret)
1164         return ret;
1165     ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp);
1166     if (ret)
1167         return ret;
1168 
1169     mt7601u_rxdc_cal(dev);
1170 
1171     mt7601u_tssi_dc_gain_cal(dev);
1172 
1173     mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);
1174 
1175     mt7601u_temp_comp(dev, true);
1176 
1177     return 0;
1178 }
1179 
1180 int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw)
1181 {
1182     u32 val, old;
1183 
1184     if (bw == dev->bw) {
1185         /* Vendor driver does the rmc even when no change is needed. */
1186         mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10);
1187 
1188         return 0;
1189     }
1190     dev->bw = bw;
1191 
1192     /* Stop MAC for the time of bw change */
1193     old = mt7601u_rr(dev, MT_MAC_SYS_CTRL);
1194     val = old & ~(MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX);
1195     mt7601u_wr(dev, MT_MAC_SYS_CTRL, val);
1196     mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX | MT_MAC_STATUS_RX,
1197           0, 500000);
1198 
1199     mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10);
1200 
1201     mt7601u_wr(dev, MT_MAC_SYS_CTRL, old);
1202 
1203     return mt7601u_load_bbp_temp_table_bw(dev);
1204 }
1205 
1206 /**
1207  * mt7601u_set_rx_path - set rx path in BBP
1208  * @dev:    pointer to adapter structure
1209  * @path:   rx path to set values are 0-based
1210  */
1211 void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path)
1212 {
1213     mt7601u_bbp_rmw(dev, 3, 0x18, path << 3);
1214 }
1215 
1216 /**
1217  * mt7601u_set_tx_dac - set which tx DAC to use
1218  * @dev:    pointer to adapter structure
1219  * @dac:    DAC index, values are 0-based
1220  */
1221 void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 dac)
1222 {
1223     mt7601u_bbp_rmc(dev, 1, 0x18, dac << 3);
1224 }
1225 
1226 int mt7601u_phy_init(struct mt7601u_dev *dev)
1227 {
1228     int ret;
1229 
1230     dev->rf_pa_mode[0] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG0);
1231     dev->rf_pa_mode[1] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG1);
1232 
1233     ret = mt7601u_rf_wr(dev, 0, 12, dev->ee->rf_freq_off);
1234     if (ret)
1235         return ret;
1236     ret = mt7601u_write_reg_pairs(dev, 0, rf_central,
1237                       ARRAY_SIZE(rf_central));
1238     if (ret)
1239         return ret;
1240     ret = mt7601u_write_reg_pairs(dev, 0, rf_channel,
1241                       ARRAY_SIZE(rf_channel));
1242     if (ret)
1243         return ret;
1244     ret = mt7601u_write_reg_pairs(dev, 0, rf_vga, ARRAY_SIZE(rf_vga));
1245     if (ret)
1246         return ret;
1247 
1248     ret = mt7601u_init_cal(dev);
1249     if (ret)
1250         return ret;
1251 
1252     dev->prev_pwr_diff = 100;
1253 
1254     INIT_DELAYED_WORK(&dev->cal_work, mt7601u_phy_calibrate);
1255     INIT_DELAYED_WORK(&dev->freq_cal.work, mt7601u_phy_freq_cal);
1256 
1257     return 0;
1258 }
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